From: Tobias Weber <toweber86@gmail.com>
Date: Mon, 30 Apr 2018 07:50:16 +0000 (+0200)
Subject: adding additional if clause to generate data words without pause inbetween.
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=920dd10c9af9ddfb787a2ce48caa6e7c730ad3cb;p=trb3.git

adding additional if clause to generate data words without pause inbetween.
---

diff --git a/mupix/Mupix8/sources/Generator3.vhd b/mupix/Mupix8/sources/Generator3.vhd
index 1a2332d..8f3f5f2 100644
--- a/mupix/Mupix8/sources/Generator3.vhd
+++ b/mupix/Mupix8/sources/Generator3.vhd
@@ -15,9 +15,7 @@ use IEEE.NUMERIC_STD.ALL;
 
 entity Generator3 is
     generic(
-        constant iWIDTH : natural := 32
-    );
-    
+        iWIDTH : natural := 32);
     port(
         clk        : in std_logic;
         reset      : in std_logic;
@@ -82,7 +80,11 @@ begin
                             writeEn_int <= '1';
                             num_ctr     <= num_ctr + 1;
                             if num_ctr < unsigned(data_num) - 1 then
+                              if unsigned(data_pause) > 0 then
                                 data_fsm <= pause;
+                              else
+                                data_fsm <= gen;
+                              end if;
                             else
                                 data_fsm <= down;
                             end if;
@@ -115,8 +117,7 @@ begin
                             end if;
                         else
                             data_fsm <= idle;
-                        end if;
-                        
+                        end if;         
                 end case;
             end if;
             writeEn <= writeEn_int;
diff --git a/mupix/Mupix8/tb/DataGenTest.vhd b/mupix/Mupix8/tb/DataGenTest.vhd
new file mode 100644
index 0000000..74be8f2
--- /dev/null
+++ b/mupix/Mupix8/tb/DataGenTest.vhd
@@ -0,0 +1,74 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity GeneratorTest is
+end entity GeneratorTest;
+
+architecture sim of GeneratorTest is
+
+  component Generator3 is
+    generic (
+      iWIDTH : natural);
+    port (
+      clk        : in  std_logic;
+      reset      : in  std_logic;
+      start_gen  : in  std_logic;
+      data_num   : in  std_logic_vector(31 downto 0);
+      data_pause : in  std_logic_vector(31 downto 0);
+      data_down  : in  std_logic_vector(31 downto 0);
+      chan_sel   : in  std_logic_vector(1 downto 0);
+      data_out   : out std_logic_vector(iWIDTH - 1 downto 0);
+      writeEn    : out std_logic);
+  end component Generator3;
+
+  constant iWIDTH     : natural := 32;
+  constant clk_period : time    := 10 ns;
+
+  signal clk        : std_logic;
+  signal reset      : std_logic                     := '0';
+  signal start_gen  : std_logic                     := '0';
+  signal data_num   : std_logic_vector(31 downto 0) := (others => '0');
+  signal data_pause : std_logic_vector(31 downto 0) := (others => '0');
+  signal data_down  : std_logic_vector(31 downto 0) := (others => '0');
+  signal chan_sel   : std_logic_vector(1 downto 0)  := (others => '0');
+  signal data_out   : std_logic_vector(iWIDTH - 1 downto 0);
+  signal writeEn    : std_logic;
+
+begin
+
+  Generator3_1 : entity work.Generator3
+    generic map (
+      iWIDTH => iWIDTH)
+    port map (
+      clk        => clk,
+      reset      => reset,
+      start_gen  => start_gen,
+      data_num   => data_num,
+      data_pause => data_pause,
+      data_down  => data_down,
+      chan_sel   => chan_sel,
+      data_out   => data_out,
+      writeEn    => writeEn);
+
+  clock_gen : process is
+  begin  -- process clock_gen
+    clk <= '1';
+    wait for clk_period/2;
+    clk <= '0';
+    wait for clk_period/2;
+  end process clock_gen;
+
+  stimulus : process is
+  begin  -- process stimulus
+    wait for 100 ns;
+    data_num   <= x"0000000a";
+    data_pause <= x"00000001";
+    data_down  <= x"0000000b";
+    start_gen  <= '1';
+    wait for clk_period;
+    start_gen  <= '0';
+    wait;
+  end process stimulus;
+
+end architecture sim;