From: Jan Michel Date: Fri, 10 Aug 2018 09:52:25 +0000 (+0200) Subject: better handling for large number of inputs in input statistics module X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=92ca8e654f8246c2ffb7e4efdc7ec22f2d2ab46b;p=trb3.git better handling for large number of inputs in input statistics module --- diff --git a/base/code/input_statistics.vhd b/base/code/input_statistics.vhd index 8e872ec..6aa0bbe 100644 --- a/base/code/input_statistics.vhd +++ b/base/code/input_statistics.vhd @@ -29,21 +29,24 @@ end entity; architecture input_statistics_arch of input_statistics is constant LAST_FIFO_NUM : integer := (INPUTS-1) * (1-SINGLE_FIFO_ONLY); +constant input_above32 : integer := INPUTS / 32 - INPUTS / 64; +constant input_above64 : integer := INPUTS / 64 ; + signal inp_reg : std_logic_vector(INPUTS-1 downto 0); signal inp_reg_last : std_logic_vector(INPUTS-1 downto 0); signal inp_inv : std_logic_vector(INPUTS-1 downto 0); signal inp_stretch : std_logic_vector(INPUTS-1 downto 0); -signal inp_reg_95 : std_logic_vector(95 downto 0) := (others => '0'); +signal inp_reg_95 : std_logic_vector(31+32*(input_above32+input_above64) downto 0); --(95 downto 0) := (others => '0'); signal trigger_fifo, trigger_fifo_buf : std_logic; signal trigger_fifo_real, trigger_fifo_external : std_logic := '0'; -signal trigger_fifo_channel : integer range 0 to 31; +signal trigger_fifo_channel : integer range 0 to INPUTS-1; signal trigger_fifo_channel_enable : std_logic; signal reset_cnt : std_logic; signal timer_rst : std_logic; -signal enable : std_logic_vector(95 downto 0); -signal invert : std_logic_vector(95 downto 0); +signal enable : std_logic_vector(31+32*(input_above32+input_above64) downto 0); --(95 downto 0); +signal invert : std_logic_vector(31+32*(input_above32+input_above64) downto 0); --(95 downto 0); signal rate : unsigned(31 downto 0); signal fifo_cnt_in : std_logic_vector(17 downto 0); @@ -94,17 +97,16 @@ begin when x"0" => enable(31 downto 0) <= DATA_IN; when x"1" => invert(31 downto 0) <= DATA_IN; when x"2" => rate <= unsigned(DATA_IN); - timer_rst <= '1'; - when x"5" => enable(63 downto 32) <= DATA_IN; - when x"6" => invert(63 downto 32) <= DATA_IN; - when x"7" => enable(95 downto 64) <= DATA_IN; - when x"8" => invert(95 downto 64) <= DATA_IN; - + timer_rst <= '1'; + when x"5" => enable(32*input_above32+31 downto 32*input_above32) <= DATA_IN; + when x"6" => invert(32*input_above32+31 downto 32*input_above32) <= DATA_IN; + when x"7" => enable(64*input_above64+31 downto 64*input_above64) <= DATA_IN; + when x"8" => invert(64*input_above64+31 downto 64*input_above64) <= DATA_IN; when x"f" => trigger_fifo <= DATA_IN(0); - reset_cnt <= DATA_IN(1); - fifo_in_sel <= to_integer(unsigned(DATA_IN(20 downto 16))); - trigger_fifo_channel_enable <= DATA_IN(31); - trigger_fifo_channel <= to_integer(unsigned(DATA_IN(28 downto 24))); + reset_cnt <= DATA_IN(1); + fifo_in_sel <= to_integer(unsigned(DATA_IN(22 downto 16))); + trigger_fifo_channel_enable <= DATA_IN(31); + trigger_fifo_channel <= to_integer(unsigned(DATA_IN(30 downto 24))); when others => NACK_OUT <= '1'; ACK_OUT <= '0'; end case; else @@ -119,14 +121,14 @@ begin when x"2" => DATA_OUT <= std_logic_vector(rate); when x"3" => DATA_OUT <= std_logic_vector(timer); when x"4" => DATA_OUT <= status_reg; - when x"5" => DATA_OUT <= enable(63 downto 32); - when x"6" => DATA_OUT <= invert(63 downto 32); - when x"7" => DATA_OUT <= enable(95 downto 64); - when x"8" => DATA_OUT <= invert(95 downto 64); + when x"5" => DATA_OUT <= enable(32*input_above32+31 downto 32*input_above32); + when x"6" => DATA_OUT <= invert(32*input_above32+31 downto 32*input_above32); + when x"7" => DATA_OUT <= enable(64*input_above64+31 downto 64*input_above64); + when x"8" => DATA_OUT <= invert(64*input_above64+31 downto 64*input_above64); when x"c" => DATA_OUT <= (others => '0'); DATA_OUT <= inp_reg_95(31 downto 0); - when x"d" => DATA_OUT <= (others => '0'); DATA_OUT <= inp_reg_95(63 downto 32); - when x"e" => DATA_OUT <= (others => '0'); DATA_OUT <= inp_reg_95(95 downto 64); - when x"f" => DATA_OUT <= (others => '0'); DATA_OUT(20 downto 16) <= std_logic_vector(to_unsigned(fifo_in_sel,5)); + when x"d" => DATA_OUT <= (others => '0'); DATA_OUT <= inp_reg_95(32*input_above32+31 downto 32*input_above32); + when x"e" => DATA_OUT <= (others => '0'); DATA_OUT <= inp_reg_95(64*input_above64+31 downto 64*input_above64); + when x"f" => DATA_OUT <= (others => '0'); DATA_OUT(22 downto 16) <= std_logic_vector(to_unsigned(fifo_in_sel,7)); DATA_OUT(14 downto 8) <= std_logic_vector(to_unsigned(INPUTS,7)); DATA_OUT(15 downto 15) <= std_logic_vector(to_unsigned(SINGLE_FIFO_ONLY,1)); DATA_OUT(28 downto 24) <= std_logic_vector(to_unsigned(trigger_fifo_channel,5)); @@ -137,8 +139,8 @@ begin fifo_read(to_integer(unsigned(ADDR_IN(4 downto 0)))) <= '1'; fifo_select <= to_integer(unsigned(ADDR_IN(4 downto 0))); fifo_wait <= '1'; - elsif ADDR_IN(6 downto 5) = "10" and tmp < INPUTS then - DATA_OUT(23 downto 0) <= std_logic_vector(cnt(to_integer(unsigned(ADDR_IN(4 downto 0))))); + elsif ADDR_IN(6) = '1' and tmp < INPUTS then + DATA_OUT(23 downto 0) <= std_logic_vector(cnt(to_integer(unsigned(ADDR_IN(5 downto 0))))); ACK_OUT <= '1'; else NACK_OUT <= '1';