From: hadeshyp Date: Wed, 9 Apr 2008 10:18:28 +0000 (+0000) Subject: corrected bug in API, Jan X-Git-Tag: oldGBE~574 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=93e95f47603d4c8241149880ffa4849a2dd3c604;p=trbnet.git corrected bug in API, Jan --- diff --git a/trb_net16_api_base.vhd b/trb_net16_api_base.vhd index 2df0631..dc095e9 100644 --- a/trb_net16_api_base.vhd +++ b/trb_net16_api_base.vhd @@ -350,9 +350,15 @@ begin STAT_FIFO_TO_INT(11) <= fifo_to_int_read; STAT_FIFO_TO_INT(14) <= fifo_to_int_full; STAT_FIFO_TO_INT(15) <= fifo_to_int_empty; + STAT_FIFO_TO_INT(16) <= next_APL_DATAREADY_OUT; + STAT_FIFO_TO_INT(17) <= sbuf_to_apl_free; + STAT_FIFO_TO_INT(18) <= fifo_to_apl_read_before; + STAT_FIFO_TO_INT(19) <= fifo_to_apl_read; + STAT_FIFO_TO_INT(20) <= fifo_to_apl_empty; + STAT_FIFO_TO_INT(21) <= fifo_to_apl_write; STAT_FIFO_TO_INT(7 downto 4) <= (others => '0'); STAT_FIFO_TO_INT(13 downto 12) <= (others => '0'); - STAT_FIFO_TO_INT(25 downto 16) <= (others => '0'); + STAT_FIFO_TO_INT(25 downto 22) <= (others => '0'); STAT_FIFO_TO_INT(28 downto 26) <= state_bits_to_int; STAT_FIFO_TO_INT(31 downto 29) <= state_bits_to_apl; --------------------------------------- @@ -673,10 +679,10 @@ begin end if; when sa_MY_ADDR => if APL_WRITE_4_PACKETS = 0 then - next_APL_DATAREADY_OUT <= fifo_to_apl_read_before and (or_all(fifo_to_apl_packet_num_out)); + next_APL_DATAREADY_OUT <= fifo_to_apl_read_before and (or_all(fifo_to_apl_packet_num_out)) and sbuf_to_apl_free; throw_away <= not or_all(fifo_to_apl_packet_num_out); else - next_APL_DATAREADY_OUT <= fifo_to_apl_read_before; + next_APL_DATAREADY_OUT <= fifo_to_apl_read_before and sbuf_to_apl_free; end if; fifo_to_apl_read <= not fifo_to_apl_empty and not (fifo_to_apl_read_before and not sbuf_to_apl_free and not throw_away); if reg_APL_TYP_OUT = TYPE_TRM and reg_APL_PACKET_NUM_OUT = "11" and sbuf_to_apl_free = '1' then diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd index 320b5a6..a132fe2 100644 --- a/trb_net16_hub_base.vhd +++ b/trb_net16_hub_base.vhd @@ -439,6 +439,12 @@ end component; API_SEQNR_IN : in std_logic_vector (7 downto 0); MY_ADDRESS_OUT : out std_logic_vector(15 downto 0); + --Port to write Unique ID + IDRAM_DATA_IN : in std_logic_vector(15 downto 0); + IDRAM_DATA_OUT : out std_logic_vector(15 downto 0); + IDRAM_ADDR_IN : in std_logic_vector(2 downto 0); + IDRAM_WR_IN : in std_logic; + --Register in / out REGISTERS_IN : in std_logic_vector(REGISTER_WIDTH*2**(NUM_STAT_REGS)-1 downto 0); @@ -1141,6 +1147,11 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1'); MY_ADDRESS_OUT => HUB_ADDRESS, REGISTERS_IN => HC_STAT_REGS, REGISTERS_OUT => HC_CTRL_REGS, + --Port to write Unique ID + IDRAM_DATA_IN => (others => '0'), + IDRAM_DATA_OUT => open, + IDRAM_ADDR_IN => (others => '0'), + IDRAM_WR_IN => '0', DAT_ADDR_OUT => open, DAT_READ_ENABLE_OUT => open, DAT_WRITE_ENABLE_OUT=> open, diff --git a/trb_net16_hub_logic.vhd b/trb_net16_hub_logic.vhd index dac162f..fe6aeaa 100644 --- a/trb_net16_hub_logic.vhd +++ b/trb_net16_hub_logic.vhd @@ -175,6 +175,8 @@ architecture trb_net16_hub_logic_arch of trb_net16_hub_logic is signal comb_INIT_next_read : std_logic; signal reply_fsm_state : std_logic; + signal waiting_for_init_finish, next_waiting_for_init_finish : std_logic; + begin REPLY_HEADER_OUT <= (others => '0'); @@ -632,14 +634,14 @@ reading_last_hdr <= (others => '0'); reply_state_machine : process(REPLY_POOL_next_READ, current_state, packet_counter, send_reply_trm, SEQ_NR, REPLY_combined_trm_F1, REPLY_combined_trm_F2, comb_REPLY_muxed_DATAREADY, comb_REPLY_muxed_DATA, - comb_REPLY_muxed_PACKET_NUM) + comb_REPLY_muxed_PACKET_NUM, waiting_for_init_finish) begin release_locked <= '0'; next_state <= current_state; comb_REPLY_POOL_DATAREADY <= '0'; comb_REPLY_POOL_PACKET_NUM <= packet_counter; comb_REPLY_POOL_DATA <= (others => '0'); - + next_waiting_for_init_finish <= waiting_for_init_finish; if current_state = SENDING_DATA then comb_REPLY_POOL_DATAREADY <= comb_REPLY_muxed_DATAREADY; @@ -651,7 +653,12 @@ reading_last_hdr <= (others => '0'); end if; if current_state = SENDING_REPLY_TRM then - comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read; + comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read and not waiting_for_init_finish; + if waiting_for_init_finish = '1' and init_locked = '1' then + release_locked <= '1'; --release only when init has finished too + next_state <= SENDING_DATA; + next_waiting_for_init_finish <= '0'; + end if; case packet_counter is when "01" => comb_REPLY_POOL_DATA <= REPLY_combined_trm_F1; @@ -659,9 +666,11 @@ reading_last_hdr <= (others => '0'); comb_REPLY_POOL_DATA <= REPLY_combined_trm_F2; when "11" => comb_REPLY_POOL_DATA <= "0000" & SEQ_NR & "0000"; - if REPLY_POOL_next_read = '1' then - release_locked <= '1'; + if REPLY_POOL_next_read = '1' and (init_locked = '1') then + release_locked <= '1'; --release only when init has finished too next_state <= SENDING_DATA; + elsif init_locked = '0' then + next_waiting_for_init_finish <= '1'; end if; when others => comb_REPLY_POOL_DATA <= (others => '0'); @@ -681,9 +690,11 @@ reading_last_hdr <= (others => '0'); if RESET = '1' then current_state <= SENDING_DATA; REPLY_POOL_next_read <= '0'; + waiting_for_init_finish <= '0'; else current_state <= next_state; REPLY_POOL_next_read <= comb_REPLY_POOL_next_read; + waiting_for_init_finish <= next_waiting_for_init_finish; end if; end if; end process; diff --git a/trb_net16_regIO.vhd b/trb_net16_regIO.vhd index 338f003..9998237 100644 --- a/trb_net16_regIO.vhd +++ b/trb_net16_regIO.vhd @@ -10,7 +10,6 @@ use work.trb_net_std.all; --REGISTERS with highest bit set are writeable (CTRL), with highest bit unset are readonly (STAT) from outside and vice versa from inside --the highest address bit is not used to determine the data position inside REGISTER IN/OUT --REGISTER_IN is not registered again ---if DAT-Port is not used, set DAT_DATAREADY_IN to '1' @@ -58,9 +57,20 @@ entity trb_net16_regIO is API_RUN_IN : in std_logic; API_SEQNR_IN : in std_logic_vector (7 downto 0); + --Port to write Unique ID + IDRAM_DATA_IN : in std_logic_vector(15 downto 0); + IDRAM_DATA_OUT : out std_logic_vector(15 downto 0); + IDRAM_ADDR_IN : in std_logic_vector(2 downto 0); + IDRAM_WR_IN : in std_logic; + + MY_ADDRESS_OUT : out std_logic_vector(15 downto 0); - --Register in / out + --Common Register in / out +-- COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0); +-- COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0); + + --Custom Register in / out REGISTERS_IN : in std_logic_vector(REGISTER_WIDTH*2**(NUM_STAT_REGS)-1 downto 0); REGISTERS_OUT : out std_logic_vector(REGISTER_WIDTH*2**(NUM_CTRL_REGS)-1 downto 0); @@ -73,8 +83,9 @@ entity trb_net16_regIO is --if successful DAT_DATA_IN : in std_logic_vector(REGISTER_WIDTH-1 downto 0); DAT_DATAREADY_IN : in std_logic; - DAT_NO_MORE_DATA_IN : in std_logic + DAT_NO_MORE_DATA_IN : in std_logic; --To finish transmission, when reading from a fifo and it got empty + STAT : out std_logic_vector(31 downto 0) ); end entity; @@ -249,11 +260,11 @@ begin if API_PACKET_NUM_IN = "11" then next_HDR_F3 <= API_DATA_IN; case API_DATA_IN(3 downto 0) is - when "1000" => next_state <= ONE_READ; - when "1001" => next_state <= ONE_WRITE; - when "1010" => next_state <= MEM_READ; - when "1011" => next_state <= MEM_WRITE; - when "1111" => next_state <= ADDRESS_RECV; + when c_read_register_type => next_state <= ONE_READ; + when c_write_register_type => next_state <= ONE_WRITE; + when c_read_multiple_type => next_state <= MEM_READ; + when c_write_multiple_type => next_state <= MEM_WRITE; + when c_network_control_type => next_state <= ADDRESS_RECV; when others => next_state <= SEND_REPLY_SHORT_TRANSFER; end case; next_operation <= API_DATA_IN(3 downto 0); @@ -488,7 +499,11 @@ begin DAT_ADDR_OUT <= buf_DAT_ADDR_OUT; REGISTERS_OUT <= buf_REGISTERS_OUT; - + STAT(0) <= ADR_REJECTED; + STAT(1) <= ADR_READ_IN; + STAT(2) <= ADR_DATAREADY_OUT; + STAT(3) <= ADR_DATAREADY_IN; + STAT(31 downto 4) <= (others => '0'); process(current_state) begin