From: hadaq <hadaq>
Date: Wed, 20 Mar 2013 19:42:45 +0000 (+0000)
Subject: running so far, now implement TrbNet ch1 and ch2
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=9436b740a35ace3527ffbf46841bc05061408521;p=trb3.git

running so far, now implement TrbNet ch1 and ch2
---

diff --git a/nxyter/source/fifo_dc_8to32.vhd b/nxyter/source/fifo_dc_8to32.vhd
deleted file mode 100644
index 2ff5748..0000000
--- a/nxyter/source/fifo_dc_8to32.vhd
+++ /dev/null
@@ -1,1160 +0,0 @@
--- VHDL netlist generated by SCUBA Diamond_2.0_Production (151)
--- Module  Version: 5.4
---/usr/local/opt/lattice_diamond/diamond/2.0/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 512 -width 8 -depth 512 -rdata_width 32 -regout -no_enable -pe -1 -pf -1 -e 
-
--- Fri Oct 12 14:39:06 2012
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity fifo_dc_8to32 is
-    port (
-        Data: in  std_logic_vector(7 downto 0); 
-        WrClock: in  std_logic; 
-        RdClock: in  std_logic; 
-        WrEn: in  std_logic; 
-        RdEn: in  std_logic; 
-        Reset: in  std_logic; 
-        RPReset: in  std_logic; 
-        Q: out  std_logic_vector(31 downto 0); 
-        Empty: out  std_logic; 
-        Full: out  std_logic);
-end fifo_dc_8to32;
-
-architecture Structure of fifo_dc_8to32 is
-
-    -- internal signal declarations
-    signal invout_1: std_logic;
-    signal invout_0: std_logic;
-    signal wcount_r1: std_logic;
-    signal wcount_r0: std_logic;
-    signal w_g2b_xor_cluster_1: std_logic;
-    signal r_g2b_xor_cluster_1: std_logic;
-    signal w_gdata_0: std_logic;
-    signal w_gdata_1: std_logic;
-    signal w_gdata_2: std_logic;
-    signal w_gdata_3: std_logic;
-    signal w_gdata_4: std_logic;
-    signal w_gdata_5: std_logic;
-    signal w_gdata_6: std_logic;
-    signal w_gdata_7: std_logic;
-    signal w_gdata_8: std_logic;
-    signal wptr_0: std_logic;
-    signal wptr_1: std_logic;
-    signal wptr_2: std_logic;
-    signal wptr_3: std_logic;
-    signal wptr_4: std_logic;
-    signal wptr_5: std_logic;
-    signal wptr_6: std_logic;
-    signal wptr_7: std_logic;
-    signal wptr_8: std_logic;
-    signal wptr_9: std_logic;
-    signal r_gdata_0: std_logic;
-    signal r_gdata_1: std_logic;
-    signal r_gdata_2: std_logic;
-    signal r_gdata_3: std_logic;
-    signal r_gdata_4: std_logic;
-    signal r_gdata_5: std_logic;
-    signal r_gdata_6: std_logic;
-    signal rptr_0: std_logic;
-    signal rptr_1: std_logic;
-    signal rptr_2: std_logic;
-    signal rptr_3: std_logic;
-    signal rptr_4: std_logic;
-    signal rptr_5: std_logic;
-    signal rptr_6: std_logic;
-    signal rptr_7: std_logic;
-    signal w_gcount_0: std_logic;
-    signal w_gcount_1: std_logic;
-    signal w_gcount_2: std_logic;
-    signal w_gcount_3: std_logic;
-    signal w_gcount_4: std_logic;
-    signal w_gcount_5: std_logic;
-    signal w_gcount_6: std_logic;
-    signal w_gcount_7: std_logic;
-    signal w_gcount_8: std_logic;
-    signal w_gcount_9: std_logic;
-    signal r_gcount_0: std_logic;
-    signal r_gcount_1: std_logic;
-    signal r_gcount_2: std_logic;
-    signal r_gcount_3: std_logic;
-    signal r_gcount_4: std_logic;
-    signal r_gcount_5: std_logic;
-    signal r_gcount_6: std_logic;
-    signal r_gcount_7: std_logic;
-    signal w_gcount_r20: std_logic;
-    signal w_gcount_r0: std_logic;
-    signal w_gcount_r21: std_logic;
-    signal w_gcount_r1: std_logic;
-    signal w_gcount_r22: std_logic;
-    signal w_gcount_r2: std_logic;
-    signal w_gcount_r23: std_logic;
-    signal w_gcount_r3: std_logic;
-    signal w_gcount_r24: std_logic;
-    signal w_gcount_r4: std_logic;
-    signal w_gcount_r25: std_logic;
-    signal w_gcount_r5: std_logic;
-    signal w_gcount_r26: std_logic;
-    signal w_gcount_r6: std_logic;
-    signal w_gcount_r27: std_logic;
-    signal w_gcount_r7: std_logic;
-    signal w_gcount_r28: std_logic;
-    signal w_gcount_r8: std_logic;
-    signal w_gcount_r29: std_logic;
-    signal w_gcount_r9: std_logic;
-    signal r_gcount_w20: std_logic;
-    signal r_gcount_w0: std_logic;
-    signal r_gcount_w21: std_logic;
-    signal r_gcount_w1: std_logic;
-    signal r_gcount_w22: std_logic;
-    signal r_gcount_w2: std_logic;
-    signal r_gcount_w23: std_logic;
-    signal r_gcount_w3: std_logic;
-    signal r_gcount_w24: std_logic;
-    signal r_gcount_w4: std_logic;
-    signal r_gcount_w25: std_logic;
-    signal r_gcount_w5: std_logic;
-    signal r_gcount_w26: std_logic;
-    signal r_gcount_w6: std_logic;
-    signal r_gcount_w27: std_logic;
-    signal r_gcount_w7: std_logic;
-    signal empty_i: std_logic;
-    signal rRst: std_logic;
-    signal full_i: std_logic;
-    signal iwcount_0: std_logic;
-    signal iwcount_1: std_logic;
-    signal w_gctr_ci: std_logic;
-    signal iwcount_2: std_logic;
-    signal iwcount_3: std_logic;
-    signal co0: std_logic;
-    signal iwcount_4: std_logic;
-    signal iwcount_5: std_logic;
-    signal co1: std_logic;
-    signal iwcount_6: std_logic;
-    signal iwcount_7: std_logic;
-    signal co2: std_logic;
-    signal iwcount_8: std_logic;
-    signal iwcount_9: std_logic;
-    signal co4: std_logic;
-    signal wcount_9: std_logic;
-    signal co3: std_logic;
-    signal scuba_vhi: std_logic;
-    signal ircount_0: std_logic;
-    signal ircount_1: std_logic;
-    signal r_gctr_ci: std_logic;
-    signal ircount_2: std_logic;
-    signal ircount_3: std_logic;
-    signal co0_1: std_logic;
-    signal ircount_4: std_logic;
-    signal ircount_5: std_logic;
-    signal co1_1: std_logic;
-    signal ircount_6: std_logic;
-    signal ircount_7: std_logic;
-    signal co3_1: std_logic;
-    signal rcount_7: std_logic;
-    signal co2_1: std_logic;
-    signal rden_i: std_logic;
-    signal cmp_ci: std_logic;
-    signal wcount_r2: std_logic;
-    signal wcount_r3: std_logic;
-    signal rcount_0: std_logic;
-    signal rcount_1: std_logic;
-    signal co0_2: std_logic;
-    signal wcount_r4: std_logic;
-    signal wcount_r5: std_logic;
-    signal rcount_2: std_logic;
-    signal rcount_3: std_logic;
-    signal co1_2: std_logic;
-    signal w_g2b_xor_cluster_0: std_logic;
-    signal wcount_r7: std_logic;
-    signal rcount_4: std_logic;
-    signal rcount_5: std_logic;
-    signal co2_2: std_logic;
-    signal wcount_r8: std_logic;
-    signal empty_cmp_clr: std_logic;
-    signal rcount_6: std_logic;
-    signal empty_cmp_set: std_logic;
-    signal empty_d: std_logic;
-    signal empty_d_c: std_logic;
-    signal wren_i: std_logic;
-    signal cmp_ci_1: std_logic;
-    signal wcount_0: std_logic;
-    signal wcount_1: std_logic;
-    signal co0_3: std_logic;
-    signal rcount_w0: std_logic;
-    signal rcount_w1: std_logic;
-    signal wcount_2: std_logic;
-    signal wcount_3: std_logic;
-    signal co1_3: std_logic;
-    signal rcount_w2: std_logic;
-    signal rcount_w3: std_logic;
-    signal wcount_4: std_logic;
-    signal wcount_5: std_logic;
-    signal co2_3: std_logic;
-    signal r_g2b_xor_cluster_0: std_logic;
-    signal rcount_w5: std_logic;
-    signal wcount_6: std_logic;
-    signal wcount_7: std_logic;
-    signal co3_2: std_logic;
-    signal rcount_w6: std_logic;
-    signal full_cmp_clr: std_logic;
-    signal wcount_8: std_logic;
-    signal full_cmp_set: std_logic;
-    signal full_d: std_logic;
-    signal full_d_c: std_logic;
-    signal scuba_vlo: std_logic;
-
-    -- local component declarations
-    component AGEB2
-        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
-            B1: in  std_logic; CI: in  std_logic; GE: out  std_logic);
-    end component;
-    component AND2
-        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
-    end component;
-    component CU2
-        port (CI: in  std_logic; PC0: in  std_logic; PC1: in  std_logic; 
-            CO: out  std_logic; NC0: out  std_logic; NC1: out  std_logic);
-    end component;
-    component FADD2B
-        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
-            B1: in  std_logic; CI: in  std_logic; COUT: out  std_logic; 
-            S0: out  std_logic; S1: out  std_logic);
-    end component;
-    component FD1P3BX
-        port (D: in  std_logic; SP: in  std_logic; CK: in  std_logic; 
-            PD: in  std_logic; Q: out  std_logic);
-    end component;
-    component FD1P3DX
-        port (D: in  std_logic; SP: in  std_logic; CK: in  std_logic; 
-            CD: in  std_logic; Q: out  std_logic);
-    end component;
-    component FD1S3BX
-        port (D: in  std_logic; CK: in  std_logic; PD: in  std_logic; 
-            Q: out  std_logic);
-    end component;
-    component FD1S3DX
-        port (D: in  std_logic; CK: in  std_logic; CD: in  std_logic; 
-            Q: out  std_logic);
-    end component;
-    component INV
-        port (A: in  std_logic; Z: out  std_logic);
-    end component;
-    component OR2
-        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
-    end component;
-    component ROM16X1A
-        generic (INITVAL : in std_logic_vector(15 downto 0));
-        port (AD3: in  std_logic; AD2: in  std_logic; AD1: in  std_logic; 
-            AD0: in  std_logic; DO0: out  std_logic);
-    end component;
-    component VHI
-        port (Z: out  std_logic);
-    end component;
-    component VLO
-        port (Z: out  std_logic);
-    end component;
-    component XOR2
-        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
-    end component;
-    component DP16KC
-        generic (GSR : in String; WRITEMODE_B : in String; 
-                WRITEMODE_A : in String; CSDECODE_B : in String; 
-                CSDECODE_A : in String; REGMODE_B : in String; 
-                REGMODE_A : in String; DATA_WIDTH_B : in Integer; 
-                DATA_WIDTH_A : in Integer);
-        port (DIA0: in  std_logic; DIA1: in  std_logic; 
-            DIA2: in  std_logic; DIA3: in  std_logic; 
-            DIA4: in  std_logic; DIA5: in  std_logic; 
-            DIA6: in  std_logic; DIA7: in  std_logic; 
-            DIA8: in  std_logic; DIA9: in  std_logic; 
-            DIA10: in  std_logic; DIA11: in  std_logic; 
-            DIA12: in  std_logic; DIA13: in  std_logic; 
-            DIA14: in  std_logic; DIA15: in  std_logic; 
-            DIA16: in  std_logic; DIA17: in  std_logic; 
-            ADA0: in  std_logic; ADA1: in  std_logic; 
-            ADA2: in  std_logic; ADA3: in  std_logic; 
-            ADA4: in  std_logic; ADA5: in  std_logic; 
-            ADA6: in  std_logic; ADA7: in  std_logic; 
-            ADA8: in  std_logic; ADA9: in  std_logic; 
-            ADA10: in  std_logic; ADA11: in  std_logic; 
-            ADA12: in  std_logic; ADA13: in  std_logic; 
-            CEA: in  std_logic; CLKA: in  std_logic; OCEA: in  std_logic; 
-            WEA: in  std_logic; CSA0: in  std_logic; CSA1: in  std_logic; 
-            CSA2: in  std_logic; RSTA: in  std_logic; 
-            DIB0: in  std_logic; DIB1: in  std_logic; 
-            DIB2: in  std_logic; DIB3: in  std_logic; 
-            DIB4: in  std_logic; DIB5: in  std_logic; 
-            DIB6: in  std_logic; DIB7: in  std_logic; 
-            DIB8: in  std_logic; DIB9: in  std_logic; 
-            DIB10: in  std_logic; DIB11: in  std_logic; 
-            DIB12: in  std_logic; DIB13: in  std_logic; 
-            DIB14: in  std_logic; DIB15: in  std_logic; 
-            DIB16: in  std_logic; DIB17: in  std_logic; 
-            ADB0: in  std_logic; ADB1: in  std_logic; 
-            ADB2: in  std_logic; ADB3: in  std_logic; 
-            ADB4: in  std_logic; ADB5: in  std_logic; 
-            ADB6: in  std_logic; ADB7: in  std_logic; 
-            ADB8: in  std_logic; ADB9: in  std_logic; 
-            ADB10: in  std_logic; ADB11: in  std_logic; 
-            ADB12: in  std_logic; ADB13: in  std_logic; 
-            CEB: in  std_logic; CLKB: in  std_logic; OCEB: in  std_logic; 
-            WEB: in  std_logic; CSB0: in  std_logic; CSB1: in  std_logic; 
-            CSB2: in  std_logic; RSTB: in  std_logic; 
-            DOA0: out  std_logic; DOA1: out  std_logic; 
-            DOA2: out  std_logic; DOA3: out  std_logic; 
-            DOA4: out  std_logic; DOA5: out  std_logic; 
-            DOA6: out  std_logic; DOA7: out  std_logic; 
-            DOA8: out  std_logic; DOA9: out  std_logic; 
-            DOA10: out  std_logic; DOA11: out  std_logic; 
-            DOA12: out  std_logic; DOA13: out  std_logic; 
-            DOA14: out  std_logic; DOA15: out  std_logic; 
-            DOA16: out  std_logic; DOA17: out  std_logic; 
-            DOB0: out  std_logic; DOB1: out  std_logic; 
-            DOB2: out  std_logic; DOB3: out  std_logic; 
-            DOB4: out  std_logic; DOB5: out  std_logic; 
-            DOB6: out  std_logic; DOB7: out  std_logic; 
-            DOB8: out  std_logic; DOB9: out  std_logic; 
-            DOB10: out  std_logic; DOB11: out  std_logic; 
-            DOB12: out  std_logic; DOB13: out  std_logic; 
-            DOB14: out  std_logic; DOB15: out  std_logic; 
-            DOB16: out  std_logic; DOB17: out  std_logic);
-    end component;
-    attribute MEM_LPC_FILE : string; 
-    attribute MEM_INIT_FILE : string; 
-    attribute RESETMODE : string; 
-    attribute GSR : string; 
-    attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_dc_8to32.lpc";
-    attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is "";
-    attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC";
-    attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "fifo_dc_8to32.lpc";
-    attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is "";
-    attribute RESETMODE of pdp_ram_0_1_0 : label is "SYNC";
-    attribute GSR of FF_91 : label is "ENABLED";
-    attribute GSR of FF_90 : label is "ENABLED";
-    attribute GSR of FF_89 : label is "ENABLED";
-    attribute GSR of FF_88 : label is "ENABLED";
-    attribute GSR of FF_87 : label is "ENABLED";
-    attribute GSR of FF_86 : label is "ENABLED";
-    attribute GSR of FF_85 : label is "ENABLED";
-    attribute GSR of FF_84 : label is "ENABLED";
-    attribute GSR of FF_83 : label is "ENABLED";
-    attribute GSR of FF_82 : label is "ENABLED";
-    attribute GSR of FF_81 : label is "ENABLED";
-    attribute GSR of FF_80 : label is "ENABLED";
-    attribute GSR of FF_79 : label is "ENABLED";
-    attribute GSR of FF_78 : label is "ENABLED";
-    attribute GSR of FF_77 : label is "ENABLED";
-    attribute GSR of FF_76 : label is "ENABLED";
-    attribute GSR of FF_75 : label is "ENABLED";
-    attribute GSR of FF_74 : label is "ENABLED";
-    attribute GSR of FF_73 : label is "ENABLED";
-    attribute GSR of FF_72 : label is "ENABLED";
-    attribute GSR of FF_71 : label is "ENABLED";
-    attribute GSR of FF_70 : label is "ENABLED";
-    attribute GSR of FF_69 : label is "ENABLED";
-    attribute GSR of FF_68 : label is "ENABLED";
-    attribute GSR of FF_67 : label is "ENABLED";
-    attribute GSR of FF_66 : label is "ENABLED";
-    attribute GSR of FF_65 : label is "ENABLED";
-    attribute GSR of FF_64 : label is "ENABLED";
-    attribute GSR of FF_63 : label is "ENABLED";
-    attribute GSR of FF_62 : label is "ENABLED";
-    attribute GSR of FF_61 : label is "ENABLED";
-    attribute GSR of FF_60 : label is "ENABLED";
-    attribute GSR of FF_59 : label is "ENABLED";
-    attribute GSR of FF_58 : label is "ENABLED";
-    attribute GSR of FF_57 : label is "ENABLED";
-    attribute GSR of FF_56 : label is "ENABLED";
-    attribute GSR of FF_55 : label is "ENABLED";
-    attribute GSR of FF_54 : label is "ENABLED";
-    attribute GSR of FF_53 : label is "ENABLED";
-    attribute GSR of FF_52 : label is "ENABLED";
-    attribute GSR of FF_51 : label is "ENABLED";
-    attribute GSR of FF_50 : label is "ENABLED";
-    attribute GSR of FF_49 : label is "ENABLED";
-    attribute GSR of FF_48 : label is "ENABLED";
-    attribute GSR of FF_47 : label is "ENABLED";
-    attribute GSR of FF_46 : label is "ENABLED";
-    attribute GSR of FF_45 : label is "ENABLED";
-    attribute GSR of FF_44 : label is "ENABLED";
-    attribute GSR of FF_43 : label is "ENABLED";
-    attribute GSR of FF_42 : label is "ENABLED";
-    attribute GSR of FF_41 : label is "ENABLED";
-    attribute GSR of FF_40 : label is "ENABLED";
-    attribute GSR of FF_39 : label is "ENABLED";
-    attribute GSR of FF_38 : label is "ENABLED";
-    attribute GSR of FF_37 : label is "ENABLED";
-    attribute GSR of FF_36 : label is "ENABLED";
-    attribute GSR of FF_35 : label is "ENABLED";
-    attribute GSR of FF_34 : label is "ENABLED";
-    attribute GSR of FF_33 : label is "ENABLED";
-    attribute GSR of FF_32 : label is "ENABLED";
-    attribute GSR of FF_31 : label is "ENABLED";
-    attribute GSR of FF_30 : label is "ENABLED";
-    attribute GSR of FF_29 : label is "ENABLED";
-    attribute GSR of FF_28 : label is "ENABLED";
-    attribute GSR of FF_27 : label is "ENABLED";
-    attribute GSR of FF_26 : label is "ENABLED";
-    attribute GSR of FF_25 : label is "ENABLED";
-    attribute GSR of FF_24 : label is "ENABLED";
-    attribute GSR of FF_23 : label is "ENABLED";
-    attribute GSR of FF_22 : label is "ENABLED";
-    attribute GSR of FF_21 : label is "ENABLED";
-    attribute GSR of FF_20 : label is "ENABLED";
-    attribute GSR of FF_19 : label is "ENABLED";
-    attribute GSR of FF_18 : label is "ENABLED";
-    attribute GSR of FF_17 : label is "ENABLED";
-    attribute GSR of FF_16 : label is "ENABLED";
-    attribute GSR of FF_15 : label is "ENABLED";
-    attribute GSR of FF_14 : label is "ENABLED";
-    attribute GSR of FF_13 : label is "ENABLED";
-    attribute GSR of FF_12 : label is "ENABLED";
-    attribute GSR of FF_11 : label is "ENABLED";
-    attribute GSR of FF_10 : label is "ENABLED";
-    attribute GSR of FF_9 : label is "ENABLED";
-    attribute GSR of FF_8 : label is "ENABLED";
-    attribute GSR of FF_7 : label is "ENABLED";
-    attribute GSR of FF_6 : label is "ENABLED";
-    attribute GSR of FF_5 : label is "ENABLED";
-    attribute GSR of FF_4 : label is "ENABLED";
-    attribute GSR of FF_3 : label is "ENABLED";
-    attribute GSR of FF_2 : label is "ENABLED";
-    attribute GSR of FF_1 : label is "ENABLED";
-    attribute GSR of FF_0 : label is "ENABLED";
-    attribute syn_keep : boolean;
-
-begin
-    -- component instantiation statements
-    AND2_t18: AND2
-        port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
-    INV_1: INV
-        port map (A=>full_i, Z=>invout_1);
-
-    AND2_t17: AND2
-        port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
-    INV_0: INV
-        port map (A=>empty_i, Z=>invout_0);
-
-    OR2_t16: OR2
-        port map (A=>Reset, B=>RPReset, Z=>rRst);
-
-    XOR2_t15: XOR2
-        port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
-    XOR2_t14: XOR2
-        port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
-    XOR2_t13: XOR2
-        port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
-    XOR2_t12: XOR2
-        port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
-    XOR2_t11: XOR2
-        port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
-    XOR2_t10: XOR2
-        port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
-    XOR2_t9: XOR2
-        port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
-    XOR2_t8: XOR2
-        port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
-    XOR2_t7: XOR2
-        port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
-    XOR2_t6: XOR2
-        port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
-    XOR2_t5: XOR2
-        port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
-    XOR2_t4: XOR2
-        port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
-    XOR2_t3: XOR2
-        port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
-    XOR2_t2: XOR2
-        port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
-    XOR2_t1: XOR2
-        port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
-    XOR2_t0: XOR2
-        port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
-    LUT4_21: ROM16X1A
-        generic map (initval=> X"6996")
-        port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, 
-            AD1=>w_gcount_r28, AD0=>w_gcount_r29, 
-            DO0=>w_g2b_xor_cluster_0);
-
-    LUT4_20: ROM16X1A
-        generic map (initval=> X"6996")
-        port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, 
-            AD1=>w_gcount_r24, AD0=>w_gcount_r25, 
-            DO0=>w_g2b_xor_cluster_1);
-
-    LUT4_19: ROM16X1A
-        generic map (initval=> X"6996")
-        port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, AD1=>scuba_vlo, 
-            AD0=>scuba_vlo, DO0=>wcount_r8);
-
-    LUT4_18: ROM16X1A
-        generic map (initval=> X"6996")
-        port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, 
-            AD1=>w_gcount_r29, AD0=>scuba_vlo, DO0=>wcount_r7);
-
-    LUT4_17: ROM16X1A
-        generic map (initval=> X"6996")
-        port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, 
-            AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5);
-
-    LUT4_16: ROM16X1A
-        generic map (initval=> X"6996")
-        port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, 
-            AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4);
-
-    LUT4_15: ROM16X1A
-        generic map (initval=> X"6996")
-        port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, 
-            AD1=>w_gcount_r25, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r3);
-
-    LUT4_14: ROM16X1A
-        generic map (initval=> X"6996")
-        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
-            AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r2);
-
-    LUT4_13: ROM16X1A
-        generic map (initval=> X"6996")
-        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
-            AD1=>w_gcount_r21, AD0=>scuba_vlo, DO0=>wcount_r1);
-
-    LUT4_12: ROM16X1A
-        generic map (initval=> X"6996")
-        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
-            AD1=>w_gcount_r20, AD0=>w_gcount_r21, DO0=>wcount_r0);
-
-    LUT4_11: ROM16X1A
-        generic map (initval=> X"6996")
-        port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, 
-            AD1=>r_gcount_w26, AD0=>r_gcount_w27, 
-            DO0=>r_g2b_xor_cluster_0);
-
-    LUT4_10: ROM16X1A
-        generic map (initval=> X"6996")
-        port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, 
-            AD1=>r_gcount_w22, AD0=>r_gcount_w23, 
-            DO0=>r_g2b_xor_cluster_1);
-
-    LUT4_9: ROM16X1A
-        generic map (initval=> X"6996")
-        port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, AD1=>scuba_vlo, 
-            AD0=>scuba_vlo, DO0=>rcount_w6);
-
-    LUT4_8: ROM16X1A
-        generic map (initval=> X"6996")
-        port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, 
-            AD1=>r_gcount_w27, AD0=>scuba_vlo, DO0=>rcount_w5);
-
-    LUT4_7: ROM16X1A
-        generic map (initval=> X"6996")
-        port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, 
-            AD1=>r_gcount_w25, AD0=>rcount_w6, DO0=>rcount_w3);
-
-    LUT4_6: ROM16X1A
-        generic map (initval=> X"6996")
-        port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, 
-            AD1=>r_gcount_w24, AD0=>rcount_w5, DO0=>rcount_w2);
-
-    LUT4_5: ROM16X1A
-        generic map (initval=> X"6996")
-        port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, 
-            AD1=>r_gcount_w23, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w1);
-
-    LUT4_4: ROM16X1A
-        generic map (initval=> X"6996")
-        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
-            AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0);
-
-    LUT4_3: ROM16X1A
-        generic map (initval=> X"0410")
-        port map (AD3=>rptr_7, AD2=>rcount_7, AD1=>w_gcount_r29, 
-            AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
-    LUT4_2: ROM16X1A
-        generic map (initval=> X"1004")
-        port map (AD3=>rptr_7, AD2=>rcount_7, AD1=>w_gcount_r29, 
-            AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
-    LUT4_1: ROM16X1A
-        generic map (initval=> X"0140")
-        port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w27, 
-            AD0=>scuba_vlo, DO0=>full_cmp_set);
-
-    LUT4_0: ROM16X1A
-        generic map (initval=> X"4001")
-        port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w27, 
-            AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
-    pdp_ram_0_0_1: DP16KC
-        generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", 
-        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
-        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  18, 
-        DATA_WIDTH_A=>  4)
-        port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), 
-            DIA3=>Data(3), DIA4=>scuba_vlo, DIA5=>scuba_vlo, 
-            DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, 
-            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
-            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
-            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
-            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, 
-            ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, 
-            ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>scuba_vlo, 
-            ADA12=>scuba_vlo, ADA13=>scuba_vlo, CEA=>wren_i, 
-            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, 
-            CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, 
-            DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, 
-            DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, 
-            DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, 
-            DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, 
-            DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, 
-            DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, 
-            ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, 
-            ADB3=>scuba_vlo, ADB4=>rptr_0, ADB5=>rptr_1, ADB6=>rptr_2, 
-            ADB7=>rptr_3, ADB8=>rptr_4, ADB9=>rptr_5, ADB10=>rptr_6, 
-            ADB11=>scuba_vlo, ADB12=>scuba_vlo, ADB13=>scuba_vlo, 
-            CEB=>rden_i, CLKB=>RdClock, OCEB=>scuba_vhi, WEB=>scuba_vlo, 
-            CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, 
-            RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, 
-            DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, 
-            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, 
-            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, 
-            DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), 
-            DOB4=>Q(8), DOB5=>Q(9), DOB6=>Q(10), DOB7=>Q(11), DOB8=>open, 
-            DOB9=>Q(16), DOB10=>Q(17), DOB11=>Q(18), DOB12=>Q(19), 
-            DOB13=>Q(24), DOB14=>Q(25), DOB15=>Q(26), DOB16=>Q(27), 
-            DOB17=>open);
-
-    pdp_ram_0_1_0: DP16KC
-        generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", 
-        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
-        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  18, 
-        DATA_WIDTH_A=>  4)
-        port map (DIA0=>Data(4), DIA1=>Data(5), DIA2=>Data(6), 
-            DIA3=>Data(7), DIA4=>scuba_vlo, DIA5=>scuba_vlo, 
-            DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, 
-            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
-            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
-            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
-            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, 
-            ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, 
-            ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>scuba_vlo, 
-            ADA12=>scuba_vlo, ADA13=>scuba_vlo, CEA=>wren_i, 
-            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, 
-            CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, 
-            DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, 
-            DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, 
-            DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, 
-            DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, 
-            DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, 
-            DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, 
-            ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, 
-            ADB3=>scuba_vlo, ADB4=>rptr_0, ADB5=>rptr_1, ADB6=>rptr_2, 
-            ADB7=>rptr_3, ADB8=>rptr_4, ADB9=>rptr_5, ADB10=>rptr_6, 
-            ADB11=>scuba_vlo, ADB12=>scuba_vlo, ADB13=>scuba_vlo, 
-            CEB=>rden_i, CLKB=>RdClock, OCEB=>scuba_vhi, WEB=>scuba_vlo, 
-            CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, 
-            RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, 
-            DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, 
-            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, 
-            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, 
-            DOA17=>open, DOB0=>Q(4), DOB1=>Q(5), DOB2=>Q(6), DOB3=>Q(7), 
-            DOB4=>Q(12), DOB5=>Q(13), DOB6=>Q(14), DOB7=>Q(15), 
-            DOB8=>open, DOB9=>Q(20), DOB10=>Q(21), DOB11=>Q(22), 
-            DOB12=>Q(23), DOB13=>Q(28), DOB14=>Q(29), DOB15=>Q(30), 
-            DOB16=>Q(31), DOB17=>open);
-
-    FF_91: FD1P3BX
-        port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, 
-            Q=>wcount_0);
-
-    FF_90: FD1P3DX
-        port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>wcount_1);
-
-    FF_89: FD1P3DX
-        port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>wcount_2);
-
-    FF_88: FD1P3DX
-        port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>wcount_3);
-
-    FF_87: FD1P3DX
-        port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>wcount_4);
-
-    FF_86: FD1P3DX
-        port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>wcount_5);
-
-    FF_85: FD1P3DX
-        port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>wcount_6);
-
-    FF_84: FD1P3DX
-        port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>wcount_7);
-
-    FF_83: FD1P3DX
-        port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>wcount_8);
-
-    FF_82: FD1P3DX
-        port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>wcount_9);
-
-    FF_81: FD1P3DX
-        port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>w_gcount_0);
-
-    FF_80: FD1P3DX
-        port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>w_gcount_1);
-
-    FF_79: FD1P3DX
-        port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>w_gcount_2);
-
-    FF_78: FD1P3DX
-        port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>w_gcount_3);
-
-    FF_77: FD1P3DX
-        port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>w_gcount_4);
-
-    FF_76: FD1P3DX
-        port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>w_gcount_5);
-
-    FF_75: FD1P3DX
-        port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>w_gcount_6);
-
-    FF_74: FD1P3DX
-        port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>w_gcount_7);
-
-    FF_73: FD1P3DX
-        port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>w_gcount_8);
-
-    FF_72: FD1P3DX
-        port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>w_gcount_9);
-
-    FF_71: FD1P3DX
-        port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>wptr_0);
-
-    FF_70: FD1P3DX
-        port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>wptr_1);
-
-    FF_69: FD1P3DX
-        port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>wptr_2);
-
-    FF_68: FD1P3DX
-        port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>wptr_3);
-
-    FF_67: FD1P3DX
-        port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>wptr_4);
-
-    FF_66: FD1P3DX
-        port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>wptr_5);
-
-    FF_65: FD1P3DX
-        port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>wptr_6);
-
-    FF_64: FD1P3DX
-        port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>wptr_7);
-
-    FF_63: FD1P3DX
-        port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>wptr_8);
-
-    FF_62: FD1P3DX
-        port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, 
-            Q=>wptr_9);
-
-    FF_61: FD1P3BX
-        port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, 
-            Q=>rcount_0);
-
-    FF_60: FD1P3DX
-        port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>rcount_1);
-
-    FF_59: FD1P3DX
-        port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>rcount_2);
-
-    FF_58: FD1P3DX
-        port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>rcount_3);
-
-    FF_57: FD1P3DX
-        port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>rcount_4);
-
-    FF_56: FD1P3DX
-        port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>rcount_5);
-
-    FF_55: FD1P3DX
-        port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>rcount_6);
-
-    FF_54: FD1P3DX
-        port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>rcount_7);
-
-    FF_53: FD1P3DX
-        port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>r_gcount_0);
-
-    FF_52: FD1P3DX
-        port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>r_gcount_1);
-
-    FF_51: FD1P3DX
-        port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>r_gcount_2);
-
-    FF_50: FD1P3DX
-        port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>r_gcount_3);
-
-    FF_49: FD1P3DX
-        port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>r_gcount_4);
-
-    FF_48: FD1P3DX
-        port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>r_gcount_5);
-
-    FF_47: FD1P3DX
-        port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>r_gcount_6);
-
-    FF_46: FD1P3DX
-        port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>r_gcount_7);
-
-    FF_45: FD1P3DX
-        port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>rptr_0);
-
-    FF_44: FD1P3DX
-        port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>rptr_1);
-
-    FF_43: FD1P3DX
-        port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>rptr_2);
-
-    FF_42: FD1P3DX
-        port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>rptr_3);
-
-    FF_41: FD1P3DX
-        port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>rptr_4);
-
-    FF_40: FD1P3DX
-        port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>rptr_5);
-
-    FF_39: FD1P3DX
-        port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>rptr_6);
-
-    FF_38: FD1P3DX
-        port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, 
-            Q=>rptr_7);
-
-    FF_37: FD1S3DX
-        port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
-    FF_36: FD1S3DX
-        port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
-    FF_35: FD1S3DX
-        port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
-    FF_34: FD1S3DX
-        port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
-    FF_33: FD1S3DX
-        port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
-    FF_32: FD1S3DX
-        port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
-    FF_31: FD1S3DX
-        port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
-    FF_30: FD1S3DX
-        port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
-    FF_29: FD1S3DX
-        port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
-    FF_28: FD1S3DX
-        port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
-    FF_27: FD1S3DX
-        port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
-    FF_26: FD1S3DX
-        port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
-    FF_25: FD1S3DX
-        port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
-    FF_24: FD1S3DX
-        port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
-    FF_23: FD1S3DX
-        port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
-    FF_22: FD1S3DX
-        port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
-    FF_21: FD1S3DX
-        port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
-    FF_20: FD1S3DX
-        port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
-    FF_19: FD1S3DX
-        port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, 
-            Q=>w_gcount_r20);
-
-    FF_18: FD1S3DX
-        port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, 
-            Q=>w_gcount_r21);
-
-    FF_17: FD1S3DX
-        port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, 
-            Q=>w_gcount_r22);
-
-    FF_16: FD1S3DX
-        port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, 
-            Q=>w_gcount_r23);
-
-    FF_15: FD1S3DX
-        port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, 
-            Q=>w_gcount_r24);
-
-    FF_14: FD1S3DX
-        port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, 
-            Q=>w_gcount_r25);
-
-    FF_13: FD1S3DX
-        port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, 
-            Q=>w_gcount_r26);
-
-    FF_12: FD1S3DX
-        port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, 
-            Q=>w_gcount_r27);
-
-    FF_11: FD1S3DX
-        port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, 
-            Q=>w_gcount_r28);
-
-    FF_10: FD1S3DX
-        port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, 
-            Q=>w_gcount_r29);
-
-    FF_9: FD1S3DX
-        port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
-    FF_8: FD1S3DX
-        port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
-    FF_7: FD1S3DX
-        port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
-    FF_6: FD1S3DX
-        port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
-    FF_5: FD1S3DX
-        port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
-    FF_4: FD1S3DX
-        port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
-    FF_3: FD1S3DX
-        port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
-    FF_2: FD1S3DX
-        port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
-    FF_1: FD1S3BX
-        port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
-    FF_0: FD1S3DX
-        port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
-    w_gctr_cia: FADD2B
-        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
-            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, 
-            S1=>open);
-
-    w_gctr_0: CU2
-        port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, 
-            NC0=>iwcount_0, NC1=>iwcount_1);
-
-    w_gctr_1: CU2
-        port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, 
-            NC0=>iwcount_2, NC1=>iwcount_3);
-
-    w_gctr_2: CU2
-        port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, 
-            NC0=>iwcount_4, NC1=>iwcount_5);
-
-    w_gctr_3: CU2
-        port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, 
-            NC0=>iwcount_6, NC1=>iwcount_7);
-
-    w_gctr_4: CU2
-        port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, 
-            NC0=>iwcount_8, NC1=>iwcount_9);
-
-    scuba_vhi_inst: VHI
-        port map (Z=>scuba_vhi);
-
-    r_gctr_cia: FADD2B
-        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
-            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, 
-            S1=>open);
-
-    r_gctr_0: CU2
-        port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, 
-            NC0=>ircount_0, NC1=>ircount_1);
-
-    r_gctr_1: CU2
-        port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, 
-            NC0=>ircount_2, NC1=>ircount_3);
-
-    r_gctr_2: CU2
-        port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, 
-            NC0=>ircount_4, NC1=>ircount_5);
-
-    r_gctr_3: CU2
-        port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, 
-            NC0=>ircount_6, NC1=>ircount_7);
-
-    empty_cmp_ci_a: FADD2B
-        port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, 
-            CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
-    empty_cmp_0: AGEB2
-        port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r2, 
-            B1=>wcount_r3, CI=>cmp_ci, GE=>co0_2);
-
-    empty_cmp_1: AGEB2
-        port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r4, 
-            B1=>wcount_r5, CI=>co0_2, GE=>co1_2);
-
-    empty_cmp_2: AGEB2
-        port map (A0=>rcount_4, A1=>rcount_5, B0=>w_g2b_xor_cluster_0, 
-            B1=>wcount_r7, CI=>co1_2, GE=>co2_2);
-
-    empty_cmp_3: AGEB2
-        port map (A0=>rcount_6, A1=>empty_cmp_set, B0=>wcount_r8, 
-            B1=>empty_cmp_clr, CI=>co2_2, GE=>empty_d_c);
-
-    a0: FADD2B
-        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
-            B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, 
-            S1=>open);
-
-    full_cmp_ci_a: FADD2B
-        port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, 
-            CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
-    full_cmp_0: AGEB2
-        port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, 
-            B1=>scuba_vlo, CI=>cmp_ci_1, GE=>co0_3);
-
-    full_cmp_1: AGEB2
-        port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w0, 
-            B1=>rcount_w1, CI=>co0_3, GE=>co1_3);
-
-    full_cmp_2: AGEB2
-        port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w2, 
-            B1=>rcount_w3, CI=>co1_3, GE=>co2_3);
-
-    full_cmp_3: AGEB2
-        port map (A0=>wcount_6, A1=>wcount_7, B0=>r_g2b_xor_cluster_0, 
-            B1=>rcount_w5, CI=>co2_3, GE=>co3_2);
-
-    full_cmp_4: AGEB2
-        port map (A0=>wcount_8, A1=>full_cmp_set, B0=>rcount_w6, 
-            B1=>full_cmp_clr, CI=>co3_2, GE=>full_d_c);
-
-    scuba_vlo_inst: VLO
-        port map (Z=>scuba_vlo);
-
-    a1: FADD2B
-        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
-            B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, 
-            S1=>open);
-
-    Empty <= empty_i;
-    Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of fifo_dc_8to32 is
-    for Structure
-        for all:AGEB2 use entity ecp3.AGEB2(V); end for;
-        for all:AND2 use entity ecp3.AND2(V); end for;
-        for all:CU2 use entity ecp3.CU2(V); end for;
-        for all:FADD2B use entity ecp3.FADD2B(V); end for;
-        for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
-        for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
-        for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
-        for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
-        for all:INV use entity ecp3.INV(V); end for;
-        for all:OR2 use entity ecp3.OR2(V); end for;
-        for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
-        for all:VHI use entity ecp3.VHI(V); end for;
-        for all:VLO use entity ecp3.VLO(V); end for;
-        for all:XOR2 use entity ecp3.XOR2(V); end for;
-        for all:DP16KC use entity ecp3.DP16KC(V); end for;
-    end for;
-end Structure_CON;
-
--- synopsys translate_on
diff --git a/nxyter/source/nx_data_buffer.vhd b/nxyter/source/nx_data_buffer.vhd
index 51eddeb..18f3899 100644
--- a/nxyter/source/nx_data_buffer.vhd
+++ b/nxyter/source/nx_data_buffer.vhd
@@ -12,12 +12,8 @@ entity nx_data_buffer is
 
     -- Data Buffer FIFO
     DATA_IN              : in std_logic_vector(31 downto 0);
-    NEW_DATA_IN          : in std_logic;
+    DATA_CLK_IN          : in std_logic;
 
-    -- Control
-    FIFO_WRITE_ENABLE_IN : in std_logic;
-    FIFO_READ_ENABLE_IN  : in std_logic;
-    
     -- Slave bus         
     SLV_READ_IN          : in  std_logic;
     SLV_WRITE_IN         : in  std_logic;
@@ -38,7 +34,6 @@ architecture Behavioral of nx_data_buffer is
   signal fifo_next_word     : std_logic_vector(31 downto 0);
   signal fifo_full          : std_logic;
   signal fifo_write_enable  : std_logic;
-  signal fifo_fill          : std_logic;
   
   -- FIFO Read Handler
   signal fifo_o             : std_logic_vector(31 downto 0);
@@ -72,14 +67,13 @@ architecture Behavioral of nx_data_buffer is
   signal slv_ack_o             : std_logic;
 
   signal register_fifo_status  : std_logic_vector(31 downto 0);
-  signal register_write_enable : std_logic;
 
   signal data_wait             : std_logic;
 
 begin
 
   DEBUG_OUT(0)     <= CLK_IN;
-  DEBUG_OUT(1)     <= fifo_fill;
+  DEBUG_OUT(1)     <= '0';
   DEBUG_OUT(2)     <= data_wait;
   DEBUG_OUT(3)     <= fifo_read_done;
   DEBUG_OUT(4)     <= fifo_read_busy;
@@ -114,23 +108,15 @@ begin
     if(rising_edge(CLK_IN)) then
       if(RESET_IN = '1') then
         fifo_write_enable  <= '0';
-        fifo_fill          <= '0';
       else
         fifo_write_enable <= '0';
         fifo_next_word    <= x"deadbeef";
         
-        if (NEW_DATA_IN = '1' and fifo_fill = '1') then
+        if (DATA_CLK_IN = '1' and fifo_full = '0') then
           fifo_next_word    <= DATA_IN;
           fifo_write_enable <= '1';
         end if;
         
-        if (fifo_empty = '1') then
-          fifo_fill <= '1';
-        end if;
-
-        if (fifo_full = '1') then
-          fifo_fill <= '0';
-        end if;
       end if;
     end if;
   end process PROC_FIFO_WRITE_HANDLER;
@@ -225,7 +211,6 @@ begin
         slv_ack_o             <= '0';
         slv_unknown_addr_o    <= '0';
         slv_no_more_data_o    <= '0';
-        register_write_enable <= '0';
 
         fifo_read_start       <= '0';
         data_wait             <= '0';
@@ -268,10 +253,6 @@ begin
             
         elsif (SLV_WRITE_IN  = '1') then
           case SLV_ADDR_IN is
-            when x"0001" =>
-              register_write_enable <= SLV_DATA_IN(0);
-              slv_ack_o <= '1';
-
             when others  =>
               slv_unknown_addr_o <= '1';              
               slv_ack_o <= '0';
diff --git a/nxyter/source/nx_timer.vhd b/nxyter/source/nx_timer.vhd
index 7d91274..b21963f 100644
--- a/nxyter/source/nx_timer.vhd
+++ b/nxyter/source/nx_timer.vhd
@@ -55,28 +55,33 @@ begin
 
     timer_done_o_x <= '0';
 
-    case STATE is
-      when S_IDLE =>
-        if (TIMER_START_IN = 0) then
-          NEXT_STATE <= S_IDLE;
-        else
-          timer_ctr_x <= TIMER_START_IN;
-          NEXT_STATE <= S_COUNT;
-        end if;
+    if (TIMER_START_IN > 0) then
+      timer_ctr_x <= TIMER_START_IN;
+      NEXT_STATE  <= S_COUNT;
+    else
+      case STATE is
+        when S_IDLE =>
+          if (TIMER_START_IN = 0) then
+            NEXT_STATE <= S_IDLE;
+          else
+            timer_ctr_x <= TIMER_START_IN;
+            NEXT_STATE  <= S_COUNT;
+          end if;
         
-      when S_COUNT =>
-        if (timer_ctr > 0) then
-          timer_ctr_x <= timer_ctr - 1;
-          NEXT_STATE <= S_COUNT;
-        else
-          NEXT_STATE <= S_DONE;
-        end if;
+        when S_COUNT =>
+          if (timer_ctr > 0) then
+            timer_ctr_x <= timer_ctr - 1;
+            NEXT_STATE  <= S_COUNT;
+          else
+            NEXT_STATE  <= S_DONE;
+          end if;
         
-      when S_DONE =>
-        timer_done_o_x <= '1';
-        NEXT_STATE <= S_IDLE;
-        
-    end case;
+        when S_DONE =>
+          timer_done_o_x <= '1';
+          NEXT_STATE     <= S_IDLE;
+
+      end case;
+    end if;
   end process PROC_TIMER;
   
   -----------------------------------------------------------------------------
diff --git a/nxyter/source/nx_timestamp_decode.vhd b/nxyter/source/nx_timestamp_decode.vhd
index 277df30..c2a42c3 100644
--- a/nxyter/source/nx_timestamp_decode.vhd
+++ b/nxyter/source/nx_timestamp_decode.vhd
@@ -14,13 +14,14 @@ entity nx_timestamp_decode is
     -- Inputs
     NX_NEW_TIMESTAMP_IN  : in  std_logic;
     NX_TIMESTAMP_IN      : in  std_logic_vector(31 downto 0);
-    TIMESTAMP_REF_IN     : in  unsigned(11 downto 0);
 
     -- Outputs
-    TIMESTAMP_DATA_OUT   : out std_logic_vector(31 downto 0);
+    TIMESTAMP_OUT        : out unsigned(13 downto 0);
+    CHANNEL_OUT          : out unsigned(6 downto 0);
+    TIMESTAMP_STATUS_OUT : out std_logic_vector(1 downto 0);
     TIMESTAMP_VALID_OUT  : out std_logic;
-    NX_TOKEN_RETURN      : out std_logic;
-    NX_NOMORE_DATA       : out std_logic;
+    NX_TOKEN_RETURN_OUT  : out std_logic;
+    NX_NOMORE_DATA_OUT   : out std_logic;
 
     -- Slave bus         
     SLV_READ_IN          : in  std_logic;
@@ -39,10 +40,6 @@ end entity;
 
 architecture Behavioral of nx_timestamp_decode is
   
-  -- Sync Ref
-  signal timestamp_ref_x      : unsigned(11 downto 0);
-  signal timestamp_ref        : unsigned(11 downto 0);
-
   -- Gray Decoder
   signal nx_timestamp         : std_logic_vector(13 downto 0);
   signal nx_channel_id        : std_logic_vector( 6 downto 0);
@@ -56,16 +53,22 @@ architecture Behavioral of nx_timestamp_decode is
   signal timstamp_raw         : std_logic_vector(31 downto 0);
   
   -- Validate Timestamp
-  signal timestamp_data_o     : std_logic_vector(31 downto 0);
+  signal timestamp_o          : unsigned(13 downto 0);
+  signal channel_o            : unsigned(6 downto 0);
+  signal timestamp_status_o   : std_logic_vector(1 downto 0);
   signal timestamp_valid_o    : std_logic;
+
+  signal nx_notempty_ctr      : unsigned (1 downto 0);  
   signal nx_token_return_o    : std_logic;
   signal nx_nomore_data_o     : std_logic;
-  signal nx_data_notvalid_ctr : unsigned(1 downto 0);
+  
   signal invalid_frame_ctr    : unsigned(15 downto 0);
   signal overflow_ctr         : unsigned(15 downto 0);
   signal pileup_ctr           : unsigned(15 downto 0);
   signal parity_error_ctr     : unsigned(15 downto 0);
-  
+  signal nx_valid_ctr         : unsigned(19 downto 0);
+  signal nx_rate_timer        : unsigned(19 downto 0);
+
   -- Config
   signal readout_type         : std_logic_vector(1 downto 0);
 
@@ -75,9 +78,7 @@ architecture Behavioral of nx_timestamp_decode is
   signal slv_unknown_addr_o   : std_logic;
   signal slv_ack_o            : std_logic;
   signal clear_counters       : std_logic;
-  signal trigger_window_width : unsigned(13 downto 0);
-  signal trigger_window_delay : unsigned(13 downto 0);
-  signal readout_mode         : std_logic_vector(1 downto 0);
+  signal nx_trigger_rate      : unsigned(19 downto 0);
 
 begin
 
@@ -87,7 +88,6 @@ begin
   DEBUG_OUT(2)                    <= TIMESTAMP_VALID_OUT;
   DEBUG_OUT(3)                    <= new_timestamp;
   DEBUG_OUT(5 downto 4)           <= status_bits;
-
   DEBUG_OUT(6)                    <= parity;
   DEBUG_OUT(7)                    <= '0';
   
@@ -121,20 +121,6 @@ begin
       BINARY_OUT => nx_channel_id
       );
 
-  -- Sync Timestamp Ref
-  PROC_SYNC_TIMESTAMP_REF: process (CLK_IN)
-  begin
-    if( rising_edge(CLK_IN) ) then
-      if (RESET_IN = '1') then
-        timestamp_ref_x <= (others => '0');
-        timestamp_ref   <= (others => '0');
-      else
-        timestamp_ref_x <= TIMESTAMP_REF_IN;
-        timestamp_ref   <= timestamp_ref_x;
-      end if;
-    end if;
-  end process PROC_SYNC_TIMESTAMP_REF;
-  
   -- Separate Status-, Parity- and Frame-bits, calculate parity
   PROC_TIMESTAMP_BITS: process (CLK_IN)
     variable parity_bits : std_logic_vector(22 downto 0);
@@ -180,36 +166,40 @@ begin
   -----------------------------------------------------------------------------
 
   PROC_VALIDATE_TIMESTAMP: process (CLK_IN)
-    variable ref    : unsigned(13 downto 0);
-    variable deltaT : unsigned(13 downto 0);
   begin 
     if( rising_edge(CLK_IN) ) then
       if (RESET_IN = '1') then
-        timestamp_data_o     <= (others => '0');
+        timestamp_o          <= (others => '0');
+        channel_o            <= (others => '0');
+        timestamp_status_o   <= (others => '0');
         timestamp_valid_o    <= '0';
+        nx_notempty_ctr      <= (others => '0');
         nx_token_return_o    <= '0';
         nx_nomore_data_o     <= '1';
-        nx_data_notvalid_ctr <= (others => '0');
+
         invalid_frame_ctr    <= (others => '0');
         overflow_ctr         <= (others => '0');
         pileup_ctr           <= (others => '0');
         parity_error_ctr     <= (others => '0');
+        nx_valid_ctr         <= (others => '0');
+        nx_trigger_rate      <= (others => '0');
+        nx_rate_timer        <= (others => '0');
       else
-        timestamp_data_o(31 downto 0)  <= (others => '0');
-        timestamp_valid_o              <= '0';
-        nx_token_return_o              <= '0';
-        nx_nomore_data_o               <= '0';
+        timestamp_o          <= (others => '0');
+        channel_o            <= (others => '0');
+        timestamp_status_o   <= (others => '0');
+        timestamp_valid_o    <= '0';
+        nx_token_return_o    <= '0';
+        nx_nomore_data_o     <= '0';
     
         if (new_timestamp = '1') then
           case valid_frame_bits is
             when "1000" =>
               ---- Check Overflow
-              if (status_bits(0) = '1') then
-                if (clear_counters = '0') then
-                  overflow_ctr <= overflow_ctr + 1;
-                end if;
+              if ((status_bits(0) = '1') and (clear_counters = '0')) then
+                overflow_ctr <= overflow_ctr + 1;
               end if;
-
+              
               ---- Check Parity
               if ((parity_bit /= parity) and (clear_counters = '0')) then
                 parity_error_ctr <= parity_error_ctr + 1;
@@ -221,51 +211,28 @@ begin
               end if;
               
               -- Take Timestamp
-              ref                 := timestamp_ref & "00";
-              deltaT              := ref - unsigned(nx_timestamp);
-              
-              case readout_mode is
-                
-                when "00" => 
-                  -- Raw
-                  timestamp_data_o(13 downto  0)   <= nx_timestamp;  
-                  timestamp_valid_o                <= '1';
-                
-                when "01" =>
-                  -- Ref
-                  timestamp_data_o(13 downto  0)   <= std_logic_vector(deltaT);
-                  timestamp_valid_o                <= '1';
-
-                when "10" =>
-                  -- Trigger Window
-                  if ((deltaT < trigger_window_delay) and
-                      (deltaT > (trigger_window_delay - trigger_window_width)))
-                  then
-                    timestamp_data_o(13 downto  0) <= std_logic_vector(deltaT);
-                    timestamp_valid_o              <= '1';
-                  end if;
-
-                when others => null;
-              end case;
+              timestamp_o          <= unsigned(nx_timestamp);
+              channel_o            <= unsigned(nx_channel_id);
+              timestamp_status_o   <= status_bits;
+              timestamp_valid_o    <= '1';
               
-              timestamp_data_o(15 downto 14) <= (others => '0');
-              timestamp_data_o(22 downto 16) <= nx_channel_id;
-              timestamp_data_o(23)           <= '0';
-              timestamp_data_o(24)           <= parity_bit;
-              timestamp_data_o(25)           <= parity;
-              timestamp_data_o(29 downto 26) <= (others => '0');
-              timestamp_data_o(31 downto 30) <= status_bits;
+              nx_notempty_ctr      <= (others => '0');
 
-              nx_data_notvalid_ctr           <= (others => '0');
+              -- Rate Counter
+              if (nx_rate_timer < x"186a0") then
+                nx_valid_ctr  <= nx_valid_ctr + 1;
+              end if;
                 
             when "0000" =>
-              case nx_data_notvalid_ctr is
+              case nx_notempty_ctr is
                 when "00"   =>
-                  nx_token_return_o    <= '1';
-                  nx_data_notvalid_ctr <= nx_data_notvalid_ctr + 1;
+                  nx_token_return_o <= '1';
+                  nx_notempty_ctr   <= nx_notempty_ctr + 1;
+
                 when "01"   =>
-                  nx_nomore_data_o     <= '1';
-                  nx_data_notvalid_ctr <= nx_data_notvalid_ctr + 1;
+                  nx_nomore_data_o  <= '1';
+                  nx_notempty_ctr   <= nx_notempty_ctr + 1;
+                  
                 when others => null;
               end case;
               
@@ -274,9 +241,19 @@ begin
               if (clear_counters = '0') then
                 invalid_frame_ctr <= invalid_frame_ctr + 1;
               end if;
+              nx_notempty_ctr      <= (others => '0');
           end case;
         end if;
 
+        -- Trigger Rate
+        if (nx_rate_timer < x"186a0") then
+          nx_rate_timer   <= nx_rate_timer + 1;
+        else
+          nx_rate_timer   <= (others => '0');
+          nx_trigger_rate <= nx_valid_ctr;
+          nx_valid_ctr    <= (others => '0');
+        end if;
+        
         -- Reset Counters
         if (clear_counters = '1') then
           invalid_frame_ctr   <= (others => '0');
@@ -301,10 +278,7 @@ begin
         slv_ack_o              <= '0';
         slv_unknown_addr_o     <= '0';
         slv_no_more_data_o     <= '0';
-        readout_mode           <= "00";
         clear_counters         <= '0';
-        trigger_window_width   <= (others => '0');
-        trigger_window_delay   <= (others => '0');
       else
         slv_data_out_o         <= (others => '0');
         slv_unknown_addr_o     <= '0';
@@ -313,46 +287,36 @@ begin
         
         if (SLV_READ_IN  = '1') then
           case SLV_ADDR_IN is
-            when x"0000" =>
-              slv_data_out_o(1 downto 0)   <= readout_mode;
-              slv_data_out_o(31 downto 2)  <= (others => '0');
-              slv_ack_o                    <= '1';
-
-            when x"0001" =>
-              slv_data_out_o(13 downto 0)            <=
-                std_logic_vector(trigger_window_width);
-              slv_data_out_o(31 downto 14) <= (others => '0');
-              slv_ack_o                    <= '1';
 
-            when x"0002" =>
-              slv_data_out_o(13 downto 0)            <=
-                std_logic_vector(trigger_window_delay);
-              slv_data_out_o(31 downto 14) <= (others => '0');
-              slv_ack_o                    <= '1'; 
-              
-            when x"000a" =>
+            when x"0000" =>
               slv_data_out_o(15 downto 0)  <=
                 std_logic_vector(invalid_frame_ctr);
               slv_data_out_o(31 downto 16) <= (others => '0');
               slv_ack_o                    <= '1';
 
-            when x"000b" =>
+            when x"0001" =>
               slv_data_out_o(15 downto 0)  <=
                 std_logic_vector(overflow_ctr);
               slv_data_out_o(31 downto 16) <= (others => '0');
               slv_ack_o                    <= '1';
 
-            when x"000c" =>
+            when x"0002" =>
               slv_data_out_o(15 downto 0)  <=
                 std_logic_vector(pileup_ctr);
               slv_data_out_o(31 downto 16) <= (others => '0');
               slv_ack_o                    <= '1';
 
-            when x"000d" =>
+            when x"0003" =>
               slv_data_out_o(15 downto 0)  <=
                 std_logic_vector(parity_error_ctr);
               slv_data_out_o(31 downto 16) <= (others => '0');
               slv_ack_o                    <= '1';
+
+            when x"0004" =>
+              slv_data_out_o(19 downto 0)  <=
+                std_logic_vector(nx_trigger_rate);
+              slv_data_out_o(31 downto 20) <= (others => '0');
+              slv_ack_o                    <= '1';
               
             when others  =>
               slv_unknown_addr_o           <= '1';
@@ -362,20 +326,6 @@ begin
         elsif (SLV_WRITE_IN  = '1') then
           case SLV_ADDR_IN is
             when x"0000" =>
-              readout_mode                 <= SLV_DATA_IN(1 downto 0);
-              slv_ack_o                    <= '1';
-
-            when x"0001" =>
-              trigger_window_width         <=
-                unsigned(SLV_DATA_IN(13 downto 0));
-              slv_ack_o                    <= '1';
-
-            when x"0002" =>
-              trigger_window_delay         <=
-                unsigned(SLV_DATA_IN(13 downto 0));
-              slv_ack_o                    <= '1'; 
-
-            when x"000f" =>
               clear_counters               <= '1';
               slv_ack_o                    <= '1';
               
@@ -394,10 +344,12 @@ begin
   -- Output Signals
   -----------------------------------------------------------------------------
 
-  TIMESTAMP_DATA_OUT    <= timestamp_data_o;
+  TIMESTAMP_OUT         <= timestamp_o;
+  CHANNEL_OUT           <= channel_o;
+  TIMESTAMP_STATUS_OUT  <= timestamp_status_o;
   TIMESTAMP_VALID_OUT   <= timestamp_valid_o;
-  NX_TOKEN_RETURN       <= nx_token_return_o;
-  NX_NOMORE_DATA        <= nx_nomore_data_o;
+  NX_TOKEN_RETURN_OUT   <= nx_token_return_o;
+  NX_NOMORE_DATA_OUT    <= nx_nomore_data_o;
   
   -- Slave 
   SLV_DATA_OUT          <= slv_data_out_o;    
diff --git a/nxyter/source/nx_trigger_handler.vhd b/nxyter/source/nx_trigger_handler.vhd
index 8f04494..281d8cf 100644
--- a/nxyter/source/nx_trigger_handler.vhd
+++ b/nxyter/source/nx_trigger_handler.vhd
@@ -37,8 +37,8 @@ end entity;
 architecture Behavioral of nx_trigger_handler is
 
   signal start_cycle         : std_logic;
-  signal wait_timer_init     : unsigned(9 downto 0);
-  signal wait_timer_init_x   : unsigned(9 downto 0);
+  signal wait_timer_init     : unsigned(7 downto 0);
+  signal wait_timer_init_x   : unsigned(7 downto 0);
   signal wait_timer_done     : std_logic;
   signal trigger_o           : std_logic;
   signal trigger_o_x         : std_logic;
@@ -48,7 +48,7 @@ architecture Behavioral of nx_trigger_handler is
   signal trigger_busy_o_x    : std_logic;
   
   type STATES is (S_IDLE,
-                  S_WAIT_HOLD,
+                  S_START,
                   S_WAIT_TRIGGER_RELEASE
                   );
   signal STATE, NEXT_STATE : STATES;
@@ -59,7 +59,7 @@ architecture Behavioral of nx_trigger_handler is
   signal slv_unknown_addr_o       : std_logic;
   signal slv_ack_o                : std_logic;
 
-  signal reg_timestamp_hold_delay : unsigned(9 downto 0);
+  signal reg_timestamp_hold_delay : unsigned(7 downto 0);
   
 begin
 
@@ -74,7 +74,7 @@ begin
   -- Timer
   nx_timer_1: nx_timer
     generic map (
-      CTR_WIDTH => 10
+      CTR_WIDTH => 8
       )
     port map (
       CLK_IN         => CLK_IN,
@@ -108,8 +108,7 @@ begin
 
   PROC_TRIGGER_HANDLER: process(STATE,
                                 TRIGGER_IN,
-                                TRIGGER_RELEASE_IN,
-                                wait_timer_done
+                                TRIGGER_RELEASE_IN
                                 )
   begin
     trigger_o_x         <= '0';
@@ -121,25 +120,16 @@ begin
       when  S_IDLE =>
         if (TRIGGER_IN = '1') then
           trigger_o_x         <= '1';
-          if (reg_timestamp_hold_delay > 0) then
-            wait_timer_init_x   <= reg_timestamp_hold_delay;
-            NEXT_STATE          <= S_WAIT_HOLD;
-          else
-            NEXT_STATE          <= S_WAIT_TRIGGER_RELEASE;
-          end if;
-        else
-           trigger_busy_o_x   <= '0';
-           NEXT_STATE         <= S_IDLE;
-        end if;
-
-      when S_WAIT_HOLD =>
-        if (wait_timer_done = '1') then
           timestamp_hold_o_x  <= '1';
-          NEXT_STATE          <= S_WAIT_TRIGGER_RELEASE;
+          NEXT_STATE          <= S_START;
         else
-          NEXT_STATE          <= S_WAIT_HOLD ;
+          trigger_busy_o_x    <= '0';
+          NEXT_STATE          <= S_IDLE;
         end if;
 
+      when S_START =>
+        NEXT_STATE            <= S_WAIT_TRIGGER_RELEASE;
+        
       when S_WAIT_TRIGGER_RELEASE =>
         if (TRIGGER_RELEASE_IN = '0') then
           NEXT_STATE          <= S_WAIT_TRIGGER_RELEASE;
@@ -163,7 +153,7 @@ begin
         slv_unknown_addr_o       <= '0';
         start_cycle              <= '0';
         slv_ack_o                <= '0';
-        reg_timestamp_hold_delay <= (others => '0');
+        reg_timestamp_hold_delay <= x"01";
       else
         slv_unknown_addr_o <= '0';
         slv_no_more_data_o <= '0';
@@ -174,7 +164,7 @@ begin
         if (SLV_WRITE_IN  = '1') then
           case SLV_ADDR_IN is
             when x"0000" =>
-              reg_timestamp_hold_delay <= SLV_DATA_IN(9 downto 0);
+              reg_timestamp_hold_delay <= SLV_DATA_IN(7 downto 0);
               slv_ack_o                <= '1';
               
             when others =>
@@ -186,9 +176,9 @@ begin
           case SLV_ADDR_IN is
 
             when x"0000" =>
-              slv_data_out_o(9 downto 0)   <=
+              slv_data_out_o(7 downto 0)   <=
                 std_logic_vector(reg_timestamp_hold_delay);
-              slv_data_out_o(31 downto 10) <= (others => '0');
+              slv_data_out_o(31 downto 8) <= (others => '0');
               slv_ack_o                    <= '1';
 
             when others =>
diff --git a/nxyter/source/nxyter.vhd b/nxyter/source/nxyter.vhd
index e101e6a..2af5df3 100644
--- a/nxyter/source/nxyter.vhd
+++ b/nxyter/source/nxyter.vhd
@@ -102,14 +102,26 @@ architecture Behavioral of nXyter_FEE_board is
        
   -- Timestamp Decode Handlers
   signal timestamp_data       : std_logic_vector(31 downto 0);
+  signal timestamp            : unsigned(13 downto 0);
+  signal timestamp_channel_id : unsigned(6 downto 0);
+  signal timestamp_status     : std_logic_vector(1 downto 0);
   signal timestamp_valid      : std_logic;
+
   signal nx_token_return      : std_logic;
   signal nx_nomore_data       : std_logic;
 
+  -- Timestamp Process
+  signal ts_data              : std_logic_vector(31 downto 0);
+  signal ts_data_clk          : std_logic;
+  signal data_fifo_reset      : std_logic;
+  
   -- FPGA Timestamp
   signal timestamp_trigger    : unsigned(11 downto 0);
   signal nx_timestamp_sync    : std_logic;
 
+  -- Data Buffer
+  signal data_buffer_reset    : std_logic;
+    
   -- Trigger Handler
   signal trigger_release      : std_logic;
   signal trigger_ack          : std_logic;
@@ -121,22 +133,38 @@ architecture Behavioral of nXyter_FEE_board is
   signal nx_testpulse_o       : std_logic;
   
 begin
-  trigger_release <= '1';
+
 -------------------------------------------------------------------------------
 -- DEBUG
 -------------------------------------------------------------------------------
+--   DEBUG_LINE_OUT(0)            <= CLK_IN;
+--   DEBUG_LINE_OUT(1)            <= trigger_ack;
+--   DEBUG_LINE_OUT(2)            <= nx_ts_reset_o;
+--   DEBUG_LINE_OUT(3)            <= nx_testpulse_o;
+--   DEBUG_LINE_OUT(4)            <= nx_new_timestamp;
+--   DEBUG_LINE_OUT(5)            <= timestamp_valid;
+--   DEBUG_LINE_OUT(6)            <= timestamp_hold;
+--   DEBUG_LINE_OUT(7)            <= nx_token_return;
+--   DEBUG_LINE_OUT(8)            <= nx_nomore_data;
+--   DEBUG_LINE_OUT(9)            <= trigger;
+--   DEBUG_LINE_OUT(10)           <= trigger_busy;
+--   DEBUG_LINE_OUT(11)           <= ts_data_clk;
+--   DEBUG_LINE_OUT(12)           <= data_fifo_reset;
+-- 
+--   DEBUG_LINE_OUT(14 downto 13) <= timestamp_status;
+--   DEBUG_LINE_OUT(15)           <= slv_ack(3);
+
   DEBUG_LINE_OUT(0)            <= CLK_IN;
-  DEBUG_LINE_OUT(1)            <= trigger_ack;
-  DEBUG_LINE_OUT(2)            <= nx_ts_reset_o;
-  DEBUG_LINE_OUT(3)            <= nx_testpulse_o;
+  DEBUG_LINE_OUT(1)            <= trigger;
+  DEBUG_LINE_OUT(2)            <= trigger_ack;
+  DEBUG_LINE_OUT(3)            <= trigger_busy;
   DEBUG_LINE_OUT(4)            <= nx_new_timestamp;
   DEBUG_LINE_OUT(5)            <= timestamp_valid;
-  DEBUG_LINE_OUT(6)            <= timestamp_hold;
-  DEBUG_LINE_OUT(7)            <= nx_token_return;
-  DEBUG_LINE_OUT(8)            <= nx_nomore_data;
-  DEBUG_LINE_OUT(9)            <= trigger;
-  DEBUG_LINE_OUT(10)           <= trigger_busy;
-  DEBUG_LINE_OUT(15 downto 11) <= (others => '0');
+  DEBUG_LINE_OUT(6)            <= nx_token_return;
+  DEBUG_LINE_OUT(7)            <= nx_nomore_data;
+  
+  --DEBUG_LINE_OUT(15 downto 8) <= (others => '0');
+  
 
 -------------------------------------------------------------------------------
 -- Port Maps
@@ -154,7 +182,7 @@ begin
 
   THE_BUS_HANDLER: trb_net16_regio_bus_handler
     generic map(
-      PORT_NUMBER         => 8,
+      PORT_NUMBER         => 9,
 
       PORT_ADDRESSES      => ( 0 => x"0100",    -- Control Register Handler
                                1 => x"0040",    -- I2C Master
@@ -164,16 +192,18 @@ begin
                                5 => x"0140",    -- Trigger Generator
                                6 => x"0120",    -- Timestamp Decode
                                7 => x"0160",    -- Trigger Handler
+                               8 => x"0180",    -- Timestamp Process
                                others => x"0000"),
 
       PORT_ADDR_MASK      => ( 0 => 3,          -- Control Register Handler
                                1 => 0,          -- I2C master
                                2 => 2,          -- Timestamp Fifo
-                               3 => 0,          -- Data Buffer
+                               3 => 1,          -- Data Buffer
                                4 => 0,          -- SPI Master
                                5 => 3,          -- Trigger Generator
                                6 => 4,          -- Timestamp Decode
                                7 => 1,          -- Trigger Handler
+                               8 => 4,          -- Timestamp Process
                                others => 0)
       )
     port map(
@@ -292,6 +322,19 @@ begin
       BUS_NO_MORE_DATA_IN(7)              => slv_no_more_data(7),
       BUS_UNKNOWN_ADDR_IN(7)              => slv_unknown_addr(7),
 
+      -- Timestamp Process
+      BUS_READ_ENABLE_OUT(8)              => slv_read(8),
+      BUS_WRITE_ENABLE_OUT(8)             => slv_write(8),
+      BUS_DATA_OUT(8*32+31 downto 8*32)   => slv_data_wr(8*32+31 downto 8*32),
+      BUS_DATA_IN(8*32+31 downto 8*32)    => slv_data_rd(8*32+31 downto 8*32),
+      BUS_ADDR_OUT(8*16+3 downto 8*16)    => slv_addr(8*16+3 downto 8*16),
+      BUS_ADDR_OUT(8*16+15 downto 8*16+4) => open,
+      BUS_TIMEOUT_OUT(8)                  => open,
+      BUS_DATAREADY_IN(8)                 => slv_ack(8),
+      BUS_WRITE_ACK_IN(8)                 => slv_ack(8),
+      BUS_NO_MORE_DATA_IN(8)              => slv_no_more_data(8),
+      BUS_UNKNOWN_ADDR_IN(8)              => slv_unknown_addr(8),
+
       ---- debug
       STAT_DEBUG          => open
       );
@@ -344,90 +387,6 @@ begin
       DEBUG_OUT             => open
       );
 
--------------------------------------------------------------------------------
--- nXyter TimeStamp Read
--------------------------------------------------------------------------------
-
-  nx_timestamp_fifo_read_1: nx_timestamp_fifo_read
-    port map (
-      CLK_IN               => CLK_IN,
-      RESET_IN             => RESET_IN,
-
-      NX_TIMESTAMP_CLK_IN  => NX_CLK128_IN,
-      NX_TIMESTAMP_IN      => NX_TIMESTAMP_IN,
-      NX_FRAME_CLOCK_OUT   => nx_frame_clock_o,
-      NX_TIMESTAMP_OUT     => nx_timestamp,
-      NX_NEW_TIMESTAMP_OUT => nx_new_timestamp,
-      SLV_READ_IN          => slv_read(2),
-      SLV_WRITE_IN         => slv_write(2),
-      SLV_DATA_OUT         => slv_data_rd(2*32+31 downto 2*32),
-      SLV_DATA_IN          => slv_data_wr(2*32+31 downto 2*32),
-      SLV_ADDR_IN          => slv_addr(2*16+15 downto 2*16),
-      SLV_ACK_OUT          => slv_ack(2),
-      SLV_NO_MORE_DATA_OUT => slv_no_more_data(2),
-      SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(2),
-
-      -- DEBUG_OUT            => DEBUG_LINE_OUT
-      DEBUG_OUT            => open
-      );
-
-
--------------------------------------------------------------------------------
--- Timestamp Decoder and Valid Data Filter
--------------------------------------------------------------------------------
-
-  nx_timestamp_decode_1: nx_timestamp_decode
-    port map (
-      CLK_IN               => CLK_IN,
-      RESET_IN             => RESET_IN,
-      NX_NEW_TIMESTAMP_IN  => nx_new_timestamp,
-      NX_TIMESTAMP_IN      => nx_timestamp,
-      TIMESTAMP_REF_IN     => timestamp_trigger,
-      TIMESTAMP_DATA_OUT   => timestamp_data,
-      TIMESTAMP_VALID_OUT  => timestamp_valid,
-      NX_TOKEN_RETURN      => nx_token_return,
-      NX_NOMORE_DATA       => nx_nomore_data,
-
-      SLV_READ_IN          => slv_read(6),
-      SLV_WRITE_IN         => slv_write(6),
-      SLV_DATA_OUT         => slv_data_rd(6*32+31 downto 6*32),
-      SLV_DATA_IN          => slv_data_wr(6*32+31 downto 6*32),
-      SLV_ADDR_IN          => slv_addr(6*16+15 downto 6*16),
-      SLV_ACK_OUT          => slv_ack(6),
-      SLV_NO_MORE_DATA_OUT => slv_no_more_data(6),
-      SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(6),
-      
-      -- DEBUG_OUT(14 downto 0) => DEBUG_LINE_OUT(14 downto 0)
-      DEBUG_OUT           => open
-      );
-
--------------------------------------------------------------------------------
--- Data Buffer FIFO
--------------------------------------------------------------------------------
-
-  nx_data_buffer_1: nx_data_buffer
-    port map (
-      CLK_IN                => CLK_IN,
-      RESET_IN              => RESET_IN,
-      DATA_IN               => timestamp_data,
-      NEW_DATA_IN           => timestamp_valid,
-      
-      FIFO_WRITE_ENABLE_IN  => '1',
-      FIFO_READ_ENABLE_IN   => '1',
-
-      SLV_READ_IN           => slv_read(3),
-      SLV_WRITE_IN          => slv_write(3),
-      SLV_DATA_OUT          => slv_data_rd(3*32+31 downto 3*32),
-      SLV_DATA_IN           => slv_data_wr(3*32+31 downto 3*32),
-      SLV_ADDR_IN           => slv_addr(3*16+15 downto 3*16),
-      SLV_ACK_OUT           => slv_ack(3),
-      SLV_NO_MORE_DATA_OUT  => slv_no_more_data(3),
-      SLV_UNKNOWN_ADDR_OUT  => slv_unknown_addr(3),
-
-      --DEBUG_OUT            => DEBUG_LINE_OUT
-      DEBUG_OUT            => open
-      );
-
 -------------------------------------------------------------------------------
 -- SPI master block to access the ADC
 -------------------------------------------------------------------------------
@@ -485,7 +444,7 @@ begin
       CLK_IN                => CLK_IN,
       RESET_IN              => RESET_IN,
       TRIGGER_IN            => trigger,
-      TRIGGER_RELEASE_IN    => trigger_release,
+      TRIGGER_RELEASE_IN    => not trigger_release,
       TRIGGER_OUT           => trigger_ack,
       TIMESTAMP_HOLD_OUT    => timestamp_hold,
       TRIGGER_BUSY_OUT      => trigger_busy,
@@ -525,6 +484,125 @@ begin
       );
 
 
+-------------------------------------------------------------------------------
+-- nXyter TimeStamp Read
+-------------------------------------------------------------------------------
+
+  nx_timestamp_fifo_read_1: nx_timestamp_fifo_read
+    port map (
+      CLK_IN               => CLK_IN,
+      RESET_IN             => RESET_IN,
+
+      NX_TIMESTAMP_CLK_IN  => NX_CLK128_IN,
+      NX_TIMESTAMP_IN      => NX_TIMESTAMP_IN,
+      NX_FRAME_CLOCK_OUT   => nx_frame_clock_o,
+      NX_TIMESTAMP_OUT     => nx_timestamp,
+      NX_NEW_TIMESTAMP_OUT => nx_new_timestamp,
+      SLV_READ_IN          => slv_read(2),
+      SLV_WRITE_IN         => slv_write(2),
+      SLV_DATA_OUT         => slv_data_rd(2*32+31 downto 2*32),
+      SLV_DATA_IN          => slv_data_wr(2*32+31 downto 2*32),
+      SLV_ADDR_IN          => slv_addr(2*16+15 downto 2*16),
+      SLV_ACK_OUT          => slv_ack(2),
+      SLV_NO_MORE_DATA_OUT => slv_no_more_data(2),
+      SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(2),
+
+      -- DEBUG_OUT            => DEBUG_LINE_OUT
+      DEBUG_OUT            => open
+      );
+
+
+-------------------------------------------------------------------------------
+-- Timestamp Decoder and Valid Data Filter
+-------------------------------------------------------------------------------
+
+  nx_timestamp_decode_1: nx_timestamp_decode
+    port map (
+      CLK_IN                => CLK_IN,
+      RESET_IN              => RESET_IN,
+      NX_NEW_TIMESTAMP_IN   => nx_new_timestamp,
+      NX_TIMESTAMP_IN       => nx_timestamp,
+
+      TIMESTAMP_OUT         => timestamp,
+      CHANNEL_OUT           => timestamp_channel_id,
+      TIMESTAMP_STATUS_OUT  => timestamp_status,
+      TIMESTAMP_VALID_OUT   => timestamp_valid,
+      NX_TOKEN_RETURN_OUT   => nx_token_return,
+      NX_NOMORE_DATA_OUT    => nx_nomore_data,
+      
+      SLV_READ_IN           => slv_read(6),
+      SLV_WRITE_IN          => slv_write(6),
+      SLV_DATA_OUT          => slv_data_rd(6*32+31 downto 6*32),
+      SLV_DATA_IN           => slv_data_wr(6*32+31 downto 6*32),
+      SLV_ADDR_IN           => slv_addr(6*16+15 downto 6*16),
+      SLV_ACK_OUT           => slv_ack(6),
+      SLV_NO_MORE_DATA_OUT  => slv_no_more_data(6),
+      SLV_UNKNOWN_ADDR_OUT  => slv_unknown_addr(6),
+      --DEBUG_OUT            => DEBUG_OUT
+      DEBUG_OUT           => open
+      );
+
+-------------------------------------------------------------------------------
+-- NX Timestamp Process
+-------------------------------------------------------------------------------
+
+  nx_timestamp_process_1: nx_timestamp_process
+    port map (
+      CLK_IN                 => CLK_IN,
+      RESET_IN               => RESET_IN,
+
+      TIMESTAMP_CLK_IN       => timestamp_valid,
+      NX_TOKEN_RETURN_IN     => nx_token_return,
+      NX_NOMORE_DATA_IN      => nx_nomore_data,
+      TIMESTAMP_IN           => timestamp,
+      CHANNEL_IN             => timestamp_channel_id,
+      TIMESTAMP_STATUS_IN    => timestamp_status,
+      TIMESTAMP_REF_IN       => timestamp_trigger,
+      TRIGGER_IN             => trigger_ack,
+
+      PROCESS_BUSY_OUT       => trigger_release,
+      DATA_OUT               => ts_data,
+      DATA_CLK_OUT           => ts_data_clk,
+      DATA_FIFO_RESET_OUT    => data_fifo_reset,
+
+      SLV_READ_IN            => slv_read(8),
+      SLV_WRITE_IN           => slv_write(8),
+      SLV_DATA_OUT           => slv_data_rd(8*32+31 downto 8*32),
+      SLV_DATA_IN            => slv_data_wr(8*32+31 downto 8*32),
+      SLV_ADDR_IN            => slv_addr(8*16+15 downto 8*16),
+      SLV_ACK_OUT            => slv_ack(8),
+      SLV_NO_MORE_DATA_OUT   => slv_no_more_data(8),
+      SLV_UNKNOWN_ADDR_OUT   => slv_unknown_addr(8),
+      DEBUG_OUT(7 downto 0)  => DEBUG_LINE_OUT(15 downto 8),
+      DEBUG_OUT(15 downto 8) => open
+      );
+
+-------------------------------------------------------------------------------
+-- Data Buffer FIFO
+-------------------------------------------------------------------------------
+
+  nx_data_buffer_1: nx_data_buffer
+    port map (
+      CLK_IN                => CLK_IN,
+      RESET_IN              => data_buffer_reset,
+      DATA_IN               => ts_data,
+      DATA_CLK_IN           => ts_data_clk,
+      
+      SLV_READ_IN           => slv_read(3),
+      SLV_WRITE_IN          => slv_write(3),
+      SLV_DATA_OUT          => slv_data_rd(3*32+31 downto 3*32),
+      SLV_DATA_IN           => slv_data_wr(3*32+31 downto 3*32),
+      SLV_ADDR_IN           => slv_addr(3*16+15 downto 3*16),
+      SLV_ACK_OUT           => slv_ack(3),
+      SLV_NO_MORE_DATA_OUT  => slv_no_more_data(3),
+      SLV_UNKNOWN_ADDR_OUT  => slv_unknown_addr(3),
+
+      --DEBUG_OUT            => DEBUG_LINE_OUT
+      DEBUG_OUT            => open
+      );
+
+  data_buffer_reset <= RESET_IN or data_fifo_reset;
+  
 -------------------------------------------------------------------------------
 -- nXyter Signals
 -------------------------------------------------------------------------------
diff --git a/nxyter/source/nxyter_components.vhd b/nxyter/source/nxyter_components.vhd
index e3e87a4..727f199 100644
--- a/nxyter/source/nxyter_components.vhd
+++ b/nxyter/source/nxyter_components.vhd
@@ -243,6 +243,33 @@ component nx_timestamp_fifo_read
     );
 end component;
 
+component nx_timestamp_process
+  port (
+    CLK_IN               : in  std_logic;
+    RESET_IN             : in  std_logic;
+    TIMESTAMP_CLK_IN     : in  std_logic;
+    NX_TOKEN_RETURN_IN   : in  std_logic;
+    NX_NOMORE_DATA_IN    : in  std_logic;
+    TIMESTAMP_IN         : in  unsigned(13 downto 0);
+    CHANNEL_IN           : in  unsigned(6 downto 0);
+    TIMESTAMP_STATUS_IN  : in  std_logic_vector(1 downto 0);
+    TIMESTAMP_REF_IN     : in  unsigned(11 downto 0);
+    TRIGGER_IN           : in  std_logic;
+    PROCESS_BUSY_OUT     : out std_logic;
+    DATA_OUT             : out std_logic_vector(31 downto 0);
+    DATA_CLK_OUT         : out std_logic;
+    DATA_FIFO_RESET_OUT  : out std_logic;
+    SLV_READ_IN          : in  std_logic;
+    SLV_WRITE_IN         : in  std_logic;
+    SLV_DATA_OUT         : out std_logic_vector(31 downto 0);
+    SLV_DATA_IN          : in  std_logic_vector(31 downto 0);
+    SLV_ADDR_IN          : in  std_logic_vector(15 downto 0);
+    SLV_ACK_OUT          : out std_logic;
+    SLV_NO_MORE_DATA_OUT : out std_logic;
+    SLV_UNKNOWN_ADDR_OUT : out std_logic;
+    DEBUG_OUT            : out std_logic_vector(15 downto 0));
+end component;
+
 component level_to_pulse
   port (
     CLK_IN         : in  std_logic;
@@ -295,9 +322,7 @@ component nx_data_buffer
     CLK_IN               : in  std_logic;
     RESET_IN             : in  std_logic;
     DATA_IN              : in  std_logic_vector(31 downto 0);
-    NEW_DATA_IN          : in  std_logic;
-    FIFO_WRITE_ENABLE_IN : in  std_logic;
-    FIFO_READ_ENABLE_IN  : in  std_logic;
+    DATA_CLK_IN          : in  std_logic;
     SLV_READ_IN          : in  std_logic;
     SLV_WRITE_IN         : in  std_logic;
     SLV_DATA_OUT         : out std_logic_vector(31 downto 0);
@@ -316,11 +341,12 @@ component nx_timestamp_decode
     RESET_IN             : in  std_logic;
     NX_NEW_TIMESTAMP_IN  : in  std_logic;
     NX_TIMESTAMP_IN      : in  std_logic_vector(31 downto 0);
-    TIMESTAMP_REF_IN     : in  unsigned(11 downto 0);
-    TIMESTAMP_DATA_OUT   : out std_logic_vector(31 downto 0);
+    TIMESTAMP_OUT        : out unsigned(13 downto 0);
+    CHANNEL_OUT          : out unsigned(6 downto 0);
+    TIMESTAMP_STATUS_OUT : out std_logic_vector(1 downto 0);
     TIMESTAMP_VALID_OUT  : out std_logic;
-    NX_TOKEN_RETURN      : out std_logic;
-    NX_NOMORE_DATA       : out std_logic;
+    NX_TOKEN_RETURN_OUT  : out std_logic;
+    NX_NOMORE_DATA_OUT   : out std_logic;
     SLV_READ_IN          : in  std_logic;
     SLV_WRITE_IN         : in  std_logic;
     SLV_DATA_OUT         : out std_logic_vector(31 downto 0);
@@ -329,11 +355,9 @@ component nx_timestamp_decode
     SLV_ACK_OUT          : out std_logic;
     SLV_NO_MORE_DATA_OUT : out std_logic;
     SLV_UNKNOWN_ADDR_OUT : out std_logic;
-    DEBUG_OUT            : out std_logic_vector(15 downto 0)
-    );
+    DEBUG_OUT            : out std_logic_vector(15 downto 0));
 end component;
 
-
 component pll_nx_clk256
   port (
     CLK   : in  std_logic;
diff --git a/nxyter/source/registers.txt b/nxyter/source/registers.txt
new file mode 100644
index 0000000..6142ff3
--- /dev/null
+++ b/nxyter/source/registers.txt
@@ -0,0 +1,55 @@
+-- Control Register
+0x8100 :  r/w  w: reset I2C State Machine r: reset ctr
+0x8101 :  r/w  w: reset I2C all Register r: reset ctr
+0x8102 :  r/w  w: Reset and Sync Timestamps (nXyter and FPGA) r: reset ctr
+
+-- Timestamp Decode
+0x8120 :  rw   Invalid Frame Counter (16 bit) / w: clear all counters
+0x8121 :  r    Overflow Counter (16 bit)
+0x8122 :  r    Pileup Counter (16 bit)
+0x8123 :  r    Parity Error Counter (16 bit)
+0x8124 :  r    Trigger Rate (in kHz)
+
+-- Timestamp Process
+0x8180 :  r/w  Readout Mode (0:Ref + valid + window, 1: Ref + Valid 
+                             3: Raw and TimeStamp + valid,
+                             4: Raw,  5: Raw + Valid )
+0x8181 :  r/w  Trigger Window Delay (12 bit, in 3.9ns) 
+0x8182 :  r/w  Trigger Window Width (12 bit, in 3.9ns)
+0x8183 :  r/w  Readout Time Max (12 bit, in 10ns)
+0x8184 :  r    Busy Time Counter (12 bit, in 10ns)
+
+0x8185 :  r    done counter
+0x8186 :  r    done counter
+0x8187 :  r    done counter
+0x8188 :  r    done counter
+
+-- Trigger Generator
+0x8140 :  w    If writing just start trigger cycle, keep current setting
+0x8141 :  r/w  Bit 15-0 : periodic time (in 10ns) 
+0x8142 :  r/w  Bit0 7-0 : number of triggers to be sent consecutive
+0x8143 :  r/w  Bit 15-0 : Length of trigger pulse (in 10ns), if 0: skip it
+0x8144 :  r/w  Bit0     : 1: send timestamp-reset before trigger 
+
+-- Trigger Handler
+0x8160 :  r/w  Bit 15-0 : Delay Trigger in Timestamp Hold 
+
+-- Timestamp Fifo
+0x8500 :  r    current FIFO value
+0x8501 :  r/w  r: FIFO Status ......
+               w: trigger resync
+0x8502 :  r/w  r: get resync counter(8bit)
+               w: clear resync counter    
+
+-- Data Buffer
+0x8600 :  r    read FIFO buffer
+0x8601 :  r/w  r: read FIFO status
+               w: enable/disable FIFO write
+
+-- I2C Master
+0x8040 :     Access to I2C Interface
+
+-- SPI Master
+0x8060 :    Access to SPI Interface
+
+