From: Jan Michel Date: Fri, 9 Feb 2018 17:08:45 +0000 (+0100) Subject: Remove PLL from calibration clock source X-Git-Tag: v2.3~19 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=94c1527ba201dfb80c1fc05aac7c36511d78d339;p=tdc.git Remove PLL from calibration clock source --- diff --git a/releases/tdc_v2.3/trb3_periph_32PinAddOn.vhd b/releases/tdc_v2.3/trb3_periph_32PinAddOn.vhd index e9d68ed..3a9ca8d 100644 --- a/releases/tdc_v2.3/trb3_periph_32PinAddOn.vhd +++ b/releases/tdc_v2.3/trb3_periph_32PinAddOn.vhd @@ -93,7 +93,6 @@ architecture trb3_periph_32PinAddOn_arch of trb3_periph_32PinAddOn is --Clock / Reset signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL - signal osc_int : std_logic; -- clock for calibrating the tdc, 2.5 MHz, via internal osscilator signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. signal clear_i : std_logic; signal reset_i : std_logic; @@ -166,11 +165,6 @@ begin LOCK => pll_lock ); - pll_calibration : entity work.pll_in125_out33 - port map ( - CLK => CLK_GPLL_LEFT, - CLKOP => osc_int, - LOCK => open); --------------------------------------------------------------------------- -- The TrbNet media interface (to other FPGA) @@ -408,7 +402,7 @@ begin CLK_READOUT => clk_100_i, -- Clock for the readout REFERENCE_TIME => timing_trg_received_i, -- Reference time input HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals - HIT_CAL_IN => osc_int, -- Hits for calibrating the TDC + HIT_CAL_IN => CLK_GPLL_LEFT, -- Hits for calibrating the TDC -- Trigger signals from handler BUSRDO_RX => readout_rx, BUSRDO_TX => readout_tx(0), diff --git a/releases/tdc_v2.3/trb3_periph_ADA.vhd b/releases/tdc_v2.3/trb3_periph_ADA.vhd index 6d03c53..84074a4 100644 --- a/releases/tdc_v2.3/trb3_periph_ADA.vhd +++ b/releases/tdc_v2.3/trb3_periph_ADA.vhd @@ -104,7 +104,6 @@ architecture trb3_periph_ADA_arch of trb3_periph_ADA is signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL signal clk_20 : std_logic; --clock for calibration at 20 MHz, via PLL - signal osc_int : std_logic; --clock for calibration at 20 MHz, via internal osscilator signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. signal clear_i : std_logic; signal reset_i : std_logic; @@ -185,17 +184,6 @@ begin LOCK => pll_lock); - --pll_calibration: entity work.pll_in125_out100 - -- port map ( - -- CLK => CLK_GPLL_LEFT, - -- CLKOP => osc_int, - -- LOCK => open); - - pll_calibration: entity work.pll_in125_out33 - port map ( - CLK => CLK_GPLL_LEFT, - CLKOP => osc_int, - LOCK => open); --------------------------------------------------------------------------- -- The TrbNet media interface (to other FPGA) @@ -425,7 +413,7 @@ begin CLK_READOUT => clk_100_i, -- Clock for the readout REFERENCE_TIME => timing_trg_received_i, -- Reference time input HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals - HIT_CAL_IN => osc_int, -- Hits for calibrating the TDC + HIT_CAL_IN => CLK_GPLL_LEFT, -- Hits for calibrating the TDC -- Trigger signals from handler BUSRDO_RX => readout_rx, BUSRDO_TX => readout_tx(0), diff --git a/releases/tdc_v2.3/trb3_periph_gpin.vhd b/releases/tdc_v2.3/trb3_periph_gpin.vhd index a18d554..d6c13b2 100644 --- a/releases/tdc_v2.3/trb3_periph_gpin.vhd +++ b/releases/tdc_v2.3/trb3_periph_gpin.vhd @@ -95,7 +95,6 @@ architecture trb3_periph_gpin_arch of trb3_periph_gpin is --Clock / Reset signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL - signal clk_cal : std_logic; -- clock for calibrating the tdc, 2.5 MHz, via internal osscilator signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. signal clear_i : std_logic; signal reset_i : std_logic; @@ -243,11 +242,6 @@ begin LOCK => pll_lock ); - pll_calibration : entity work.pll_in125_out33 - port map ( - CLK => CLK_GPLL_LEFT, - CLKOP => clk_cal, - LOCK => open); --------------------------------------------------------------------------- -- The TrbNet media interface (to other FPGA) @@ -662,7 +656,7 @@ begin CLK_READOUT => clk_100_i, -- Clock for the readout REFERENCE_TIME => timing_trg_received_i, -- Reference time input HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals - HIT_CAL_IN => clk_cal, -- Hits for calibrating the TDC + HIT_CAL_IN => CLK_GPLL_LEFT, -- Hits for calibrating the TDC -- Trigger signals from handler BUSRDO_RX => readout_rx, BUSRDO_TX => readout_tx(0), diff --git a/releases/tdc_v2.3/trb3_periph_padiwa.vhd b/releases/tdc_v2.3/trb3_periph_padiwa.vhd index d02e501..569c98e 100644 --- a/releases/tdc_v2.3/trb3_periph_padiwa.vhd +++ b/releases/tdc_v2.3/trb3_periph_padiwa.vhd @@ -104,7 +104,6 @@ architecture trb3_periph_padiwa_arch of trb3_periph_padiwa is --Clock / Reset signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL - signal osc_int : std_logic; -- clock for calibrating the tdc, 2.5 MHz, via internal osscilator signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. signal clear_i : std_logic; signal reset_i : std_logic; @@ -268,11 +267,6 @@ begin LOCK => pll_lock ); - pll_calibration: entity work.pll_in125_out33 - port map ( - CLK => CLK_GPLL_LEFT, - CLKOP => osc_int, - LOCK => open); gen_sync_clocks : if SYNC_MODE = c_YES generate clk_100_i <= rx_clock_100; @@ -726,7 +720,7 @@ begin CLK_READOUT => clk_100_i, -- Clock for the readout REFERENCE_TIME => timing_trg_received_i, -- Reference time input HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals - HIT_CAL_IN => osc_int, -- Hits for calibrating the TDC + HIT_CAL_IN => CLK_GPLL_LEFT, -- Hits for calibrating the TDC -- Trigger signals from handler BUSRDO_RX => readout_rx, BUSRDO_TX => readout_tx(0),