From: Jan Michel <j.michel@gsi.de>
Date: Tue, 25 Jul 2017 14:01:49 +0000 (+0200)
Subject: Update ECP3 full quad to AC coupling
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=95167c5dfbc6d5b149e721c64e4b82d7147b3546;p=trbnet.git

Update ECP3 full quad to AC coupling
---

diff --git a/media_interfaces/ecp3_sfp/serdes_sync_4.ipx b/media_interfaces/ecp3_sfp/serdes_sync_4.ipx
index cb4776d..c1a8d57 100644
--- a/media_interfaces/ecp3_sfp/serdes_sync_4.ipx
+++ b/media_interfaces/ecp3_sfp/serdes_sync_4.ipx
@@ -1,11 +1,11 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_sync_4" module="PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 10 15 14:55:32.927" version="8.2" type="Module" synthesis="synplify" source_format="VHDL">
+<DiamondModule name="serdes_sync_4" module="PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2017 06 06 16:20:58.301" version="8.2" type="Module" synthesis="synplify" source_format="VHDL">
   <Package>
-		<File name="serdes_sync_4.lpc" type="lpc" modified="2015 10 15 14:55:29.000"/>
-		<File name="serdes_sync_4.pp" type="pp" modified="2015 10 15 14:55:29.000"/>
-		<File name="serdes_sync_4.sym" type="sym" modified="2015 10 15 14:55:30.000"/>
+		<File name="serdes_sync_4.lpc" type="lpc" modified="2017 06 06 16:20:56.000"/>
+		<File name="serdes_sync_4.pp" type="pp" modified="2017 06 06 16:20:56.000"/>
+		<File name="serdes_sync_4.sym" type="sym" modified="2017 06 06 16:20:57.000"/>
 		<File name="serdes_sync_4.tft" type="tft" modified="2015 10 15 14:55:29.000"/>
-		<File name="serdes_sync_4.txt" type="pcs_module" modified="2015 10 15 14:55:29.000"/>
-		<File name="serdes_sync_4.vhd" type="top_level_vhdl" modified="2015 10 15 14:55:29.000"/>
+		<File name="serdes_sync_4.txt" type="pcs_module" modified="2017 06 06 16:20:56.000"/>
+		<File name="serdes_sync_4.vhd" type="top_level_vhdl" modified="2015 10 15 15:54:51.000"/>
   </Package>
 </DiamondModule>
diff --git a/media_interfaces/ecp3_sfp/serdes_sync_4.lpc b/media_interfaces/ecp3_sfp/serdes_sync_4.lpc
index 5285ee6..1523bcc 100644
--- a/media_interfaces/ecp3_sfp/serdes_sync_4.lpc
+++ b/media_interfaces/ecp3_sfp/serdes_sync_4.lpc
@@ -16,8 +16,8 @@ CoreRevision=8.2
 ModuleName=serdes_sync_4
 SourceFormat=VHDL
 ParameterFileVersion=1.0
-Date=10/15/2015
-Time=14:55:29
+Date=06/06/2017
+Time=16:20:56
 
 [Parameters]
 Verilog=0
@@ -119,10 +119,10 @@ _rterm_rx0=50
 _rterm_rx1=50
 _rterm_rx2=50
 _rterm_rx3=50
-_rx_dcc0=DC
-_rx_dcc1=DC
-_rx_dcc2=DC
-_rx_dcc3=DC
+_rx_dcc0=AC
+_rx_dcc1=AC
+_rx_dcc2=AC
+_rx_dcc3=AC
 _los_threshold_mode0=LOS_E
 _los_threshold_mode1=LOS_E
 _los_threshold_mode2=LOS_E
diff --git a/media_interfaces/ecp3_sfp/serdes_sync_4.txt b/media_interfaces/ecp3_sfp/serdes_sync_4.txt
index f52e775..af64a86 100644
--- a/media_interfaces/ecp3_sfp/serdes_sync_4.txt
+++ b/media_interfaces/ecp3_sfp/serdes_sync_4.txt
@@ -80,10 +80,10 @@ CH0_RTERM_RX            "50"
 CH1_RTERM_RX            "50"
 CH2_RTERM_RX            "50"
 CH3_RTERM_RX            "50"
-CH0_RX_DCC              "DC"
-CH1_RX_DCC              "DC"
-CH2_RX_DCC              "DC"
-CH3_RX_DCC              "DC"
+CH0_RX_DCC              "AC"
+CH1_RX_DCC              "AC"
+CH2_RX_DCC              "AC"
+CH3_RX_DCC              "AC"
 CH0_LOS_THRESHOLD_LO       "2"
 CH1_LOS_THRESHOLD_LO       "2"
 CH2_LOS_THRESHOLD_LO       "2"
diff --git a/special/sram_is61.vhd b/oldfiles/sram_is61.vhd
similarity index 100%
rename from special/sram_is61.vhd
rename to oldfiles/sram_is61.vhd