From: Cahit Date: Thu, 24 Apr 2014 07:07:16 +0000 (+0200) Subject: corrected clock names in the constraints X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=9526a4ed19474529a5e6601d5bc48649371ff391;p=trb3.git corrected clock names in the constraints --- diff --git a/base/cbmtof.lpf b/base/cbmtof.lpf index 106afc9..9434a91 100644 --- a/base/cbmtof.lpf +++ b/base/cbmtof.lpf @@ -16,8 +16,8 @@ FREQUENCY PORT CLK_EXT 200 MHz; #MULTICYCLE FROM CLKNET "clk_100_i_c" TO CLKNET "CLK_OSC_c" 2 X ; ##MULTICYCLE FROM CLKNET "CLK_OSC_c" TO CLKNET "clk_100_i_c" 1 X ; -MULTICYCLE FROM CLKNET "clk_100_i_c" TO CLKNET "CLK_EXT" 2 X ; -#MULTICYCLE FROM CLKNET "CLK_EXT" TO CLKNET "clk_100_i_c" 1 X ; +MULTICYCLE FROM CLKNET "clk_100_i_c" TO CLKNET "CLK_EXT_c" 1 X ; +MULTICYCLE FROM CLKNET "CLK_EXT_c" TO CLKNET "clk_100_i_c" 2 X ; LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_0_200_ctc.THE_SERDES/PCSD_INST" SITE "PCSA" ; diff --git a/cbmtof/unimportant_lines_constraints.lpf b/cbmtof/unimportant_lines_constraints.lpf index c6b7e10..30e7c73 100644 --- a/cbmtof/unimportant_lines_constraints.lpf +++ b/cbmtof/unimportant_lines_constraints.lpf @@ -8,8 +8,8 @@ MULTICYCLE FROM CELL "PROC_TDC_CTRL_REG*tdc_ctrl_reg*" 4x; MULTICYCLE TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/SimAdderNo*FC/FF*" 4x; MULTICYCLE TO CELL "THE_TDC/ReferenceChannel/Channel200/SimAdderNo*FC/FF*" 4x; -MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x; -MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x; +MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET CLK_EXT_c TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x; +MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET CLK_EXT_c TO CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x; MULTICYCLE TO CELL "THE_TDC/GEN_Channels*Channels/sync_q*" 4 x; MULTICYCLE TO CELL "THE_TDC/ReferenceChannel/sync_q*" 4 x;