From: hadeshyp Date: Tue, 2 Jun 2009 09:46:54 +0000 (+0000) Subject: added time registers to regio X-Git-Tag: oldGBE~444 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=95317bd4956f61af5a94621ecf0df85e7a187815;p=trbnet.git added time registers to regio --- diff --git a/trb_net16_endpoint_hades_full.vhd b/trb_net16_endpoint_hades_full.vhd index ddeab50..dba9ab8 100644 --- a/trb_net16_endpoint_hades_full.vhd +++ b/trb_net16_endpoint_hades_full.vhd @@ -41,7 +41,8 @@ entity trb_net16_endpoint_hades_full is REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; - REGIO_USE_1WIRE_INTERFACE: integer := c_YES --c_YES,c_NO,c_MONITOR + REGIO_USE_1WIRE_INTERFACE: integer := c_YES; --c_YES,c_NO,c_MONITOR + CLOCK_FREQUENCY : integer range 1 to 200 := 100 ); port( @@ -114,6 +115,13 @@ entity trb_net16_endpoint_hades_full is REGIO_ONEWIRE_INOUT : inout std_logic; REGIO_ONEWIRE_MONITOR_IN : in std_logic; REGIO_ONEWIRE_MONITOR_OUT : out std_logic; + + TRIGGER_MONITOR_IN : in std_logic; --strobe when timing trigger received + GLOBAL_TIME_OUT : out std_logic_vector(31 downto 0); --global time, microseconds + LOCAL_TIME_OUT : out std_logic_vector(7 downto 0); --local time running with chip frequency + TIME_SINCE_LAST_TRG_OUT : out std_logic_vector(31 downto 0); --local time, resetted with each trigger + TIMER_US_TICK_OUT : out std_logic; --1 tick every microsecond + --Debugging & Status information STAT_DEBUG_IPU : out std_logic_vector (31 downto 0); STAT_DEBUG_1 : out std_logic_vector (31 downto 0); @@ -185,7 +193,8 @@ architecture trb_net16_endpoint_hades_full_arch of trb_net16_endpoint_hades_full INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; - HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678" + HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; + CLOCK_FREQ : integer range 1 to 200 := 100 --MHz ); port( -- Misc @@ -217,6 +226,11 @@ architecture trb_net16_endpoint_hades_full_arch of trb_net16_endpoint_hades_full IDRAM_ADDR_IN : in std_logic_vector(2 downto 0); IDRAM_WR_IN : in std_logic; MY_ADDRESS_OUT : out std_logic_vector(15 downto 0); + TRIGGER_MONITOR : in std_logic; --strobe when timing trigger received + GLOBAL_TIME : out std_logic_vector(31 downto 0); --global time, microseconds + LOCAL_TIME : out std_logic_vector(7 downto 0); --local time running with chip frequency + TIME_SINCE_LAST_TRG : out std_logic_vector(31 downto 0); --local time, resetted with each trigger + TIMER_US_TICK : out std_logic; --1 tick every microsecond --Common Register in / out COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REG_WIDTH-1 downto 0); @@ -850,7 +864,8 @@ begin INIT_UNIQUE_ID => REGIO_INIT_UNIQUE_ID, COMPILE_TIME => REGIO_COMPILE_TIME, COMPILE_VERSION => REGIO_COMPILE_VERSION, - HARDWARE_VERSION => REGIO_HARDWARE_VERSION + HARDWARE_VERSION => REGIO_HARDWARE_VERSION, + CLOCK_FREQ => CLOCK_FREQUENCY ) port map( -- Misc @@ -879,6 +894,11 @@ begin IDRAM_ADDR_IN => buf_IDRAM_ADDR_IN, IDRAM_WR_IN => buf_IDRAM_WR_IN, MY_ADDRESS_OUT => MY_ADDRESS, + TRIGGER_MONITOR => TRIGGER_MONITOR_IN, + GLOBAL_TIME => GLOBAL_TIME_OUT, + LOCAL_TIME => LOCAL_TIME_OUT, + TIME_SINCE_LAST_TRG => TIME_SINCE_LAST_TRG_OUT, + TIMER_US_TICK => TIMER_US_TICK_OUT, --Common Register in / out COMMON_STAT_REG_IN => buf_COMMON_STAT_REG_IN, COMMON_CTRL_REG_OUT => REGIO_COMMON_CTRL_REG_OUT, diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd index c18c0a2..451534e 100644 --- a/trb_net16_hub_base.vhd +++ b/trb_net16_hub_base.vhd @@ -20,6 +20,7 @@ entity trb_net16_hub_base is COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; + CLOCK_FREQUENCY : integer range 1 to 200 := 100; USE_ONEWIRE : integer range 0 to 2 := c_YES; --media interfaces MII_NUMBER : integer range 2 to c_MAX_MII_PER_HUB := 12; @@ -192,6 +193,10 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is signal IDRAM_ADDR_IN : std_logic_vector(2 downto 0); signal TEMP_OUT : std_logic_vector(11 downto 0); + signal global_time : std_logic_vector(31 downto 0); + signal local_time : std_logic_vector(7 downto 0); + signal timer_us_tick : std_logic; + begin @@ -667,7 +672,8 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1'); INIT_UNIQUE_ID => INIT_UNIQUE_ID, COMPILE_TIME => COMPILE_TIME, COMPILE_VERSION => COMPILE_VERSION, - HARDWARE_VERSION => HARDWARE_VERSION + HARDWARE_VERSION => HARDWARE_VERSION, + CLOCK_FREQ => CLOCK_FREQUENCY ) port map( CLK => CLK, @@ -692,6 +698,11 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1'); API_RUN_IN => HC_RUN_OUT, API_SEQNR_IN => HC_SEQNR_OUT, MY_ADDRESS_OUT => HUB_ADDRESS, + TRIGGER_MONITOR => '0', + GLOBAL_TIME => global_time, + LOCAL_TIME => local_time, + TIME_SINCE_LAST_TRG => open, + TIMER_US_TICK => timer_us_tick, REGISTERS_IN => HC_STAT_REGS, REGISTERS_OUT => HC_CTRL_REGS, COMMON_STAT_REG_IN => HC_COMMON_STAT_REGS, diff --git a/trb_net16_hub_func.vhd b/trb_net16_hub_func.vhd index e17c147..f831c8f 100644 --- a/trb_net16_hub_func.vhd +++ b/trb_net16_hub_func.vhd @@ -338,16 +338,14 @@ package trb_net16_hub_func is component trb_net16_regIO is generic ( - NUM_STAT_REGS : integer range 0 to 6 := 1; --log2 of number of status registers - NUM_CTRL_REGS : integer range 0 to 6 := 2; --log2 of number of ctrl registers + NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers + NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers --standard values for output registers - INIT_CTRL_REGS : std_logic_vector(2**(3)*32-1 downto 0) := - (others => '0'); + INIT_CTRL_REGS : std_logic_vector(2**(3)*32-1 downto 0) := (others => '0'); --set to 0 for unused ctrl registers to save resources USED_CTRL_REGS : std_logic_vector(2**(3)-1 downto 0) := "00000001"; --set to 0 for each unused bit in a register - USED_CTRL_BITMASK : std_logic_vector(2**(3)*32-1 downto 0) := - (others => '1'); + USED_CTRL_BITMASK : std_logic_vector(2**(3)*32-1 downto 0) := (others => '1'); USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF"; INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876"; @@ -355,7 +353,8 @@ package trb_net16_hub_func is INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; - HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678" + HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; + CLOCK_FREQ : integer range 1 to 200 := 100 --MHz ); port( -- Misc @@ -381,19 +380,26 @@ package trb_net16_hub_func is API_RUN_IN : in std_logic; API_SEQNR_IN : in std_logic_vector (7 downto 0); - --Port to write Unique ID + --Port to write Unique ID (-> 1-wire) IDRAM_DATA_IN : in std_logic_vector(15 downto 0); IDRAM_DATA_OUT : out std_logic_vector(15 downto 0); IDRAM_ADDR_IN : in std_logic_vector(2 downto 0); IDRAM_WR_IN : in std_logic; + + --Informations MY_ADDRESS_OUT : out std_logic_vector(15 downto 0); + TRIGGER_MONITOR : in std_logic; + GLOBAL_TIME : out std_logic_vector(31 downto 0); --global time, microseconds + LOCAL_TIME : out std_logic_vector(7 downto 0); --local time running with chip frequency + TIME_SINCE_LAST_TRG : out std_logic_vector(31 downto 0); --local time, resetted with each trigger + TIMER_US_TICK : out std_logic; --1 tick every microsecond --Common Register in / out - COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REGISTER_WIDTH-1 downto 0); - COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*c_REGIO_REGISTER_WIDTH-1 downto 0); + COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REG_WIDTH-1 downto 0); + COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*c_REGIO_REG_WIDTH-1 downto 0); --Custom Register in / out - REGISTERS_IN : in std_logic_vector(c_REGIO_REGISTER_WIDTH*2**(NUM_STAT_REGS)-1 downto 0); - REGISTERS_OUT : out std_logic_vector(c_REGIO_REGISTER_WIDTH*2**(NUM_CTRL_REGS)-1 downto 0); + REGISTERS_IN : in std_logic_vector(c_REGIO_REG_WIDTH*2**(NUM_STAT_REGS)-1 downto 0); + REGISTERS_OUT : out std_logic_vector(c_REGIO_REG_WIDTH*2**(NUM_CTRL_REGS)-1 downto 0); --Internal Data Port DAT_ADDR_OUT : out std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0); DAT_READ_ENABLE_OUT : out std_logic; @@ -405,7 +411,10 @@ package trb_net16_hub_func is DAT_WRITE_ACK_IN : in std_logic; DAT_UNKNOWN_ADDR_IN : in std_logic; DAT_TIMEOUT_OUT : out std_logic; - STAT : out std_logic_vector(31 downto 0) + + --Additional write access to ctrl registers + STAT : out std_logic_vector(31 downto 0); + STAT_ADDR_DEBUG : out std_logic_vector(15 downto 0) ); end component; diff --git a/trb_net16_regIO.vhd b/trb_net16_regIO.vhd index 235e546..1369061 100644 --- a/trb_net16_regIO.vhd +++ b/trb_net16_regIO.vhd @@ -26,7 +26,8 @@ entity trb_net16_regIO is INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; - HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678" + HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; + CLOCK_FREQ : integer range 1 to 200 := 100 --MHz ); port( -- Misc @@ -60,8 +61,10 @@ entity trb_net16_regIO is --Informations MY_ADDRESS_OUT : out std_logic_vector(15 downto 0); - GLOBAL_TIME : out std_logic_vector(31 downto 0);--global time, microseconds - LOCAL_TIME : out std_logic_vector(7 downto 0); --local time running with chip frequency + TRIGGER_MONITOR : in std_logic; --strobe when timing trigger received + GLOBAL_TIME : out std_logic_vector(31 downto 0); --global time, microseconds + LOCAL_TIME : out std_logic_vector(7 downto 0); --local time running with chip frequency + TIME_SINCE_LAST_TRG : out std_logic_vector(31 downto 0); --local time, resetted with each trigger TIMER_US_TICK : out std_logic; --1 tick every microsecond --Common Register in / out @@ -221,8 +224,17 @@ architecture trb_net16_regIO_arch of trb_net16_regIO is signal buf_STAT_ADDR_DEBUG : std_logic_vector(15 downto 0); + signal global_time_i : std_logic_vector(31 downto 0) := (others => '0'); + signal time_since_last_trg_i : std_logic_vector(31 downto 0) := (others => '0'); + signal local_time_i : std_logic_vector(7 downto 0) := (others => '0'); + signal us_tick_i : std_logic := '0'; + + begin +--------------------------------------------------------------------- +--5bit address decoder for registers +--------------------------------------------------------------------- pattern_gen_inst : trb_net_pattern_gen generic map( WIDTH => 5 @@ -233,7 +245,11 @@ begin ); reg_enable_pattern(63 downto 32) <= (others => '0'); - addresses : trb_net16_addresses +--------------------------------------------------------------------- +-- trbnet addresses +--------------------------------------------------------------------- + + the_addresses : trb_net16_addresses generic map( INIT_ADDRESS => INIT_ADDRESS, INIT_UNIQUE_ID => INIT_UNIQUE_ID, @@ -263,19 +279,10 @@ begin STAT_DEBUG => buf_STAT_ADDR_DEBUG ); - STAT_ADDR_DEBUG(2 downto 0) <= state_bits(2 downto 0); - STAT_ADDR_DEBUG(3) <= ADR_DONT_UNDERSTAND; - STAT_ADDR_DEBUG(4) <= API_DATAREADY_IN; - STAT_ADDR_DEBUG(5) <= buf_API_SHORT_TRANSFER_OUT; - STAT_ADDR_DEBUG(6) <= combined_API_SEND_OUT; - STAT_ADDR_DEBUG(11 downto 7) <= buf_STAT_ADDR_DEBUG(11 downto 7); - STAT_ADDR_DEBUG(12) <= combined_API_DATAREADY_OUT; - STAT_ADDR_DEBUG(13) <= ADR_REJECTED; - STAT_ADDR_DEBUG(14) <= ADR_SEND_OUT; - STAT_ADDR_DEBUG(15) <= ADR_DATAREADY_OUT; - buf_DAT_ADDR_OUT <= address; - buf_DAT_DATA_OUT <= saved_Reg_high & saved_Reg_low; +--------------------------------------------------------------------- +-- Main State Machine +--------------------------------------------------------------------- fsm : process(API_DATA_IN, API_PACKET_NUM_IN, API_TYP_IN, API_DATAREADY_IN, API_READ_IN, address, saved_Reg_high, saved_Reg_low, saved_operation, current_state, @@ -335,7 +342,7 @@ begin next_nomoredata <= '0'; end if; - when HEADER_RECV => --read and save HDR + when HEADER_RECV => --read HDR if API_DATAREADY_IN = '1' then case API_PACKET_NUM_IN is when c_F3 => @@ -405,6 +412,7 @@ begin next_state <= REG_WRITE; --ctrl register else next_state <= SEND_REPLY_SHORT_TRANSFER; + next_dont_understand <= '1'; end if; end if; @@ -431,7 +439,7 @@ begin else next_COMMON_REGISTERS_OUT_write_enable <= reg_enable_pattern(std_COMCTRLREG-1 downto 0); end if; - next_state <= REG_READ; + next_state <= SEND_REPLY_SHORT_TRANSFER; --REG_READ; else next_DAT_WRITE_ENABLE_OUT <= '1'; next_state <= WAIT_AFTER_REG_WRITE; @@ -458,17 +466,19 @@ begin when c_F0 => next_API_DATA_OUT <= address; when c_F1 => - if address(7 downto 6) = "01" then + if address(7 downto 6) = "01" then --0x40 next_API_DATA_OUT <= rom_read_dout; rom_read_addr <= address(1 downto 0) & '0'; - elsif address(7 downto 6) = "10" then + elsif address(7 downto 6) = "10" then --0x80 next_API_DATA_OUT <= REGISTERS_IN(regnum_STAT*c_REGIO_REG_WIDTH+31 downto regnum_STAT*c_REGIO_REG_WIDTH+16); - elsif address(7 downto 6) = "11" then + elsif address(7 downto 6) = "11" then --0xC0 next_API_DATA_OUT <= buf_REGISTERS_OUT(regnum_CTRL*c_REGIO_REG_WIDTH+31 downto regnum_CTRL*c_REGIO_REG_WIDTH+16); - elsif address(5) = '0' then + elsif address(5) = '0' then --0x00 next_API_DATA_OUT <= COMMON_STAT_REG_IN(regnum_cSTAT*c_REGIO_REG_WIDTH+31 downto regnum_cSTAT*c_REGIO_REG_WIDTH+16); - else --if address(5) = '1' then + elsif address(5) = '1' then --0x20 next_API_DATA_OUT <= buf_COMMON_CTRL_REG_OUT(regnum_cCTRL*c_REGIO_REG_WIDTH+31 downto regnum_cCTRL*c_REGIO_REG_WIDTH+16); + else + next_API_DATA_OUT <= (others => '0'); end if; when c_F2 => if address(7 downto 6) = "01" then @@ -479,8 +489,10 @@ begin next_API_DATA_OUT <= buf_REGISTERS_OUT(regnum_CTRL*c_REGIO_REG_WIDTH+15 downto regnum_CTRL*c_REGIO_REG_WIDTH); elsif address(5) = '0' then next_API_DATA_OUT <= COMMON_STAT_REG_IN(regnum_cSTAT*c_REGIO_REG_WIDTH+15 downto regnum_cSTAT*c_REGIO_REG_WIDTH); - else --if address(5) = '1' then + elsif address(5) = '1' then next_API_DATA_OUT <= buf_COMMON_CTRL_REG_OUT(regnum_cCTRL*c_REGIO_REG_WIDTH+15 downto regnum_cCTRL*c_REGIO_REG_WIDTH); + else + next_API_DATA_OUT <= (others => '0'); end if; when c_F3 => next_API_DATA_OUT <= (others => '0'); @@ -698,7 +710,9 @@ begin end process; ---generate packet numbers +--------------------------------------------------------------------- +-- Packet Numbers +--------------------------------------------------------------------- reg_packet_counter : process(CLK) begin if rising_edge(CLK) then @@ -723,6 +737,9 @@ begin end if; end process; +--------------------------------------------------------------------- +-- Generate output to API +--------------------------------------------------------------------- process(CLK) begin if rising_edge(CLK) then @@ -741,6 +758,36 @@ begin end if; end process; + --combine signals from regio and addresses + process(current_state, ADR_READ_OUT, buf_API_READ_OUT, ADR_SEND_OUT, ADR_DATA_OUT, ADR_DATAREADY_OUT, + ADR_PACKET_NUM_OUT, buf_API_SEND_OUT, buf_API_DATA_OUT, buf_API_DATAREADY_OUT, buf_API_PACKET_NUM_OUT) + begin + if current_state = ADDRESS_RECV or current_state = ADDRESS_ACK then + combined_API_READ_OUT <= ADR_READ_OUT; + combined_API_SEND_OUT <= ADR_SEND_OUT; + combined_API_DATA_OUT <= ADR_DATA_OUT; + combined_API_DATAREADY_OUT <= ADR_DATAREADY_OUT; + combined_API_PACKET_NUM_OUT <= ADR_PACKET_NUM_OUT; + else + combined_API_READ_OUT <= buf_API_READ_OUT; + combined_API_SEND_OUT <= buf_API_SEND_OUT; + combined_API_DATA_OUT <= buf_API_DATA_OUT; + combined_API_DATAREADY_OUT <= buf_API_DATAREADY_OUT; + combined_API_PACKET_NUM_OUT <= buf_API_PACKET_NUM_OUT; + end if; + end process; + + buf_API_ERROR_PATTERN_OUT(31 downto 19) <= (others => '0'); + buf_API_ERROR_PATTERN_OUT(18) <= nomoredata; + buf_API_ERROR_PATTERN_OUT(17) <= timeout; + buf_API_ERROR_PATTERN_OUT(16) <= unknown; + buf_API_ERROR_PATTERN_OUT(15 downto 5) <= (others => '0'); + buf_API_ERROR_PATTERN_OUT(4) <= dont_understand; + buf_API_ERROR_PATTERN_OUT(3 downto 0) <= (others => '0'); + +--------------------------------------------------------------------- +-- Read from DAT port +--------------------------------------------------------------------- --save Dataready_in in case API can not read immediately process(CLK) begin @@ -755,7 +802,20 @@ begin end if; end process; + process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + buf_DAT_DATA_IN <= (others => '0'); + elsif DAT_DATAREADY_IN = '1' then + buf_DAT_DATA_IN <= DAT_DATA_IN; + end if; + end if; + end process; +--------------------------------------------------------------------- +-- User defined CTRL registers +--------------------------------------------------------------------- gen_regout : for i in 0 to 2**(NUM_CTRL_REGS)-1 generate gen_regoutff1 : for j in i*c_REGIO_REG_WIDTH to (i+1)*c_REGIO_REG_WIDTH-1 generate gen_regoutff : if USED_CTRL_REGS(i) = '1' and USED_CTRL_BITMASK(j) = '1' generate @@ -778,7 +838,9 @@ begin end generate; end generate; - +--------------------------------------------------------------------- +-- Common CTRL registers +--------------------------------------------------------------------- gen_strobe_ctrl_regs : if std_COMCTRLREG >= 1 generate process(CLK) begin @@ -811,38 +873,62 @@ begin end generate; end generate; - process(CLK) +--------------------------------------------------------------------- +-- Global Time Register +--------------------------------------------------------------------- + + proc_global_time : process(CLK) begin if rising_edge(CLK) then - if RESET = '1' then - buf_DAT_DATA_IN <= (others => '0'); - elsif DAT_DATAREADY_IN = '1' then - buf_DAT_DATA_IN <= DAT_DATA_IN; +-- global_time(15 downto 0) <= next_global_time(15 downto 0); +-- global_time_overflow <= '0'; + if COMMON_REGISTERS_OUT_write_enable(2) = '1' then + global_time_i <= saved_Reg_high & saved_Reg_low; + elsif us_tick_i = '1' then + global_time_i <= global_time_i + 1; +-- next_global_time(15 downto 0) <= global_time(15 downto 0) + 1; +-- if or_all(global_time(15 downto 0)) = '1' then +-- global_time_overflow <= '1'; +-- end if; +-- elsif global_time_overflow = '1' then +-- global_time_buf <= '0'; +-- global_time(31 downto 16) <= global_time(31 downto 16) + 1; end if; end if; end process; + proc_us_tick : process(CLK) + begin + if rising_edge(CLK) then + if local_time_i = conv_std_logic_vector(CLOCK_FREQ - 1,8) then + local_time_i <= (others => '0'); + us_tick_i <= '1'; + else + local_time_i <= local_time_i + 1; + us_tick_i <= '0'; + end if; + end if; + end process; - --combine signals from regio and addresses - process(current_state, ADR_READ_OUT, buf_API_READ_OUT, ADR_SEND_OUT, ADR_DATA_OUT, ADR_DATAREADY_OUT, - ADR_PACKET_NUM_OUT, buf_API_SEND_OUT, buf_API_DATA_OUT, buf_API_DATAREADY_OUT, buf_API_PACKET_NUM_OUT) + proc_time_since_trg : process(CLK) begin - if current_state = ADDRESS_RECV or current_state = ADDRESS_ACK then - combined_API_READ_OUT <= ADR_READ_OUT; - combined_API_SEND_OUT <= ADR_SEND_OUT; - combined_API_DATA_OUT <= ADR_DATA_OUT; - combined_API_DATAREADY_OUT <= ADR_DATAREADY_OUT; - combined_API_PACKET_NUM_OUT <= ADR_PACKET_NUM_OUT; - else - combined_API_READ_OUT <= buf_API_READ_OUT; - combined_API_SEND_OUT <= buf_API_SEND_OUT; - combined_API_DATA_OUT <= buf_API_DATA_OUT; - combined_API_DATAREADY_OUT <= buf_API_DATAREADY_OUT; - combined_API_PACKET_NUM_OUT <= buf_API_PACKET_NUM_OUT; + if rising_edge(CLK) then + if TRIGGER_MONITOR = '1' then + time_since_last_trg_i <= (others => '0'); + else + time_since_last_trg_i <= time_since_last_trg_i + 1; + end if; end if; end process; + GLOBAL_TIME <= global_time_i; + LOCAL_TIME <= local_time_i; + TIMER_US_TICK <= us_tick_i; + TIME_SINCE_LAST_TRG <= time_since_last_trg_i; +--------------------------------------------------------------------- +-- ROM with board information +--------------------------------------------------------------------- board_rom : rom_16x8 generic map( INIT0 => COMPILE_TIME(15 downto 0), @@ -860,14 +946,10 @@ begin dout => rom_read_dout ); - buf_API_ERROR_PATTERN_OUT(31 downto 19) <= (others => '0'); - buf_API_ERROR_PATTERN_OUT(18) <= nomoredata; - buf_API_ERROR_PATTERN_OUT(17) <= timeout; - buf_API_ERROR_PATTERN_OUT(16) <= unknown; - buf_API_ERROR_PATTERN_OUT(15 downto 5) <= (others => '0'); - buf_API_ERROR_PATTERN_OUT(4) <= dont_understand; - buf_API_ERROR_PATTERN_OUT(3 downto 0) <= (others => '0'); +--------------------------------------------------------------------- +-- Assign signals to outputs +--------------------------------------------------------------------- API_READ_OUT <= combined_API_READ_OUT; API_SEND_OUT <= combined_API_SEND_OUT; API_DATAREADY_OUT <= combined_API_DATAREADY_OUT; @@ -884,6 +966,13 @@ begin REGISTERS_OUT <= buf_REGISTERS_OUT; COMMON_CTRL_REG_OUT <= buf_COMMON_CTRL_REG_OUT; + buf_DAT_ADDR_OUT <= address; + buf_DAT_DATA_OUT <= saved_Reg_high & saved_Reg_low; + +--------------------------------------------------------------------- +-- Debugging Signals +--------------------------------------------------------------------- + STAT(3 downto 0) <= state_bits; STAT(6 downto 4) <= buf_API_PACKET_NUM_OUT; STAT(7) <= next_API_DATAREADY_OUT; @@ -913,6 +1002,18 @@ begin end process; + STAT_ADDR_DEBUG(2 downto 0) <= state_bits(2 downto 0); + STAT_ADDR_DEBUG(3) <= ADR_DONT_UNDERSTAND; + STAT_ADDR_DEBUG(4) <= API_DATAREADY_IN; + STAT_ADDR_DEBUG(5) <= buf_API_SHORT_TRANSFER_OUT; + STAT_ADDR_DEBUG(6) <= combined_API_SEND_OUT; + STAT_ADDR_DEBUG(11 downto 7) <= buf_STAT_ADDR_DEBUG(11 downto 7); + STAT_ADDR_DEBUG(12) <= combined_API_DATAREADY_OUT; + STAT_ADDR_DEBUG(13) <= ADR_REJECTED; + STAT_ADDR_DEBUG(14) <= ADR_SEND_OUT; + STAT_ADDR_DEBUG(15) <= ADR_DATAREADY_OUT; + + end architecture; diff --git a/trb_net_std.vhd b/trb_net_std.vhd index 7db88b3..ed03630 100644 --- a/trb_net_std.vhd +++ b/trb_net_std.vhd @@ -101,9 +101,9 @@ package trb_net_std is --common registers --maximum: 4, because of regio implementation constant std_COMSTATREG : integer := 2; - constant std_COMCTRLREG : integer := 2; + constant std_COMCTRLREG : integer := 3; --needed address width for common registers - constant std_COMneededwidth : integer := 1; + constant std_COMneededwidth : integer := 2; constant c_REGIO_ADDRESS_WIDTH : integer := 16; constant c_REGIO_REGISTER_WIDTH : integer := 32; constant c_REGIO_REG_WIDTH : integer := 32;