From: Jan Michel Date: Fri, 10 May 2013 13:13:18 +0000 (+0200) Subject: Added pinout and I/O for CTS AddOn X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=95451edcbf0e86fe52d2ee19328c378910e913d2;p=trb3.git Added pinout and I/O for CTS AddOn --- diff --git a/base/trb3_central_cts.lpf b/base/trb3_central_cts.lpf index 65fa975..38a0d45 100644 --- a/base/trb3_central_cts.lpf +++ b/base/trb3_central_cts.lpf @@ -300,7 +300,7 @@ LOCATE COMP "ECL_IN_1" SITE "M26"; LOCATE COMP "ECL_IN_2" SITE "L26"; LOCATE COMP "ECL_IN_3" SITE "N28"; DEFINE PORT GROUP "ECL_IN_group" "ECL_IN*" ; -IOBUF GROUP "ECL_IN_group" IO_TYPE=LVTTL33 PULLMODE=NONE; +IOBUF GROUP "ECL_IN_group" IO_TYPE=LVTTL33 PULLMODE=DOWN; LOCATE COMP "JIN1_0" SITE "R26"; LOCATE COMP "JIN1_1" SITE "P26"; @@ -333,12 +333,12 @@ LOCATE COMP "JINLVDS_13" SITE "K32"; LOCATE COMP "JINLVDS_14" SITE "N30"; LOCATE COMP "JINLVDS_15" SITE "N29"; DEFINE PORT GROUP "JINLVDS_group" "JINLVDS*" ; -IOBUF GROUP "JINLVDS_group" IO_TYPE=LVTTL33 PULLMODE=NONE; +IOBUF GROUP "JINLVDS_group" IO_TYPE=LVTTL33 PULLMODE=DOWN; -LOCATE COMP "COMPARATOR_IN_0" SITE "T32"; -LOCATE COMP "COMPARATOR_IN_1" SITE "T30"; -DEFINE PORT GROUP "COMPARATOR_group" "COMPARATOR*" ; -IOBUF GROUP "COMPARATOR_group" IO_TYPE=LVDS25 DIFFRESISTOR=NONE; +LOCATE COMP "DISCRIMINATOR_IN_0" SITE "T32"; +LOCATE COMP "DISCRIMINATOR_IN_1" SITE "T30"; +DEFINE PORT GROUP "DISCRIMINATOR_group" "DISCRIMINATOR*" ; +IOBUF GROUP "DISCRIMINATOR_group" IO_TYPE=LVDS25 DIFFRESISTOR=NONE; LOCATE COMP "JOUT1_0" SITE "B4"; LOCATE COMP "JOUT1_1" SITE "B3"; @@ -428,10 +428,10 @@ IOBUF PORT "LED_RJ_RED_3" IO_TYPE=LVTTL33 DRIVE=8 ; IOBUF PORT "LED_RJ_RED_4" IO_TYPE=LVCMOS25 DRIVE=8 ; IOBUF PORT "LED_RJ_RED_5" IO_TYPE=LVTTL33 DRIVE=8 ; -LOCATE COMP "NIM_IN_1" SITE "T26"; -LOCATE COMP "NIM_IN_2" SITE "U26"; +LOCATE COMP "NIM_IN_0" SITE "T26"; +LOCATE COMP "NIM_IN_1" SITE "U26"; DEFINE PORT GROUP "NIM_group" "NIM*" ; -IOBUF GROUP "NIM_group" IO_TYPE=LVTTL33 PULLMODE=NONE; +IOBUF GROUP "NIM_group" IO_TYPE=LVTTL33 PULLMODE=DOWN; LOCATE COMP "PWM_OUT_0" SITE "U27"; LOCATE COMP "PWM_OUT_1" SITE "U31"; diff --git a/cts/compile_central_frankfurt.pl b/cts/compile_central_frankfurt.pl index d7c8571..0a46f69 100755 --- a/cts/compile_central_frankfurt.pl +++ b/cts/compile_central_frankfurt.pl @@ -41,7 +41,7 @@ my $SPEEDGRADE="8"; #create full lpf file -system("cp ../base/$TOPNAME.lpf workdir/$TOPNAME.lpf"); +system("cp ../base/trb3_central_cts.lpf workdir/$TOPNAME.lpf"); system("cat tdc_release/tdc_constraints.lpf >> workdir/$TOPNAME.lpf"); system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf"); system("sed -i 's#THE_TDC/#gen_TDC_THE_TDC/#g' workdir/$TOPNAME.lpf"); diff --git a/cts/config_default.vhd b/cts/config_default.vhd index c6bb52f..da2bf42 100644 --- a/cts/config_default.vhd +++ b/cts/config_default.vhd @@ -18,7 +18,7 @@ package config is --Run wih 125 MHz instead of 100 MHz - constant USE_125_MHZ : integer range c_NO to c_YES := c_YES; + constant USE_125_MHZ : integer range c_NO to c_YES := c_NO; --Which external trigger module (ETM) to use? type ETM_CHOICE_type is (ETM_CHOICE_MBS_VULOM, ETM_CHOICE_MAINZ_A2); diff --git a/cts/config_mainz_a2.vhd b/cts/config_mainz_a2.vhd index 6ff60ff..12b5bdf 100644 --- a/cts/config_mainz_a2.vhd +++ b/cts/config_mainz_a2.vhd @@ -18,7 +18,7 @@ package config is --Run wih 125 MHz instead of 100 MHz - constant USE_125_MHZ : integer range c_NO to c_YES := c_YES; + constant USE_125_MHZ : integer range c_NO to c_YES := c_NO; --Which external trigger module (ETM) to use? type ETM_CHOICE_type is (ETM_CHOICE_MBS_VULOM, ETM_CHOICE_MAINZ_A2); diff --git a/cts/trb3_central.vhd b/cts/trb3_central.vhd index 58918d8..2a80928 100644 --- a/cts/trb3_central.vhd +++ b/cts/trb3_central.vhd @@ -38,6 +38,7 @@ library work; -- 7000 - 72FF Readout endpoint registers -- 8100 - 83FF GbE configuration & status -- A000 - A1FF CTS configuration & status +-- C000 - CFFF TDC configuration & status -- D000 - D13F Flash Programming @@ -103,13 +104,29 @@ entity trb3_central is FPGA4_CONNECTOR : inout std_logic_vector(7 downto 0); --Bit 0-1: LED for SFP1/2 --Bit 0-3 connected to LED by default, two on each side - --Big AddOn connector - ADDON_RESET : out std_logic; --reset signal to AddOn - ADDON_TO_TRB_CLK : in std_logic; --Clock from AddOn, connected to PCLK input - TRB_TO_ADDON_CLK : out std_logic; --Clock sent to AddOn - ADO_LV : inout std_logic_vector(61 downto 0); - ADO_TTL : inout std_logic_vector(46 downto 0); - FS_PE : inout std_logic_vector(17 downto 0); + --AddOn connector + ECL_IN : in std_logic_vector(3 downto 0); + NIM_IN : in std_logic_vector(1 downto 0); + JIN1 : in std_logic_vector(3 downto 0); + JIN2 : in std_logic_vector(3 downto 0); + JINLVDS : in std_logic_vector(15 downto 0); --No LVDS, just TTL! + + DISCRIMINATOR_IN : in std_logic_vector(1 downto 0); + PWM_OUT : out std_logic_vector(1 downto 0); + + JOUT1 : out std_logic_vector(3 downto 0); + JOUT2 : out std_logic_vector(3 downto 0); + JOUTLVDS : out std_logic_vector(7 downto 0); + JTTL : inout std_logic_vector(15 downto 0); + TRG_FANOUT_ADDON : out std_logic; + + LED_BANK : out std_logic_vector(7 downto 0); + LED_RJ_GREEN : out std_logic_vector(5 downto 0); + LED_RJ_RED : out std_logic_vector(5 downto 0); + LED_FAN_GREEN : out std_logic; + LED_FAN_ORANGE : out std_logic; + LED_FAN_RED : out std_logic; + LED_FAN_YELLOW : out std_logic; --Flash ROM & Reboot FLASH_CLK : out std_logic; @@ -133,17 +150,25 @@ entity trb3_central is --Test Connectors TEST_LINE : out std_logic_vector(31 downto 0) ); - + + attribute syn_useioff : boolean; --no IO-FF for LEDs relaxes timing constraints attribute syn_useioff of LED_CLOCK_GREEN : signal is false; attribute syn_useioff of LED_CLOCK_RED : signal is false; + attribute syn_useioff of LED_TRIGGER_GREEN : signal is false; + attribute syn_useioff of LED_TRIGGER_RED : signal is false; attribute syn_useioff of LED_GREEN : signal is false; attribute syn_useioff of LED_ORANGE : signal is false; attribute syn_useioff of LED_RED : signal is false; - attribute syn_useioff of LED_TRIGGER_GREEN : signal is false; - attribute syn_useioff of LED_TRIGGER_RED : signal is false; attribute syn_useioff of LED_YELLOW : signal is false; + attribute syn_useioff of LED_FAN_GREEN : signal is false; + attribute syn_useioff of LED_FAN_ORANGE : signal is false; + attribute syn_useioff of LED_FAN_RED : signal is false; + attribute syn_useioff of LED_FAN_YELLOW : signal is false; + attribute syn_useioff of LED_BANK : signal is false; + attribute syn_useioff of LED_RJ_GREEN : signal is false; + attribute syn_useioff of LED_RJ_RED : signal is false; attribute syn_useioff of FPGA1_TTL : signal is false; attribute syn_useioff of FPGA2_TTL : signal is false; attribute syn_useioff of FPGA3_TTL : signal is false; @@ -1378,13 +1403,9 @@ end process; --------------------------------------------------------------------------- --- Big AddOn Connector +-- AddOn Connector --------------------------------------------------------------------------- - ADDON_RESET <= '1'; - TRB_TO_ADDON_CLK <= '0'; - ADO_LV <= (others => 'Z'); - ADO_TTL <= (others => 'Z'); - FS_PE <= (others => 'Z'); + ---------------------------------------------------------------------------