From: Jan Michel Date: Sun, 4 Aug 2024 13:13:56 +0000 (+0200) Subject: code changes towards Trb5sc based CTS X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=9545c34b2fe6eef0e98e1b11fa050f0a70227589;p=trb5sc.git code changes towards Trb5sc based CTS --- diff --git a/cts/config.vhd b/cts/config.vhd index 9df133e..66fde17 100644 --- a/cts/config.vhd +++ b/cts/config.vhd @@ -37,7 +37,7 @@ package config is constant EVENT_BUFFER_SIZE : integer range 9 to 15 := 10; -- size of the event buffer, 2**N constant EVENT_MAX_SIZE : integer := 500; --maximum event size. Must not exceed EVENT_BUFFER_SIZE/2 - constant USE_GBE : integer := c_NO; + constant USE_GBE : integer := c_YES; --Runs with 120 MHz instead of 100 MHz constant USE_120_MHZ : integer := c_NO; @@ -62,15 +62,44 @@ package config is constant TRIG_GEN_OUTPUT_NUM : integer := 4; constant MONITOR_INPUT_NUM : integer := 16; + + + constant GEN_BUSY_OUTPUT : integer := c_NO; + + constant TRIGGER_COIN_COUNT : integer := 1; + constant TRIGGER_PULSER_COUNT : integer := 2; + constant TRIGGER_RAND_PULSER : integer := 0; + constant TRIGGER_ADDON_COUNT : integer := 2; + constant PERIPH_TRIGGER_COUNT : integer := 0; + constant ADDON_LINE_COUNT : integer := 12; --36 with Padiwa, 22 with RJ-adapter + constant CTS_OUTPUT_MULTIPLEXERS : integer := 0; +--TODO: +-- constant INCLUDE_MBS_MASTER : integer range c_NO to c_YES := c_NO; +--Which external trigger module (ETM) to use? + constant INCLUDE_ETM : integer range c_NO to c_YES := c_NO; + type ETM_CHOICE_type is (ETM_CHOICE_MBS_VULOM, ETM_CHOICE_MAINZ_A2, ETM_CHOICE_CBMNET, ETM_CHOICE_M26, ETM_CHOICE_R3B); + constant ETM_CHOICE : ETM_CHOICE_type := ETM_CHOICE_MBS_VULOM; + constant ETM_ID : std_logic_vector(7 downto 0); + + constant INCLUDE_TIMESTAMP_GENERATOR : integer := c_NO; + ------------------------------------------------------------------------------ --End of design configuration ------------------------------------------------------------------------------ + constant INTERFACE_NUM : integer; + constant IS_UPLINK : hub_ct := (0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0); + constant IS_DOWNLINK : hub_ct := (1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0); + constant IS_UPLINK_ONLY : hub_ct := (0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0); + + ------------------------------------------------------------------------------ --Select settings by configuration ------------------------------------------------------------------------------ - type intlist_t is array(0 to 7) of integer; - type hw_info_t is array(0 to 7) of unsigned(31 downto 0); + constant cts_rdo_additional_ports : integer := '1'; --for internal endpoint + + + constant HW_INFO_BASE : unsigned(31 downto 0) := x"A5000200"; constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0); @@ -92,6 +121,23 @@ package body config is constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ); constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ); + + + function etm_id_func return std_logic_vector is + variable res : unsigned(7 downto 0); + begin + res := x"00"; + if INCLUDE_ETM=c_YES then + res := x"60"; + res := res + TO_UNSIGNED(ETM_CHOICE_type'pos(ETM_CHOICE), 4); + end if; + return std_logic_vector(res); + end function; + + constant ETM_ID : std_logic_vector(7 downto 0) := etm_id_func; + + + function generateIncludedFeatures return std_logic_vector is variable t : std_logic_vector(63 downto 0); begin @@ -104,7 +150,7 @@ function generateIncludedFeatures return std_logic_vector is -- t(15) := '1'; --TDC -- t(17 downto 16) := std_logic_vector(to_unsigned(NUM_TDC_MODULES-1,2)); t(16 downto 16) := std_logic_vector(to_unsigned(USE_GBE,1)); - t(28 downto 28) := std_logic_vector(to_unsigned(1-SERDES_NUM,1)); + t(28 downto 28) := std_logic_vector(to_unsigned(0,1)); t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1)); t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1)); diff --git a/cts/trb5sc_cts.vhd b/cts/trb5sc_cts.vhd index 03fc609..c7e1b96 100644 --- a/cts/trb5sc_cts.vhd +++ b/cts/trb5sc_cts.vhd @@ -23,7 +23,32 @@ entity trb5sc_cts is SFP_LOS : in std_logic; SFP_MOD_0 : in std_logic; - + --ADC AddOn + GPIO : inout std_logic_vector(5 downto 0); + + ADDON_LED : out std_logic_vector(7 downto 1); + ADDON_LED_RJ : out std_logic_vector(1 downto 0); + + SCLK_A : out std_logic; + CSB_A : out std_logic; + SDIO_A : inout std_logic; + FCO_A : in std_logic; + DATA_A : in std_logic_vector(3 downto 0); + DCO_A : in std_logic; + CLK_A : out std_logic; + + CLK_B : out std_logic; + TESTPAT_B : out std_logic; + DCO_B : in std_logic; + DATA_B : in std_logic; + CNV_B : out std_logic; + + LEMO_OUT : out std_logic_vector(1 downto 0); + LEMO_OE : out std_logic_vector(1 downto 0); + LEMO_TTL : in std_logic_vector(1 downto 0); + LEMO_NIM : in std_logic_vector(1 downto 0); + ADDON_RJ : in std_logic_vector(3 downto 0); + --ADC ADC_SCLK : out std_logic; ADC_NCS : out std_logic; @@ -65,7 +90,7 @@ entity trb5sc_cts is end entity; -architecture arch of trb5sc_adc is +architecture arch of trb5sc_cts is constant ACTIVE_CHANNELS : integer := 5; @@ -95,8 +120,8 @@ architecture arch of trb5sc_adc is signal readout_rx : READOUT_RX; signal readout_tx : readout_tx_array_t(0 to ACTIVE_CHANNELS-1); - signal ctrlbus_tx, bussci_tx, bustools_tx, bustc_tx, bus_master_in, busadc_tx, busi2c_tx : CTRLBUS_TX; - signal ctrlbus_rx, bussci_rx, bustools_rx, bustc_rx, bus_master_out, busadc_rx, busi2c_rx : CTRLBUS_RX; + signal ctrlbus_tx, bustools_tx, buscts_rx, bustc_tx, busgbeip_rx, busgbereg_rx, bus_master_in, busadc_tx : CTRLBUS_TX; + signal ctrlbus_rx, bustools_rx, buscts_tx, bustc_rx, busgbeip_tx, busgbereg_tx, bus_master_out, busadc_rx : CTRLBUS_RX; signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); @@ -105,6 +130,8 @@ architecture arch of trb5sc_adc is signal clock_select : std_logic; signal bus_master_active : std_logic; signal flash_ncs_i : std_logic; + signal rdack, wrack : std_logic; + signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0); signal header_io_i : std_logic_vector(10 downto 1); @@ -117,10 +144,75 @@ architecture arch of trb5sc_adc is signal clk_350, clk_50, clk_200bypass : std_logic; - + signal monitor_inputs_i : std_logic_vector(MONITOR_INPUT_NUM-1 downto 0); + signal trigger_gen_outputs_i: std_logic_vector(TRIG_GEN_OUTPUT_NUM-1 downto 0); + signal trigger_busy_i : std_logic; + signal cts_trigger_out : std_logic; + signal cts_monitor_out : std_logic_vector(1 downto 0); + + signal gbe_cts_number : std_logic_vector(15 downto 0); + signal gbe_cts_code : std_logic_vector(7 downto 0); + signal gbe_cts_information : std_logic_vector(7 downto 0); + signal gbe_cts_start_readout : std_logic; + signal gbe_cts_readout_type : std_logic_vector(3 downto 0); + signal gbe_cts_readout_finished : std_logic; + signal gbe_cts_status_bits : std_logic_vector(31 downto 0); + signal gbe_fee_data : std_logic_vector(15 downto 0); + signal gbe_fee_dataready : std_logic; + signal gbe_fee_read : std_logic; + signal gbe_fee_status_bits : std_logic_vector(31 downto 0); + signal gbe_fee_busy : std_logic; + + signal gsc_init_data, gsc_reply_data : std_logic_vector(15 downto 0); + signal gsc_init_read, gsc_reply_read : std_logic; + signal gsc_init_dataready, gsc_reply_dataready : std_logic; + signal gsc_init_packet_num, gsc_reply_packet_num : std_logic_vector(2 downto 0); + signal gsc_busy : std_logic; + + signal cts_rdo_trg_status_bits_cts : std_logic_vector(31 downto 0) := (others => '0'); + signal cts_rdo_data : std_logic_vector(31 downto 0); + signal cts_rdo_write : std_logic; + signal cts_rdo_finished : std_logic; + + -- signal cts_ext_trigger : std_logic; + -- signal cts_ext_status : std_logic_vector(31 downto 0) := (others => '0'); + -- signal cts_ext_control : std_logic_vector(31 downto 0); + -- signal cts_ext_debug : std_logic_vector(31 downto 0); + -- signal cts_ext_header : std_logic_vector(1 downto 0) := "00"; + + signal cts_rdo_additional_data : std_logic_vector(32*cts_rdo_additional_ports-1 downto 0); + signal cts_rdo_additional_write : std_logic_vector(cts_rdo_additional_ports-1 downto 0) := (others => '0'); + signal cts_rdo_additional_finished : std_logic_vector(cts_rdo_additional_ports-1 downto 0) := (others => '1'); + signal cts_rdo_trg_status_bits_additional : std_logic_vector(32*cts_rdo_additional_ports-1 downto 0) := (others => '0'); + + signal cts_rdo_additional : readout_tx_array_t(0 to cts_rdo_additional_ports-1); + signal cts_rdo_rx : READOUT_RX; + + + signal cts_addon_triggers_in : std_logic_vector(ADDON_LINE_COUNT-1 downto 0); + signal cts_monitor_out : std_logic_vector(CTS_OUTPUT_MULTIPLEXERS-1 downto 0); + + + signal cts_trg_send : std_logic; + signal cts_trg_type : std_logic_vector(3 downto 0); + signal cts_trg_number : std_logic_vector(15 downto 0); + signal cts_trg_information : std_logic_vector(23 downto 0); + signal cts_trg_code : std_logic_vector(7 downto 0); + signal cts_trg_status_bits : std_logic_vector(31 downto 0); + signal cts_trg_busy : std_logic; + + signal cts_ipu_send : std_logic; + signal cts_ipu_type : std_logic_vector(3 downto 0); + signal cts_ipu_number : std_logic_vector(15 downto 0); + signal cts_ipu_information : std_logic_vector(7 downto 0); + signal cts_ipu_code : std_logic_vector(7 downto 0); + signal cts_ipu_status_bits : std_logic_vector(31 downto 0); + signal cts_ipu_busy : std_logic; + + begin - trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and not IN_SELECT_EXT_CLOCK); + -- trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and not IN_SELECT_EXT_CLOCK); --------------------------------------------------------------------------- -- Clock & Reset Handling @@ -128,8 +220,8 @@ begin THE_CLOCK_RESET : entity work.clock_reset_handler port map( CLOCK_IN => CLK_200, - RESET_FROM_NET => med2int(0).stat_op(13), - SEND_RESET_IN => med2int(0).stat_op(15), + RESET_FROM_NET => '0',--med2int(0).stat_op(13), + SEND_RESET_IN => '0', --med2int(0).stat_op(15), BUS_RX => bustc_rx, BUS_TX => bustc_tx, @@ -144,6 +236,9 @@ begin DEBUG_OUT => debug_clock_reset ); + + + THE_ADC_PLL : entity work.adc_pll port map( @@ -152,123 +247,339 @@ begin CLKOS => clk_50, CLKOS2 => open ); - - CLK_A <= clk_50; - + + CLK_A <= clk_50; --------------------------------------------------------------------------- --- TrbNet Uplink +-- GbE --------------------------------------------------------------------------- - - THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync + GBE : entity work.gbe_wrapper generic map( - SERDES_NUM => 0, - USE_NEW_ECP5_RESET => 1, - IS_SYNC_SLAVE => c_YES + DO_SIMULATION => 0, + INCLUDE_DEBUG => 0, + USE_INTERNAL_TRBNET_DUMMY => 0, + USE_EXTERNAL_TRBNET_DUMMY => 0, + RX_PATH_ENABLE => 1, + FIXED_SIZE_MODE => 1, + INCREMENTAL_MODE => 1, + FIXED_SIZE => 100, + FIXED_DELAY_MODE => 1, + UP_DOWN_MODE => 0, + UP_DOWN_LIMIT => 100, + FIXED_DELAY => 100, + + NUMBER_OF_GBE_LINKS => 1, + LINKS_ACTIVE => "0001", + + LINK_HAS_READOUT => "0001", + LINK_HAS_SLOWCTRL => "0001", + LINK_HAS_DHCP => "0001", + -- LINK_HAS_ARP => "0001", + LINK_HAS_PING => "0001", + LINK_HAS_FWD => "0000" ) + port map( - CLK_REF_FULL => clk_full_osc, --med2int(0).clk_full, - CLK_INTERNAL_FULL => clk_full_osc, - SYSCLK => clk_sys, - RESET => reset_i, - CLEAR => clear_i, - --Internal Connection - MEDIA_MED2INT => med2int(0), - MEDIA_INT2MED => int2med(0), - - --Sync operation - RX_DLM => open, - RX_DLM_WORD => open, - TX_DLM => open, - TX_DLM_WORD => open, - - --SFP Connection - SD_PRSNT_N_IN => sfp_prsnt_i, - SD_LOS_IN => sfp_los_i, - SD_TXDIS_OUT => sfp_txdis_i, - --Control Interface - BUS_RX => bussci_rx, - BUS_TX => bussci_tx, - -- Status and control port - STAT_DEBUG => med_stat_debug(63 downto 0), - CTRL_DEBUG => open + CLK_SYS_IN => clk_sys, + CLK_125_IN => CLK_SUPPL_PCLK, + RESET => reset_i, + GSR_N => GSR_N, + + TRIGGER_IN => cts_rdo_rx.data_valid, + + SD_PRSNT_N_IN(0) => SFP_MOD0, + SD_LOS_IN(0) => SFP_LOS, + SD_TXDIS_OUT(0) => SFP_TX_DIS, + + CTS_NUMBER_IN => gbe_cts_number, + CTS_CODE_IN => gbe_cts_code, + CTS_INFORMATION_IN => gbe_cts_information, + CTS_READOUT_TYPE_IN => gbe_cts_readout_type, + CTS_START_READOUT_IN => gbe_cts_start_readout, + CTS_DATA_OUT => open, + CTS_DATAREADY_OUT => open, + CTS_READOUT_FINISHED_OUT => gbe_cts_readout_finished, + CTS_READ_IN => '1', + CTS_LENGTH_OUT => open, + CTS_ERROR_PATTERN_OUT => gbe_cts_status_bits, + + FEE_DATA_IN => gbe_fee_data, + FEE_DATAREADY_IN => gbe_fee_dataready, + FEE_READ_OUT => gbe_fee_read, + FEE_STATUS_BITS_IN => gbe_fee_status_bits, + FEE_BUSY_IN => gbe_fee_busy, + + MC_UNIQUE_ID_IN => timer.uid, + MY_TRBNET_ADDRESS_IN => timer.network_address, + ISSUE_REBOOT_OUT => reboot_from_gbe, + + GSC_CLK_IN => clk_sys, + GSC_INIT_DATAREADY_OUT => gsc_init_dataready, + GSC_INIT_DATA_OUT => gsc_init_data, + GSC_INIT_PACKET_NUM_OUT => gsc_init_packet_num, + GSC_INIT_READ_IN => gsc_init_read, + GSC_REPLY_DATAREADY_IN => gsc_reply_dataready, + GSC_REPLY_DATA_IN => gsc_reply_data, + GSC_REPLY_PACKET_NUM_IN => gsc_reply_packet_num, + GSC_REPLY_READ_OUT => gsc_reply_read, + GSC_BUSY_IN => gsc_busy, + + BUS_IP_RX => busgbeip_rx, + BUS_IP_TX => busgbeip_tx, + BUS_REG_RX => busgbereg_rx, + BUS_REG_TX => busgbereg_tx, + + MAKE_RESET_OUT => reset_via_gbe, + STATUS_OUT => status, --open, + DEBUG_OUT => open ); - gen_sfp_con : if SERDES_NUM = 1 generate - sfp_los_i <= SFP_LOS; - sfp_prsnt_i <= SFP_MOD_0; - SFP_TX_DIS <= sfp_txdis_i; - end generate; - gen_bpl_con : if SERDES_NUM = 0 generate - sfp_los_i <= BACK_GPIO(1); - sfp_prsnt_i <= BACK_GPIO(1); - BACK_GPIO(0) <= sfp_txdis_i; - end generate; - - --------------------------------------------------------------------------- --- Endpoint +-- Hub --------------------------------------------------------------------------- - THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record - generic map ( - ADDRESS_MASK => x"FFFF", - BROADCAST_BITMASK => BROADCAST_BITMASK, - REGIO_INIT_ENDPOINT_ID => x"0001", - REGIO_USE_1WIRE_INTERFACE => c_I2C, - TIMING_TRIGGER_RAW => c_YES, - --Configure data handler - DATA_INTERFACE_NUMBER => ACTIVE_CHANNELS, - DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE, - DATA_BUFFER_WIDTH => 32, - DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE, - TRG_RELEASE_AFTER_DATA => c_YES, - HEADER_BUFFER_DEPTH => 9, - HEADER_BUFFER_FULL_THRESH => 2**9-16, - USE_GBE => USE_GBE + THE_HUB : trb_net16_hub_streaming_port_sctrl_cts + generic map( + INIT_ADDRESS => INIT_ADDRESS, + MII_NUMBER => INTERFACE_NUM, + MII_IS_UPLINK => IS_UPLINK, + MII_IS_DOWNLINK => IS_DOWNLINK, + MII_IS_UPLINK_ONLY => IS_UPLINK_ONLY, + HARDWARE_VERSION => HARDWARE_INFO, + INCLUDED_FEATURES => INCLUDED_FEATURES, + INIT_ENDPOINT_ID => x"0001", + BROADCAST_BITMASK => x"7E", + CLOCK_FREQUENCY => 100, + USE_ONEWIRE => c_YES, + BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR, + RDO_ADDITIONAL_PORT => cts_rdo_additional_ports, + RDO_DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE, + RDO_DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE, + RDO_HEADER_BUFFER_DEPTH => 9, + RDO_HEADER_BUFFER_FULL_THRESH => 2**9-16 ) - - port map( - -- Misc - CLK => clk_sys, - RESET => reset_i, - CLK_125 => CLK_125, - CLEAR_N => GSR_N, - - -- Media direction port - MEDIA_MED2INT => med2int(0), - MEDIA_INT2MED => int2med(0), - - --Timing trigger in - TRG_TIMING_TRG_RECEIVED_IN => trigger_in_i, - - READOUT_RX => readout_rx, - READOUT_TX => readout_tx, - - --Slow Control Port - REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 - REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 - BUS_RX => ctrlbus_rx, - BUS_TX => ctrlbus_tx, + port map ( + CLK => clk_sys, + RESET => reset_i, + CLK_EN => '1', + + -- Media interfacces --------------------------------------------------------------- + MED_DATAREADY_OUT(INTERFACE_NUM*1-1 downto 0) => open, + MED_DATA_OUT(INTERFACE_NUM*16-1 downto 0) => open, + MED_PACKET_NUM_OUT(INTERFACE_NUM*3-1 downto 0) => open, + MED_READ_IN(INTERFACE_NUM*1-1 downto 0) => (others => '0'), + MED_DATAREADY_IN(INTERFACE_NUM*1-1 downto 0) => (others => '0'), + MED_DATA_IN(INTERFACE_NUM*16-1 downto 0) => (others => '0'), + MED_PACKET_NUM_IN(INTERFACE_NUM*3-1 downto 0) => (others => '0'), + MED_READ_OUT(INTERFACE_NUM*1-1 downto 0) => open, + MED_STAT_OP(INTERFACE_NUM*16-1 downto 0) => open, + MED_CTRL_OP(INTERFACE_NUM*16-1 downto 0) => (others => '0'), + + -- Gbe Read-out Path --------------------------------------------------------------- + --Event information coming from CTS for GbE + GBE_CTS_NUMBER_OUT => gbe_cts_number, + GBE_CTS_CODE_OUT => gbe_cts_code, + GBE_CTS_INFORMATION_OUT => gbe_cts_information, + GBE_CTS_READOUT_TYPE_OUT => gbe_cts_readout_type, + GBE_CTS_START_READOUT_OUT => gbe_cts_start_readout, + --Information sent to CTS + GBE_CTS_READOUT_FINISHED_IN => gbe_cts_readout_finished, + GBE_CTS_STATUS_BITS_IN => gbe_cts_status_bits, + -- Data from Frontends + GBE_FEE_DATA_OUT => gbe_fee_data, + GBE_FEE_DATAREADY_OUT => gbe_fee_dataready, + GBE_FEE_READ_IN => gbe_fee_read, + GBE_FEE_STATUS_BITS_OUT => gbe_fee_status_bits, + GBE_FEE_BUSY_OUT => gbe_fee_busy, + + -- CTS Request Sending ------------------------------------------------------------- + --LVL1 trigger + CTS_TRG_SEND_IN => cts_trg_send, + CTS_TRG_TYPE_IN => cts_trg_type, + CTS_TRG_NUMBER_IN => cts_trg_number, + CTS_TRG_INFORMATION_IN => cts_trg_information, + CTS_TRG_RND_CODE_IN => cts_trg_code, + CTS_TRG_STATUS_BITS_OUT => cts_trg_status_bits, + CTS_TRG_BUSY_OUT => cts_trg_busy, + --IPU Channel + CTS_IPU_SEND_IN => cts_ipu_send, + CTS_IPU_TYPE_IN => cts_ipu_type, + CTS_IPU_NUMBER_IN => cts_ipu_number, + CTS_IPU_INFORMATION_IN => cts_ipu_information, + CTS_IPU_RND_CODE_IN => cts_ipu_code, + -- Receiver port + CTS_IPU_STATUS_BITS_OUT => cts_ipu_status_bits, + CTS_IPU_BUSY_OUT => cts_ipu_busy, + + -- CTS Data Readout ---------------------------------------------------------------- + --Trigger to CTS out + RDO_TRIGGER_IN => cts_trigger_out, + RDO_TRG_DATA_VALID_OUT => cts_rdo_rx.data_valid, + RDO_VALID_TIMING_TRG_OUT => cts_rdo_rx.valid_timing_trg, + RDO_VALID_NOTIMING_TRG_OUT => cts_rdo_rx.valid_notiming_trg, + RDO_INVALID_TRG_OUT => cts_rdo_rx.invalid_trg, + RDO_TRG_TYPE_OUT => cts_rdo_rx.trg_type, + RDO_TRG_CODE_OUT => cts_rdo_rx.trg_code, + RDO_TRG_INFORMATION_OUT => cts_rdo_rx.trg_information, + RDO_TRG_NUMBER_OUT => cts_rdo_rx.trg_number, + + --Data from CTS in + RDO_TRG_STATUSBITS_IN => cts_rdo_trg_status_bits_cts, + RDO_DATA_IN => cts_rdo_data, + RDO_DATA_WRITE_IN => cts_rdo_write, + RDO_DATA_FINISHED_IN => cts_rdo_finished, + --Data from additional modules + RDO_ADDITIONAL_STATUSBITS_IN => cts_rdo_trg_status_bits_additional, + RDO_ADDITIONAL_DATA => cts_rdo_additional_data, + RDO_ADDITIONAL_WRITE => cts_rdo_additional_write, + RDO_ADDITIONAL_FINISHED => cts_rdo_additional_finished, + + -- Slow Control -------------------------------------------------------------------- + COMMON_STAT_REGS => open, + COMMON_CTRL_REGS => common_ctrl_reg, + ONEWIRE => TEMPSENS, + ONEWIRE_MONITOR_IN => open, + MY_ADDRESS_OUT => timer.network_address, + UNIQUE_ID_OUT => timer.uid, BUS_MASTER_IN => bus_master_in, BUS_MASTER_OUT => bus_master_out, BUS_MASTER_ACTIVE => bus_master_active, - - ONEWIRE_INOUT => open, - I2C_SCL => I2C_SCL, - I2C_SDA => I2C_SDA, - --Timing registers - TIMERS_OUT => timer, - STATUS_GBE_OUT=> gbe_status + TIMER_TICKS_OUT(0) => timer.tick_us, + TIMER_TICKS_OUT(1) => timer.tick_ms, + TEMPERATURE_OUT => timer.temperature, + EXTERNAL_SEND_RESET => reset_via_gbe, + + REGIO_ADDR_OUT => ctrlbus_rx.addr, + REGIO_READ_ENABLE_OUT => ctrlbus_rx.read, + REGIO_WRITE_ENABLE_OUT => ctrlbus_rx.write, + REGIO_DATA_OUT => ctrlbus_rx.data, + REGIO_DATA_IN => ctrlbus_tx.data, + REGIO_DATAREADY_IN => rdack, + REGIO_NO_MORE_DATA_IN => ctrlbus_tx.nack, + REGIO_WRITE_ACK_IN => wrack, + REGIO_UNKNOWN_ADDR_IN => ctrlbus_tx.unknown, + REGIO_TIMEOUT_OUT => ctrlbus_rx.timeout, + + --Gbe Sctrl Input + GSC_INIT_DATAREADY_IN => gsc_init_dataready, + GSC_INIT_DATA_IN => gsc_init_data, + GSC_INIT_PACKET_NUM_IN => gsc_init_packet_num, + GSC_INIT_READ_OUT => gsc_init_read, + GSC_REPLY_DATAREADY_OUT => gsc_reply_dataready, + GSC_REPLY_DATA_OUT => gsc_reply_data, + GSC_REPLY_PACKET_NUM_OUT => gsc_reply_packet_num, + GSC_REPLY_READ_IN => gsc_reply_read, + GSC_BUSY_OUT => gsc_busy, + + --status and control ports + HUB_STAT_CHANNEL => open, + HUB_STAT_GEN => open, + MPLEX_CTRL => (others => '0'), + MPLEX_STAT => open, + STAT_REGS => open, + STAT_CTRL_REGS => open, + + --Fixed status and control ports + STAT_DEBUG => open, + CTRL_DEBUG => (others => '0') ); + + gen_addition_ports : for i in 0 to cts_rdo_additional_ports-1 generate + cts_rdo_additional_data(31 + i*32 downto 32*i) <= cts_rdo_additional(i).data; + cts_rdo_trg_status_bits_additional(31 + i*32 downto 32*i) <= cts_rdo_additional(i).statusbits; + + cts_rdo_additional_write(i) <= cts_rdo_additional(i).data_write; + cts_rdo_additional_finished(i) <= cts_rdo_additional(i).data_finished; + + end generate; + + + rdack <= ctrlbus_tx.ack or ctrlbus_tx.rack; + wrack <= ctrlbus_tx.ack or ctrlbus_tx.wack; + + +--------------------------------------------------------------------------- +-- CTS +--------------------------------------------------------------------------- + THE_CTS : CTS + generic map ( + EXTERNAL_TRIGGER_ID => ETM_ID, -- fill in trigger logic enumeration id of external trigger logic + PLATTFORM => 6, --TRB5sc + OUTPUT_MULTIPLEXERS => CTS_OUTPUT_MULTIPLEXERS, + ADDON_GROUPS => 1, + ADDON_GROUP_UPPER => (12, others => 0) + ) + port map ( + CLK => clk_sys, + RESET => reset_i, + + TRIGGER_BUSY_OUT => trigger_busy_i, + TIME_REFERENCE_OUT => cts_trigger_out, + + ADDON_TRIGGERS_IN => cts_addon_triggers_in, + ADDON_GROUP_ACTIVITY_OUT => open, + ADDON_GROUP_SELECTED_OUT => open, + + EXT_TRIGGER_IN => '0', + EXT_STATUS_IN => (others => '0'), + EXT_CONTROL_OUT => open, + EXT_HEADER_BITS_IN => (others => '0'), + EXT_FORCE_TRIGGER_INFO_IN => (others => '0'), + + PERIPH_TRIGGER_IN => (others => '0'), + + OUTPUT_MULTIPLEXERS_OUT => cts_monitor_out, + + CTS_TRG_SEND_OUT => cts_trg_send, + CTS_TRG_TYPE_OUT => cts_trg_type, + CTS_TRG_NUMBER_OUT => cts_trg_number, + CTS_TRG_INFORMATION_OUT => cts_trg_information, + CTS_TRG_RND_CODE_OUT => cts_trg_code, + CTS_TRG_STATUS_BITS_IN => cts_trg_status_bits, + CTS_TRG_BUSY_IN => cts_trg_busy, + + CTS_IPU_SEND_OUT => cts_ipu_send, + CTS_IPU_TYPE_OUT => cts_ipu_type, + CTS_IPU_NUMBER_OUT => cts_ipu_number, + CTS_IPU_INFORMATION_OUT => cts_ipu_information, + CTS_IPU_RND_CODE_OUT => cts_ipu_code, + CTS_IPU_STATUS_BITS_IN => cts_ipu_status_bits, + CTS_IPU_BUSY_IN => cts_ipu_busy, + + CTS_REGIO_ADDR_IN => buscts_rx.addr, + CTS_REGIO_DATA_IN => buscts_rx.data, + CTS_REGIO_READ_ENABLE_IN => buscts_rx.read, + CTS_REGIO_WRITE_ENABLE_IN => buscts_rx.write, + CTS_REGIO_DATA_OUT => buscts_tx.data, + CTS_REGIO_DATAREADY_OUT => buscts_tx.rack, + CTS_REGIO_WRITE_ACK_OUT => buscts_tx.wack, + CTS_REGIO_UNKNOWN_ADDR_OUT => buscts_tx.unknown, + + LVL1_TRG_DATA_VALID_IN => cts_rdo_rx.data_valid, + LVL1_VALID_TIMING_TRG_IN => cts_rdo_rx.valid_timing_trg, + LVL1_VALID_NOTIMING_TRG_IN => cts_rdo_rx.valid_notiming_trg, + LVL1_INVALID_TRG_IN => cts_rdo_rx.invalid_trg, + + FEE_TRG_STATUSBITS_OUT => cts_rdo_trg_status_bits_cts, + FEE_DATA_OUT => cts_rdo_data, + FEE_DATA_WRITE_OUT => cts_rdo_write, + FEE_DATA_FINISHED_OUT => cts_rdo_finished + ); + + cts_addon_triggers_in(12 downto 4) <= HDR_IO(23 downto 16); + cts_addon_triggers_in( 3 downto 0) <= trigger_gen_outputs_i; + + buscts_tx.nack <= '0'; + buscts_tx.ack <= '0'; + --------------------------------------------------------------------------- -- Bus Handler --------------------------------------------------------------------------- THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record generic map( PORT_NUMBER => 4, - PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"9000", others => x"0000"), - PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, others => 0), + PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"9000", 4 => x"8100", 5 => x"8300", 6 => x"a000", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, 4 => 8, 5 => 8, 6 => 11, others => 0), PORT_MASK_ENABLE => 1 ) port map( @@ -282,10 +593,17 @@ begin BUS_RX(1) => bussci_rx, --SCI Serdes BUS_RX(2) => bustc_rx, --Clock switch BUS_RX(3) => busadc_rx, + BUS_RX(4) => busgbeip_rx, + BUS_RX(5) => busgbereg_rx, + BUS_RX(6) => buscts_rx, + BUS_TX(0) => bustools_tx, BUS_TX(1) => bussci_tx, BUS_TX(2) => bustc_tx, BUS_TX(3) => busadc_tx, + BUS_TX(4) => busgbeip_tx, + BUS_TX(5) => busgbereg_tx, + BUS_TX(6) => buscts_tx, STAT_DEBUG => open ); @@ -310,7 +628,7 @@ begin FLASH_IN => FLASH_MISO, FLASH_OUT => FLASH_MOSI, PROGRAMN => PROGRAMN, - REBOOT_IN => common_ctrl_reg(15), + REBOOT_IN => common_ctrl_reg(15) or reboot_from_gbe, --SPI SPI_CS_OUT => spi_cs, SPI_MOSI_OUT => spi_mosi, @@ -332,8 +650,8 @@ begin TRIG_GEN_INPUTS(11 downto 0) => adc_trigger_i, TRIG_GEN_INPUTS(15 downto 12) => x"0", - TRIG_GEN_OUTPUTS(1 downto 0) => BACK_GPIO(3 downto 2), - TRIG_GEN_OUTPUTS(3 downto 2) => SPARE(1 downto 0), + TRIG_GEN_OUTPUTS(3 downto 0) => trigger_gen_outputs_i, + --SED SED_ERROR_OUT => sed_error_i, --Slowcontrol @@ -357,10 +675,12 @@ begin SDIO_A <= spi_mosi(0); spi_miso(0) <= SDIO_A when rising_edge(clk_sys); - + + + --------------------------------------------------------------------------- -- ADC ADDON ---------------------------------------------------------------------------- +--------------------------------------------------------------------------- THE_ADDON : entity work.adc_addon generic map( ACTIVE_CHANNELS => ACTIVE_CHANNELS @@ -370,24 +690,24 @@ begin CLK_ADCBRAW => clk_full_osc, CLK_ADCRAW => clk_350, RESET => reset_i, - + FCO_A => FCO_A, DATA_A => DATA_A, DCO_A => DCO_A, - - DCO_B => DCO_B, - DATA_B => DATA_B, - CLK_B => CLK_B, - CNV_B => CNV_B, + + DCO_B => DCO_B, + DATA_B => DATA_B, + CLK_B => CLK_B, + CNV_B => CNV_B, TESTPAT_B => TESTPAT_B, - + TRIGGER_OUT => adc_trigger_i(ACTIVE_CHANNELS-1 downto 0), READOUT_RX => readout_rx, READOUT_TX => readout_tx, - + BUS_RX => busadc_rx, BUS_TX => busadc_tx - + ); @@ -410,7 +730,12 @@ begin FLASH_NCS <= flash_ncs_i; - +------------------------------------------------------------------------------- +-- No trigger/data endpoint included +------------------------------------------------------------------------------- +readout_tx(0).data_finished <= '1'; +readout_tx(0).data_write <= '0'; +readout_tx(0).busy_release <= '1'; end architecture;