From: hadeshyp Date: Mon, 24 Aug 2009 14:43:18 +0000 (+0000) Subject: added reset for fot & lvds X-Git-Tag: oldGBE~393 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=954af85fabacb0210e42cd554cb3e38dfb0260ce;p=trbnet.git added reset for fot & lvds --- diff --git a/media_interfaces/trb_net16_med_ecp_fot.vhd b/media_interfaces/trb_net16_med_ecp_fot.vhd index 4694622..fe93f80 100644 --- a/media_interfaces/trb_net16_med_ecp_fot.vhd +++ b/media_interfaces/trb_net16_med_ecp_fot.vhd @@ -192,6 +192,13 @@ attribute HGROUP of trb_net16_med_ecp_fot_arch : architecture is "GROUP_PCS"; signal FSM_STAT_DEBUG : std_logic_vector(64-1 downto 0); signal FSM_CTRL_OP : std_logic_vector(16-1 downto 0); + signal send_reset_q : std_logic; + signal reset_word_cnt : std_logic_vector(4 downto 0); + signal send_reset_words : std_logic; + signal send_reset_words_q : std_logic; + signal make_trbnet_reset : std_logic; + signal make_trbnet_reset_q: std_logic; + begin --ff_rxfullclk <= clk_25; @@ -292,6 +299,12 @@ begin tx_k <= '0'; tx_data(7 downto 0) <= tx_fifo_dout(7 downto 0); tx_fifo_read_en <= tx_allow_qtx; + elsif send_reset_q = '1' then + byte_buffer(7 downto 0) <= x"FE"; + byte_waiting <= '1'; + tx_k <= '1'; + tx_data(7 downto 0) <= x"FE"; + tx_fifo_read_en <= '0'; else byte_buffer(7 downto 0) <= x"50"; byte_waiting <= '1'; @@ -371,6 +384,32 @@ begin end if; end process THE_WRITE_RX_FIFO_PROC; + + THE_CNT_RESET_PROC : process( ff_rxfullclk ) + begin + if rising_edge(ff_rxfullclk) then + if reset = '1' then + send_reset_words <= '0'; + make_trbnet_reset <= '0'; + reset_word_cnt(4 downto 0) <= (others => '0'); + else + send_reset_words <= '0'; + make_trbnet_reset <= '0'; + if buf_rx_data(7 downto 0) = x"FE" and buf_rx_k = '1' then + if reset_word_cnt(4) = '0' then + reset_word_cnt(4 downto 0) <= reset_word_cnt(4 downto 0) + 1; + else + send_reset_words <= '1'; + end if; + else + reset_word_cnt(4 downto 0) <= (others => '0'); + make_trbnet_reset <= reset_word_cnt(4); + end if; + end if; + end if; + end process; + + --TX Control (100) --------------------- buf_med_read_out <= not tx_fifo_full and tx_allow_del; @@ -513,6 +552,35 @@ begin D_OUT(0) => rx_allow_qrx ); + + SYNC_RESET_DETECT_1 : signal_sync + generic map( + DEPTH => 2, + WIDTH => 1 + ) + port map( + RESET => reset, + D_IN(0) => send_reset_words, + CLK0 => CLK, + CLK1 => CLK, + D_OUT(0) => send_reset_words_q + ); + + SYNC_RESET_DETECT_2 : signal_sync + generic map( + DEPTH => 2, + WIDTH => 1 + ) + port map( + RESET => reset, + D_IN(0) => make_trbnet_reset, + CLK0 => CLK, + CLK1 => CLK, + D_OUT(0) => make_trbnet_reset_q + ); + + + --LED Signals --------------------- THE_TX_RX_LED_PROC: process( clk ) @@ -575,7 +643,10 @@ begin STAT_OP(9 downto 0) <= FSM_STAT_OP(9 downto 0); STAT_OP(10) <= rx_led; STAT_OP(11) <= tx_led; - STAT_OP(15 downto 12) <= FSM_STAT_OP(15 downto 12); + STAT_OP(12) <= FSM_STAT_OP(12); + STAT_OP(13) <= make_trbnet_reset_q; + STAT_OP(14) <= FSM_STAT_OP(14); + STAT_OP(15) <= send_reset_words_q; STAT_DEBUG(31 downto 0) <= FSM_STAT_DEBUG(31 downto 0); STAT_DEBUG(39 downto 32) <= buf_rx_data_reg(7 downto 0); diff --git a/media_interfaces/trb_net16_med_ecp_fot_4.vhd b/media_interfaces/trb_net16_med_ecp_fot_4.vhd index 7158599..f9b615a 100644 --- a/media_interfaces/trb_net16_med_ecp_fot_4.vhd +++ b/media_interfaces/trb_net16_med_ecp_fot_4.vhd @@ -297,6 +297,14 @@ component serdes_fot_full_quad is signal FSM_STAT_DEBUG : std_logic_vector(4*64-1 downto 0); signal FSM_CTRL_OP : std_logic_vector(4*16-1 downto 0); + signal send_reset_q : std_logic_vector(3 downto 0); + signal reset_word_cnt : std_logic_vector(19 downto 0); + signal send_reset_words : std_logic_vector(3 downto 0); + signal send_reset_words_q : std_logic_vector(3 downto 0); + signal make_trbnet_reset : std_logic_vector(3 downto 0); + signal make_trbnet_reset_q: std_logic_vector(3 downto 0); + + attribute syn_keep : boolean; attribute syn_keep of led_counter : signal is true; @@ -617,7 +625,7 @@ begin byte_waiting(i) <= '0'; tx_fifo_read_en(i) <= '0'; tx_k(i) <= '1'; - tx_data((i+1)*8-1 downto i*8) <= x"EE"; + tx_data((i+1)*8-1 downto i*8) <= x"FE"; tx_fifo_valid_read(i) <= '0'; else tx_fifo_read_en(i) <= tx_allow_qtx(i); @@ -629,6 +637,12 @@ begin tx_k(i) <= '0'; tx_data((i+1)*8-1 downto i*8) <= tx_fifo_dout(i*16+7 downto i*16+0); tx_fifo_read_en(i) <= tx_allow_qtx(i); + elsif send_reset_q(i) = '1' then + byte_buffer((i+1)*8-1 downto i*8) <= x"FE"; + byte_waiting(i) <= '1'; + tx_k(i) <= '1'; + tx_data((i+1)*8-1 downto i*8) <= x"FE"; + tx_fifo_read_en(i) <= '0'; else byte_buffer((i+1)*8-1 downto i*8) <= x"50"; byte_waiting(i) <= '1'; @@ -638,7 +652,7 @@ begin end if; else --if byte_waiting = '1' then tx_data((i+1)*8-1 downto i*8) <= byte_buffer((i+1)*8-1 downto i*8); - tx_k(i) <= '0'; --second byte is always data + tx_k(i) <= send_reset_q(i); --second byte is always data byte_waiting(i) <= '0'; tx_fifo_read_en(i) <= '0'; end if; @@ -710,6 +724,33 @@ begin end if; end process THE_WRITE_RX_FIFO_PROC; + + THE_CNT_RESET_PROC : process( ff_rxfullclk ) + begin + if rising_edge(ff_rxfullclk(i)) then + if reset = '1' then + send_reset_words(i) <= '0'; + make_trbnet_reset(i) <= '0'; + reset_word_cnt(i*5+4 downto i*5) <= (others => '0'); + else + send_reset_words(i) <= '0'; + make_trbnet_reset(i) <= '0'; + if buf_rx_data(i*8+7 downto i*8) = x"FE" and buf_rx_k(i) = '1' then + if reset_word_cnt(i*5+4) = '0' then + reset_word_cnt(i*5+4 downto i*5) <= reset_word_cnt(i*5+4 downto i*5) + 1; + else + send_reset_words(i) <= '1'; + end if; + else + reset_word_cnt(i*5+4 downto i*5) <= (others => '0'); + make_trbnet_reset(i) <= reset_word_cnt(i*5+4); + end if; + end if; + end if; + end process; + + + --TX Control (100) --------------------- buf_med_read_out(i) <= not tx_fifo_full(i) and tx_allow_del(i); @@ -780,18 +821,20 @@ begin CLK_TO_TX_SYNC: signal_sync generic map( DEPTH => 2, - WIDTH => 3 + WIDTH => 4 ) port map( RESET => reset, D_IN(0) => tx_allow(i), D_IN(1) => lane_rst(i), D_IN(2) => quad_rst(i), + D_IN(3) => CTRL_OP(15+i*16), CLK0 => CLK, CLK1 => ff_txfullclk, D_OUT(0) => tx_allow_qtx(i), D_OUT(1) => lane_rst_qtx(i), - D_OUT(2) => quad_rst_qtx(i) + D_OUT(2) => quad_rst_qtx(i), + D_OUT(3) => send_reset_q(i) ); TX_TO_CLK_SYNC: signal_sync @@ -840,6 +883,33 @@ begin D_OUT(2) => rx_allow_del(i) ); + + SYNC_RESET_DETECT_1 : signal_sync + generic map( + DEPTH => 2, + WIDTH => 4 + ) + port map( + RESET => reset, + D_IN => send_reset_words, + CLK0 => CLK, + CLK1 => CLK, + D_OUT => send_reset_words_q + ); + + SYNC_RESET_DETECT_2 : signal_sync + generic map( + DEPTH => 2, + WIDTH => 4 + ) + port map( + RESET => reset, + D_IN => make_trbnet_reset, + CLK0 => CLK, + CLK1 => CLK, + D_OUT => make_trbnet_reset_q + ); + THE_SFP_STATUS_SYNC: signal_sync generic map( DEPTH => 2, @@ -875,7 +945,10 @@ begin STAT_OP(i*16+9 downto i*16+0) <= FSM_STAT_OP(i*16+9 downto i*16+0); STAT_OP(i*16+10) <= rx_led(i); STAT_OP(i*16+11) <= tx_led(i); - STAT_OP(i*16+15 downto i*16+12) <= FSM_STAT_OP(i*16+15 downto i*16+12); + STAT_OP(i*16+12) <= FSM_STAT_OP(i*16+12); + STAT_OP(i*16+13) <= make_trbnet_reset_q(i); + STAT_OP(i*16+14) <= FSM_STAT_OP(i*16+14); + STAT_OP(i*16+15) <= send_reset_words_q(i); STAT_DEBUG(i*64+31 downto i*64+0) <= FSM_STAT_DEBUG(i*32+31 downto i*32); STAT_DEBUG(i*64+39 downto i*64+32) <= buf_rx_data_reg(i*8+7 downto i*8); diff --git a/special/trb2_control_endpoint_tlk.vhd b/special/trb2_control_endpoint_tlk.vhd index 4720c53..e64b5a7 100644 --- a/special/trb2_control_endpoint_tlk.vhd +++ b/special/trb2_control_endpoint_tlk.vhd @@ -383,6 +383,6 @@ begin -- D2D3: 31 downto 16 -- A0A1: 46 downto 32 - ADO_TTL(46 downto 0) <= buf_ADO_TTL(46 downto 0); + ADO_TTL(46 downto 0) <= (others => 'Z'); --buf_ADO_TTL(46 downto 0); end architecture; diff --git a/special/trb_net_bridge_etrax_endpoint.vhd b/special/trb_net_bridge_etrax_endpoint.vhd index 962884f..6f520a2 100644 --- a/special/trb_net_bridge_etrax_endpoint.vhd +++ b/special/trb_net_bridge_etrax_endpoint.vhd @@ -719,8 +719,8 @@ STAT_ENDP(23) <= APL_READ_IN(3); STAT_ENDP(31 downto 24) <= APL_DATA_OUT(55 downto 48); -STAT_API1(3 downto 0) <= apl_to_buf_REPLY_DATA(23 downto 16); -STAT_API1(7 downto 4) <= apl_to_buf_REPLY_DATA(23 downto 16); +STAT_API1(3 downto 0) <= apl_to_buf_REPLY_DATA(19 downto 16); +STAT_API1(7 downto 4) <= apl_to_buf_REPLY_DATA(19 downto 16); STAT_API1(11) <= apl_to_buf_REPLY_READ(3); STAT_API1(12) <= buf_to_apl_REPLY_DATAREADY(3); diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd index 87f626b..c853596 100644 --- a/trb_net16_hub_base.vhd +++ b/trb_net16_hub_base.vhd @@ -20,6 +20,7 @@ entity trb_net16_hub_base is INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := (others => '0'); COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; + INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; CLOCK_FREQUENCY : integer range 1 to 200 := 100; USE_ONEWIRE : integer range 0 to 2 := c_YES; @@ -227,7 +228,7 @@ begin --generate media resync gen_resync : for i in 0 to MII_NUMBER-1 generate - resync(i) <= MED_STAT_OP(i*16+15); + resync(i) <= MED_STAT_OP(i*16+15) when MII_IS_UPLINK(i) = c_YES else '0'; MED_CTRL_OP(13+i*16 downto i*16) <= (others => '0'); MED_CTRL_OP(14+i*16) <= HUB_CTRL_media_interfaces_off(i); MED_CTRL_OP(15+i*16) <= combined_resync; @@ -724,6 +725,7 @@ MED_DATA_OUT <= buf_MED_DATA_OUT; USE_DAT_PORT => c_NO, INIT_ADDRESS => INIT_ADDRESS, INIT_UNIQUE_ID => INIT_UNIQUE_ID, + INIT_ENDPOINT_ID => INIT_ENDPOINT_ID, COMPILE_TIME => COMPILE_TIME, COMPILE_VERSION => COMPILE_VERSION, HARDWARE_VERSION => HARDWARE_VERSION, diff --git a/trb_net16_med_16_CC.vhd b/trb_net16_med_16_CC.vhd index 1c9d847..1e75707 100644 --- a/trb_net16_med_16_CC.vhd +++ b/trb_net16_med_16_CC.vhd @@ -80,14 +80,15 @@ architecture trb_net16_med_16_CC_arch of trb_net16_med_16_CC is signal buf_MED_PACKET_NUM_OUT : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal buf_MED_DATA_OUT : std_logic_vector(c_DATA_WIDTH-1 downto 0); - signal trbnet_reset : std_logic; - signal resync_needed: std_logic; + signal not_connected : std_logic; + signal resync_received: std_logic; type link_state_t is (STARTUP, WAITING, WORKING, RESYNCING, RESYNC_WAIT); signal link_state : link_state_t; signal med_error : std_logic_vector(2 downto 0); - signal pattern_counter : unsigned(3 downto 0); + signal pattern_counter : unsigned(11 downto 0); signal pattern_detected : std_logic; signal state_bits : std_logic_vector(2 downto 0); + signal make_reset : std_logic; begin @@ -160,15 +161,15 @@ begin STAT_OP(10) <= rx_led; STAT_OP(11) <= tx_led; STAT_OP(12) <= '0'; - STAT_OP(13) <= '0'; - STAT_OP(14) <= trbnet_reset; - STAT_OP(15) <= resync_needed; + STAT_OP(13) <= make_reset; + STAT_OP(14) <= not_connected; + STAT_OP(15) <= resync_received; PROC_LED : process(CLK) begin if rising_edge(CLK) then - if RESET = '1' or trbnet_reset = '1' then + if RESET = '1' or not_connected = '1' then led_counter <= (others => '0'); rx_led <= '0'; tx_led <= '0'; @@ -211,20 +212,20 @@ begin if RESET = '1' then link_state <= STARTUP; link_running <= '0'; - resync_needed <= '0'; - trbnet_reset <= '1'; - resync <= '0'; + resync_received <= '0'; + not_connected <= '1'; + make_reset <= '0'; else case link_state is when STARTUP => med_error <= ERROR_NC; link_running <= '0'; - trbnet_reset <= '1'; - resync_needed <= '0'; + not_connected <= '1'; + resync_received <= '0'; if pattern_detected = '1' then - trbnet_reset <= '0'; + not_connected <= '0'; link_state <= WAITING; - pattern_counter <= x"4"; + pattern_counter <= x"040"; end if; when WAITING => @@ -232,48 +233,53 @@ begin if pattern_detected = '1' and reg_DATA_VALID_IN = '0' then pattern_counter <= pattern_counter + "1"; elsif pattern_detected = '0' then - pattern_counter <= pattern_counter - x"4"; + pattern_counter <= pattern_counter - x"40"; end if; - if pattern_counter < x"4" then + if pattern_counter < x"040" then link_state <= STARTUP; - elsif pattern_counter = x"F" then + elsif pattern_counter = x"FFF" then link_state <= WORKING; end if; when WORKING => med_error <= ERROR_OK; link_running <= '1'; - if CTRL_OP(15) = '1' then - link_state <= RESYNCING; - resync_counter <= (others => '0'); - link_running <= '0'; - end if; - if (reg_DATA_VALID_IN = '1' and reg_DATA_CTRL_IN = '1' and rx_counter /= c_H0) - or (reg_DATA_VALID_IN = '1' and reg_DATA_CTRL_IN = '0' and rx_counter = c_H0) then - resync_needed <= '1'; +-- if CTRL_OP(15) = '1' then +-- link_state <= RESYNCING; +-- resync_counter <= (others => '0'); +-- link_running <= '0'; +-- end if; +-- if (reg_DATA_VALID_IN = '1' and reg_DATA_CTRL_IN = '1' and rx_counter /= c_H0) +-- or (reg_DATA_VALID_IN = '1' and reg_DATA_CTRL_IN = '0' and rx_counter = c_H0) then +-- resync_needed <= '1'; +-- else +-- resync_needed <= '0'; +-- end if; + if reg_DATA_VALID_IN = '0' and reg_DATA_IN = x"FEFE" then + resync_received <= '1'; else - resync_needed <= '0'; + resync_received <= '0'; + make_reset <= resync_received; end if; + if pattern_detected = '0' then link_running <= '0'; link_state <= STARTUP; end if; - when RESYNCING => - med_error <= ERROR_WAIT; - resync <= '1'; - resync_counter <= resync_counter + "1"; - if resync_counter = x"F" then - resync <= '0'; - resync_counter <= (others => '0'); - link_state <= RESYNC_WAIT; - end if; +-- when RESYNCING => +-- med_error <= ERROR_WAIT; +-- resync <= '1'; +-- if CTRL_OP(15) = '0' then +-- resync <= '0'; +-- link_state <= RESYNC_WAIT; +-- end if; when RESYNC_WAIT => med_error <= ERROR_WAIT; if reg_DATA_VALID_IN = '0' and reg_DATA_IN = x"AAAA" then link_state <= WAITING; - pattern_counter <= x"4"; + pattern_counter <= x"040"; elsif pattern_detected = '0' then link_state <= STARTUP; end if; @@ -306,10 +312,10 @@ begin buf_DATA_CTRL_OUT <= '0'; buf_DATA_OUT <= (others => '0'); PRESENT_SIG <= '0'; - elsif resync = '1' then + elsif CTRL_OP(15) = '1' then buf_DATA_VALID_OUT <= '0'; - buf_DATA_CTRL_OUT <= '1'; - buf_DATA_OUT <= x"EEEE"; + buf_DATA_CTRL_OUT <= not buf_DATA_CTRL_OUT; + buf_DATA_OUT <= x"FEFE"; elsif MED_DATAREADY_IN = '1' and buf_MED_READ_OUT = '1' then buf_DATA_VALID_OUT <= '1'; buf_DATA_OUT <= MED_DATA_IN; @@ -346,7 +352,7 @@ begin STAT_DEBUG(15 downto 0) <= reg_DATA_IN; STAT_DEBUG(16) <= reg_DATA_VALID_IN; STAT_DEBUG(17) <= reg_DATA_CTRL_IN; -STAT_DEBUG(18) <= resync_needed; +STAT_DEBUG(18) <= resync_received; STAT_DEBUG(22 downto 19)<= std_logic_vector(pattern_counter(3 downto 0)); STAT_DEBUG(23) <= resync; STAT_DEBUG(26 downto 24)<= state_bits; diff --git a/trb_net_components.vhd b/trb_net_components.vhd index 2eaec76..9d55c62 100644 --- a/trb_net_components.vhd +++ b/trb_net_components.vhd @@ -176,7 +176,7 @@ package trb_net_components is FEE_BUSY_OUT : out std_logic; MY_ADDRESS_IN : in std_logic_vector (15 downto 0); - CTRL_SEQNR_RESET : in std_logic; + CTRL_SEQNR_RESET : in std_logic ); end component;