From: Thomas Gessler Date: Fri, 11 Sep 2020 14:18:25 +0000 (+0200) Subject: Change to new MGT clocking scheme X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=96a887dd27a824f6ba20321d2f6671961d606ee5;p=cri.git Change to new MGT clocking scheme --- diff --git a/endpoint_test/constrs/endpoint_test.xdc b/endpoint_test/constrs/endpoint_test.xdc index 1a4d183..c514247 100644 --- a/endpoint_test/constrs/endpoint_test.xdc +++ b/endpoint_test/constrs/endpoint_test.xdc @@ -1,7 +1,7 @@ set_property PACKAGE_PIN AK38 [get_ports MGTREFCLK_N] set_property PACKAGE_PIN AK37 [get_ports MGTREFCLK_P] -create_clock -period 8.000 -name MGTREFCLK_P [get_ports MGTREFCLK_P] +create_clock -period 10.000 -name MGTREFCLK_P [get_ports MGTREFCLK_P] set_property PACKAGE_PIN AT18 [get_ports CLK_200_P] set_property IOSTANDARD LVDS [get_ports CLK_200_P] diff --git a/endpoint_test/endpoint_test.xpr b/endpoint_test/endpoint_test.xpr index afb4a2d..37a721b 100644 --- a/endpoint_test/endpoint_test.xpr +++ b/endpoint_test/endpoint_test.xpr @@ -115,7 +115,7 @@ - + @@ -193,7 +193,7 @@ - + @@ -205,7 +205,7 @@ - + diff --git a/endpoint_test/src/endpoint_test.vhd b/endpoint_test/src/endpoint_test.vhd index d9acadf..f90789a 100644 --- a/endpoint_test/src/endpoint_test.vhd +++ b/endpoint_test/src/endpoint_test.vhd @@ -13,10 +13,10 @@ entity endpoint_test is MGTREFCLK_P : in std_logic; MGTREFCLK_N : in std_logic; - RXN : in std_logic; - RXP : in std_logic; - TXN : out std_logic; - TXP : out std_logic; + RXN : in std_logic_vector(3 downto 0); + RXP : in std_logic_vector(3 downto 0); + TXN : out std_logic_vector(3 downto 0); + TXP : out std_logic_vector(3 downto 0); CLK_200_P : in std_logic; CLK_200_N : in std_logic; @@ -66,6 +66,8 @@ architecture behavioral of endpoint_test is signal med2int_i : MED2INT; signal int2med_i : INT2MED; + signal med2int_unused : med2int_array_t(0 to 2); + signal int2med_unused : int2med_array_t(0 to 2); signal ctrlbus_rx_i : CTRLBUS_RX; signal bustools_rx : CTRLBUS_RX; @@ -80,6 +82,26 @@ architecture behavioral of endpoint_test is signal bus_master_in : CTRLBUS_TX; signal readout_tx_i : READOUT_TX; + + signal txpmaresetdone : std_logic_vector(3 downto 0); + signal userclk_tx_reset : std_logic; + signal txoutclk : std_logic_vector(3 downto 0); + + signal usrclk_active_meta : std_logic := '0'; + signal usrclk_active : std_logic := '0'; + signal not_usrclk_active : std_logic; + + attribute ASYNC_REG : string; + attribute ASYNC_REG of usrclk_active_meta : signal is "true"; + attribute ASYNC_REG of usrclk_active : signal is "true"; + + signal usrclk_int : std_logic; + signal usrclk_mmcm_fb : std_logic; + signal usrclk : std_logic; + signal usrclk_double : std_logic; + + signal usrclk_vector : std_logic_vector(3 downto 0); + signal usrclk_double_vector : std_logic_vector(3 downto 0); begin MPOD_RESET_N <= "1111"; @@ -142,35 +164,138 @@ begin DEBUG_OUT => open ); + usrclk_vector <= usrclk & usrclk & usrclk & usrclk; + usrclk_double_vector <= usrclk_double & usrclk_double & usrclk_double + & usrclk_double; + + THE_MEDIA_INTERFACE : entity work.med_xcku_sfp_sync_4 + generic map ( + IS_SYNC_SLAVE => (c_YES, c_NO, c_NO, c_NO), + IS_USED => (c_YES, c_NO, c_NO, c_NO) + ) + port map ( + SYSCLK => sysclk_100, + CLK_200 => sysclk_200, + GTREFCLK => mgtrefclk, + RXOUTCLK => open, + TXOUTCLK => txoutclk, + RXUSRCLK => usrclk_vector, + RXUSRCLK_DOUBLE => usrclk_double_vector, + TXUSRCLK => usrclk_vector, + TXUSRCLK_DOUBLE => usrclk_double_vector, + RXUSRCLK_ACTIVE => usrclk_active, + TXUSRCLK_ACTIVE => usrclk_active, + RXPMARESETDONE => open, + TXPMARESETDONE => txpmaresetdone, + RESET => reset, + CLEAR => clear, + RXN => RXN, + RXP => RXP, + TXN => TXN, + TXP => TXP, + MEDIA_MED2INT(0) => med2int_i, + MEDIA_MED2INT(1 to 3) => med2int_unused, + MEDIA_INT2MED(0) => int2med_i, + MEDIA_INT2MED(1 to 3) => int2med_unused, + RX_DLM => open, + RX_DLM_WORD => open, + TX_DLM => open, + TX_DLM_WORD => open, + SD_LOS_IN => "0000", + SD_TXDIS_OUT => open, + BUS_RX => bussci_rx, + BUS_TX => bussci_tx, + STAT_DEBUG => open, + CTRL_DEBUG => open + ); + + userclk_tx_reset <= not txpmaresetdone(0); + + bufg_gt_usrclk_inst : BUFG_GT + port map ( + O => usrclk_int, + CE => '1', + CEMASK => '0', + CLR => userclk_tx_reset, + CLRMASK => '0', + DIV => "000", + I => txoutclk(0) + ); + + -- Indicate active helper block functionality when the BUFG_GT divider is + -- not held in reset + process (userclk_tx_reset, usrclk_int) is + begin + if userclk_tx_reset = '1' then + usrclk_active_meta <= '0'; + usrclk_active <= '0'; + elsif rising_edge(usrclk_int) then + usrclk_active_meta <= '1'; + usrclk_active <= usrclk_active_meta; + end if; + end process; - THE_MEDIA_INTERFACE : entity work.med_xcku_sfp_sync + not_usrclk_active <= not usrclk_active; + + mmcme3_adv_usrclk : MMCME3_ADV generic map ( - IS_SYNC_SLAVE => c_YES + BANDWIDTH => "OPTIMIZED", + CLKOUT4_CASCADE => "FALSE", + COMPENSATION => "AUTO", + STARTUP_WAIT => "FALSE", + DIVCLK_DIVIDE => 1, + CLKFBOUT_MULT_F => 10.000, + CLKFBOUT_PHASE => 0.000, + CLKFBOUT_USE_FINE_PS => "FALSE", + CLKOUT0_DIVIDE_F => 10.000, + CLKOUT0_PHASE => 0.000, + CLKOUT0_DUTY_CYCLE => 0.500, + CLKOUT0_USE_FINE_PS => "FALSE", + CLKOUT1_DIVIDE => 5, + CLKOUT1_PHASE => 0.000, + CLKOUT1_DUTY_CYCLE => 0.500, + CLKOUT1_USE_FINE_PS => "FALSE", + CLKIN1_PERIOD => 10.000 ) port map ( - SYSCLK => sysclk_100, - CLK_200 => sysclk_200, - GTREFCLK => mgtrefclk, - RESET => reset, - CLEAR => clear, - RXN => RXN, - RXP => RXP, - TXN => TXN, - TXP => TXP, - MEDIA_MED2INT => med2int_i, - MEDIA_INT2MED => int2med_i, - RX_DLM => open, - RX_DLM_WORD => open, - TX_DLM => open, - TX_DLM_WORD => open, - SD_LOS_IN => '0', - SD_TXDIS_OUT => open, - BUS_RX => bussci_rx, - BUS_TX => bussci_tx, - STAT_DEBUG => open, - CTRL_DEBUG => open + CLKFBOUT => usrclk_mmcm_fb, + CLKFBOUTB => open, + CLKOUT0 => usrclk, + CLKOUT0B => open, + CLKOUT1 => usrclk_double, + CLKOUT1B => open, + CLKOUT2 => open, + CLKOUT2B => open, + CLKOUT3 => open, + CLKOUT3B => open, + CLKOUT4 => open, + CLKOUT5 => open, + CLKOUT6 => open, + CLKFBIN => usrclk_mmcm_fb, + CLKIN1 => usrclk_int, + CLKIN2 => '0', + CLKINSEL => '1', + DADDR => "0000000", + DCLK => '0', + DEN => '0', + DI => x"0000", + DO => open, + DRDY => open, + DWE => '0', + CDDCDONE => open, + CDDCREQ => '0', + PSCLK => '0', + PSEN => '0', + PSINCDEC => '0', + PSDONE => open, + LOCKED => open, + CLKINSTOPPED => open, + CLKFBSTOPPED => open, + PWRDWN => '0', + RST => not_usrclk_active ); + THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record generic map ( ADDRESS_MASK => x"FFFF", diff --git a/hub_test/bd/design_1/design_1.bd b/hub_test/bd/design_1/design_1.bd index ae4388e..4cb1246 100644 --- a/hub_test/bd/design_1/design_1.bd +++ b/hub_test/bd/design_1/design_1.bd @@ -1,7 +1,7 @@ { "design": { "design_info": { - "boundary_crc": "0x6D8724B8D62394D", + "boundary_crc": "0x1DD12A2FE1BACBB7", "device": "xcku115-flvf1924-2-e", "name": "design_1", "rev_ctrl_bd_flag": "RevCtrlBdOff", @@ -26,7 +26,8 @@ "m02_couplers": {}, "m03_couplers": {}, "m04_couplers": {}, - "m05_couplers": {} + "m05_couplers": {}, + "m06_couplers": {} }, "microblaze_0_axi_intc": "", "microblaze_0_xlconcat": "", @@ -35,7 +36,8 @@ "axi_iic_0": "", "axi_gpio_mpod_los": "", "axi_timer_0": "", - "axi_gpio_mpod_txdis": "" + "axi_gpio_mpod_txdis": "", + "axi_gpio_resets": "" }, "interface_ports": { "I2C": { @@ -57,6 +59,10 @@ "MPOD_TXDIS_1": { "mode": "Master", "vlnv": "xilinx.com:interface:gpio_rtl:1.0" + }, + "RESETS": { + "mode": "Master", + "vlnv": "xilinx.com:interface:gpio_rtl:1.0" } }, "ports": { @@ -264,16 +270,22 @@ } }, "interface_nets": { + "microblaze_0_dlmb_bus": { + "interface_ports": [ + "dlmb_v10/LMB_Sl_0", + "dlmb_bram_if_cntlr/SLMB" + ] + }, "microblaze_0_ilmb": { "interface_ports": [ "ILMB", "ilmb_v10/LMB_M" ] }, - "microblaze_0_ilmb_bus": { + "microblaze_0_dlmb_cntlr": { "interface_ports": [ - "ilmb_v10/LMB_Sl_0", - "ilmb_bram_if_cntlr/SLMB" + "dlmb_bram_if_cntlr/BRAM_PORT", + "lmb_bram/BRAM_PORTA" ] }, "microblaze_0_ilmb_cntlr": { @@ -282,10 +294,10 @@ "lmb_bram/BRAM_PORTB" ] }, - "microblaze_0_dlmb_cntlr": { + "microblaze_0_ilmb_bus": { "interface_ports": [ - "dlmb_bram_if_cntlr/BRAM_PORT", - "lmb_bram/BRAM_PORTA" + "ilmb_v10/LMB_Sl_0", + "ilmb_bram_if_cntlr/SLMB" ] }, "microblaze_0_dlmb": { @@ -293,12 +305,6 @@ "DLMB", "dlmb_v10/LMB_M" ] - }, - "microblaze_0_dlmb_bus": { - "interface_ports": [ - "dlmb_v10/LMB_Sl_0", - "dlmb_bram_if_cntlr/SLMB" - ] } }, "nets": { @@ -327,7 +333,7 @@ "xci_name": "design_1_microblaze_0_axi_periph_0", "parameters": { "NUM_MI": { - "value": "6" + "value": "7" } }, "interface_ports": { @@ -358,6 +364,10 @@ "M05_AXI": { "mode": "Master", "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M06_AXI": { + "mode": "Master", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" } }, "ports": { @@ -485,6 +495,22 @@ "M05_ARESETN": { "type": "rst", "direction": "I" + }, + "M06_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M06_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M06_ARESETN" + } + } + }, + "M06_ARESETN": { + "type": "rst", + "direction": "I" } }, "components": { @@ -493,7 +519,7 @@ "xci_name": "design_1_xbar_0", "parameters": { "NUM_MI": { - "value": "6" + "value": "7" }, "NUM_SI": { "value": "1" @@ -512,7 +538,8 @@ "M02_AXI", "M03_AXI", "M04_AXI", - "M05_AXI" + "M05_AXI", + "M06_AXI" ] } } @@ -895,31 +922,91 @@ ] } } + }, + "m06_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m06_couplers_to_m06_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } } }, "interface_nets": { - "s00_couplers_to_xbar": { + "xbar_to_m05_couplers": { "interface_ports": [ - "s00_couplers/M_AXI", - "xbar/S00_AXI" + "xbar/M05_AXI", + "m05_couplers/S_AXI" ] }, - "xbar_to_m03_couplers": { + "m06_couplers_to_microblaze_0_axi_periph": { "interface_ports": [ - "xbar/M03_AXI", - "m03_couplers/S_AXI" + "M06_AXI", + "m06_couplers/M_AXI" ] }, - "m04_couplers_to_microblaze_0_axi_periph": { + "s00_couplers_to_xbar": { "interface_ports": [ - "M04_AXI", - "m04_couplers/M_AXI" + "s00_couplers/M_AXI", + "xbar/S00_AXI" ] }, - "microblaze_0_axi_periph_to_s00_couplers": { + "m00_couplers_to_microblaze_0_axi_periph": { "interface_ports": [ - "S00_AXI", - "s00_couplers/S_AXI" + "M00_AXI", + "m00_couplers/M_AXI" + ] + }, + "xbar_to_m06_couplers": { + "interface_ports": [ + "xbar/M06_AXI", + "m06_couplers/S_AXI" ] }, "xbar_to_m00_couplers": { @@ -928,22 +1015,22 @@ "m00_couplers/S_AXI" ] }, - "m05_couplers_to_microblaze_0_axi_periph": { + "m01_couplers_to_microblaze_0_axi_periph": { "interface_ports": [ - "M05_AXI", - "m05_couplers/M_AXI" + "M01_AXI", + "m01_couplers/M_AXI" ] }, - "xbar_to_m04_couplers": { + "xbar_to_m01_couplers": { "interface_ports": [ - "xbar/M04_AXI", - "m04_couplers/S_AXI" + "xbar/M01_AXI", + "m01_couplers/S_AXI" ] }, - "m03_couplers_to_microblaze_0_axi_periph": { + "m02_couplers_to_microblaze_0_axi_periph": { "interface_ports": [ - "M03_AXI", - "m03_couplers/M_AXI" + "M02_AXI", + "m02_couplers/M_AXI" ] }, "xbar_to_m02_couplers": { @@ -952,34 +1039,40 @@ "m02_couplers/S_AXI" ] }, - "xbar_to_m05_couplers": { + "m03_couplers_to_microblaze_0_axi_periph": { "interface_ports": [ - "xbar/M05_AXI", - "m05_couplers/S_AXI" + "M03_AXI", + "m03_couplers/M_AXI" ] }, - "m02_couplers_to_microblaze_0_axi_periph": { + "m05_couplers_to_microblaze_0_axi_periph": { "interface_ports": [ - "M02_AXI", - "m02_couplers/M_AXI" + "M05_AXI", + "m05_couplers/M_AXI" ] }, - "xbar_to_m01_couplers": { + "xbar_to_m03_couplers": { "interface_ports": [ - "xbar/M01_AXI", - "m01_couplers/S_AXI" + "xbar/M03_AXI", + "m03_couplers/S_AXI" ] }, - "m00_couplers_to_microblaze_0_axi_periph": { + "xbar_to_m04_couplers": { "interface_ports": [ - "M00_AXI", - "m00_couplers/M_AXI" + "xbar/M04_AXI", + "m04_couplers/S_AXI" ] }, - "m01_couplers_to_microblaze_0_axi_periph": { + "m04_couplers_to_microblaze_0_axi_periph": { "interface_ports": [ - "M01_AXI", - "m01_couplers/M_AXI" + "M04_AXI", + "m04_couplers/M_AXI" + ] + }, + "microblaze_0_axi_periph_to_s00_couplers": { + "interface_ports": [ + "S00_AXI", + "s00_couplers/S_AXI" ] } }, @@ -996,12 +1089,14 @@ "m03_couplers/M_ACLK", "m04_couplers/M_ACLK", "m05_couplers/M_ACLK", + "m06_couplers/M_ACLK", "m00_couplers/S_ACLK", "m01_couplers/S_ACLK", "m02_couplers/S_ACLK", "m03_couplers/S_ACLK", "m04_couplers/S_ACLK", - "m05_couplers/S_ACLK" + "m05_couplers/S_ACLK", + "m06_couplers/S_ACLK" ] }, "microblaze_0_axi_periph_ARESETN_net": { @@ -1016,12 +1111,14 @@ "m03_couplers/M_ARESETN", "m04_couplers/M_ARESETN", "m05_couplers/M_ARESETN", + "m06_couplers/M_ARESETN", "m00_couplers/S_ARESETN", "m01_couplers/S_ARESETN", "m02_couplers/S_ARESETN", "m03_couplers/S_ARESETN", "m04_couplers/S_ARESETN", - "m05_couplers/S_ARESETN" + "m05_couplers/S_ARESETN", + "m06_couplers/S_ARESETN" ] } } @@ -1118,37 +1215,49 @@ "value": "1" } } + }, + "axi_gpio_resets": { + "vlnv": "xilinx.com:ip:axi_gpio:2.0", + "xci_name": "design_1_axi_gpio_resets_0", + "parameters": { + "C_ALL_OUTPUTS": { + "value": "1" + }, + "C_GPIO_WIDTH": { + "value": "8" + } + } } }, "interface_nets": { - "microblaze_0_axi_periph_M02_AXI": { + "microblaze_0_axi_periph_M05_AXI": { "interface_ports": [ - "microblaze_0_axi_periph/M02_AXI", - "axi_iic_0/S_AXI" + "microblaze_0_axi_periph/M05_AXI", + "axi_gpio_mpod_txdis/S_AXI" ] }, - "microblaze_0_ilmb_1": { + "microblaze_0_dlmb_1": { "interface_ports": [ - "microblaze_0/ILMB", - "microblaze_0_local_memory/ILMB" + "microblaze_0/DLMB", + "microblaze_0_local_memory/DLMB" ] }, - "microblaze_0_debug": { + "microblaze_0_ilmb_1": { "interface_ports": [ - "mdm_1/MBDEBUG_0", - "microblaze_0/DEBUG" + "microblaze_0/ILMB", + "microblaze_0_local_memory/ILMB" ] }, - "microblaze_0_dlmb_1": { + "axi_gpio_resets_GPIO": { "interface_ports": [ - "microblaze_0/DLMB", - "microblaze_0_local_memory/DLMB" + "RESETS", + "axi_gpio_resets/GPIO" ] }, - "axi_gpio_mpod_los_GPIO": { + "microblaze_0_axi_periph_M02_AXI": { "interface_ports": [ - "MPOD_LOS_0", - "axi_gpio_mpod_los/GPIO" + "microblaze_0_axi_periph/M02_AXI", + "axi_iic_0/S_AXI" ] }, "axi_iic_0_IIC": { @@ -1163,16 +1272,22 @@ "axi_gpio_mpod_txdis/GPIO" ] }, - "axi_gpio_mpod_txdis_GPIO2": { + "microblaze_0_debug": { "interface_ports": [ - "MPOD_TXDIS_1", - "axi_gpio_mpod_txdis/GPIO2" + "mdm_1/MBDEBUG_0", + "microblaze_0/DEBUG" ] }, - "microblaze_0_axi_periph_M05_AXI": { + "microblaze_0_interrupt": { "interface_ports": [ - "microblaze_0_axi_periph/M05_AXI", - "axi_gpio_mpod_txdis/S_AXI" + "microblaze_0_axi_intc/interrupt", + "microblaze_0/INTERRUPT" + ] + }, + "microblaze_0_intc_axi": { + "interface_ports": [ + "microblaze_0_axi_periph/M00_AXI", + "microblaze_0_axi_intc/s_axi" ] }, "microblaze_0_axi_periph_M03_AXI": { @@ -1181,10 +1296,10 @@ "axi_gpio_mpod_los/S_AXI" ] }, - "microblaze_0_mdm_axi": { + "microblaze_0_axi_periph_M04_AXI": { "interface_ports": [ - "microblaze_0_axi_periph/M01_AXI", - "mdm_1/S_AXI" + "microblaze_0_axi_periph/M04_AXI", + "axi_timer_0/S_AXI" ] }, "axi_gpio_mpod_los_GPIO2": { @@ -1193,28 +1308,34 @@ "axi_gpio_mpod_los/GPIO2" ] }, + "axi_gpio_mpod_txdis_GPIO2": { + "interface_ports": [ + "MPOD_TXDIS_1", + "axi_gpio_mpod_txdis/GPIO2" + ] + }, "microblaze_0_axi_dp": { "interface_ports": [ "microblaze_0_axi_periph/S00_AXI", "microblaze_0/M_AXI_DP" ] }, - "microblaze_0_axi_periph_M04_AXI": { + "microblaze_0_mdm_axi": { "interface_ports": [ - "microblaze_0_axi_periph/M04_AXI", - "axi_timer_0/S_AXI" + "microblaze_0_axi_periph/M01_AXI", + "mdm_1/S_AXI" ] }, - "microblaze_0_intc_axi": { + "axi_gpio_mpod_los_GPIO": { "interface_ports": [ - "microblaze_0_axi_periph/M00_AXI", - "microblaze_0_axi_intc/s_axi" + "MPOD_LOS_0", + "axi_gpio_mpod_los/GPIO" ] }, - "microblaze_0_interrupt": { + "microblaze_0_axi_periph_M06_AXI": { "interface_ports": [ - "microblaze_0_axi_intc/interrupt", - "microblaze_0/INTERRUPT" + "microblaze_0_axi_periph/M06_AXI", + "axi_gpio_resets/S_AXI" ] } }, @@ -1245,7 +1366,9 @@ "axi_timer_0/s_axi_aclk", "microblaze_0_axi_periph/M04_ACLK", "axi_gpio_mpod_txdis/s_axi_aclk", - "microblaze_0_axi_periph/M05_ACLK" + "microblaze_0_axi_periph/M05_ACLK", + "axi_gpio_resets/s_axi_aclk", + "microblaze_0_axi_periph/M06_ACLK" ] }, "rst_Clk_100M_mb_reset": { @@ -1277,7 +1400,9 @@ "axi_timer_0/s_axi_aresetn", "microblaze_0_axi_periph/M04_ARESETN", "axi_gpio_mpod_txdis/s_axi_aresetn", - "microblaze_0_axi_periph/M05_ARESETN" + "microblaze_0_axi_periph/M05_ARESETN", + "axi_gpio_resets/s_axi_aresetn", + "microblaze_0_axi_periph/M06_ARESETN" ] }, "mdm_1_debug_sys_rst": { @@ -1328,6 +1453,11 @@ "offset": "0x40010000", "range": "64K" }, + "SEG_axi_gpio_resets_Reg": { + "address_block": "/axi_gpio_resets/S_AXI/Reg", + "offset": "0x40020000", + "range": "64K" + }, "SEG_axi_iic_0_Reg": { "address_block": "/axi_iic_0/S_AXI/Reg", "offset": "0x40800000", @@ -1362,7 +1492,7 @@ "SEG_ilmb_bram_if_cntlr_Mem": { "address_block": "/microblaze_0_local_memory/ilmb_bram_if_cntlr/SLMB/Mem", "offset": "0x00000000", - "range": "16K" + "range": "32K" } } } diff --git a/hub_test/constrs/hub_test.xdc b/hub_test/constrs/hub_test.xdc index b165f33..145d871 100644 --- a/hub_test/constrs/hub_test.xdc +++ b/hub_test/constrs/hub_test.xdc @@ -1,20 +1,48 @@ -set_property PACKAGE_PIN AK38 [get_ports MGTREFCLK_N] -set_property PACKAGE_PIN AK37 [get_ports MGTREFCLK_P] - -create_clock -period 8.000 -name MGTREFCLK_P [get_ports MGTREFCLK_P] - set_property PACKAGE_PIN AT18 [get_ports CLK_200_P] set_property IOSTANDARD LVDS [get_ports CLK_200_P] create_clock -period 5.000 -name CLK_200_P [get_ports CLK_200_P] -set_property PACKAGE_PIN K10 [get_ports {MPOD_RESET_N[3]}] -set_property PACKAGE_PIN K11 [get_ports {MPOD_RESET_N[2]}] -set_property PACKAGE_PIN G14 [get_ports {MPOD_RESET_N[1]}] -set_property PACKAGE_PIN H14 [get_ports {MPOD_RESET_N[0]}] -set_property IOSTANDARD LVTTL [get_ports {MPOD_RESET_N[3]}] -set_property IOSTANDARD LVTTL [get_ports {MPOD_RESET_N[2]}] -set_property IOSTANDARD LVTTL [get_ports {MPOD_RESET_N[1]}] -set_property IOSTANDARD LVTTL [get_ports {MPOD_RESET_N[0]}] +set_property PACKAGE_PIN AR21 [get_ports SI5345_IN0_P] +set_property IOSTANDARD LVDS [get_ports SI5345_IN0_P] +create_clock -period 10.000 -name SI5345_IN0_P [get_ports SI5345_IN0_P] + +set_property PACKAGE_PIN AY37 [get_ports SI5345_OUT7_P] +set_property IOSTANDARD LVDS [get_ports SI5345_OUT7_P] + +set_property PACKAGE_PIN K10 [get_ports MPOD_RX1_RESET_N] +set_property IOSTANDARD LVTTL [get_ports MPOD_RX1_RESET_N] +set_property PACKAGE_PIN K11 [get_ports MPOD_RX2_RESET_N] +set_property IOSTANDARD LVTTL [get_ports MPOD_RX2_RESET_N] +set_property PACKAGE_PIN G14 [get_ports MPOD_TX1_RESET_N] +set_property IOSTANDARD LVTTL [get_ports MPOD_TX1_RESET_N] +set_property PACKAGE_PIN H14 [get_ports MPOD_TX2_RESET_N] +set_property IOSTANDARD LVTTL [get_ports MPOD_TX2_RESET_N] + +set_property PACKAGE_PIN D35 [get_ports SI5345_RST_N] +set_property IOSTANDARD LVCMOS18 [get_ports SI5345_RST_N] + +set_property PACKAGE_PIN R18 [get_ports SI5345_I2C_SEL] +set_property IOSTANDARD LVCMOS18 [get_ports SI5345_I2C_SEL] + +set_property PACKAGE_PIN P16 [get_ports SI5345_LOL_N] +set_property IOSTANDARD LVCMOS18 [get_ports SI5345_LOL_N] + +set_property PACKAGE_PIN W11 [get_ports PCA9546A_DEVS_RESET_N] +set_property IOSTANDARD LVTTL [get_ports PCA9546A_DEVS_RESET_N] + +set_property PACKAGE_PIN W10 [get_ports PCA9546A_PCIE_RESET_N] +set_property IOSTANDARD LVTTL [get_ports PCA9546A_PCIE_RESET_N] + +set_property PACKAGE_PIN AR20 [get_ports PEX_I2C_SEL0] +set_property IOSTANDARD LVCMOS18 [get_ports PEX_I2C_SEL0] +set_property PACKAGE_PIN AP20 [get_ports PEX_I2C_SEL1] +set_property IOSTANDARD LVCMOS18 [get_ports PEX_I2C_SEL1] + +set_property PACKAGE_PIN B34 [get_ports UC_RESET_N] +set_property IOSTANDARD LVCMOS18 [get_ports UC_RESET_N] + +set_property PACKAGE_PIN AK37 [get_ports MGTREFCLK_P] +create_clock -period 10.000 -name MGTREFCLK_P [get_ports MGTREFCLK_P] set_property PACKAGE_PIN V13 [get_ports SCL] set_property IOSTANDARD LVTTL [get_ports SCL] @@ -48,3 +76,5 @@ set_property LOC GTHE3_CHANNEL_X0Y16 [get_cells -hierarchical -filter {NAME =~ * set_property LOC GTHE3_CHANNEL_X0Y17 [get_cells -hierarchical -filter {NAME =~ *THE_MEDIA_4_PCSD*gen_channel_container[2].*gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST}] set_property LOC GTHE3_CHANNEL_X0Y18 [get_cells -hierarchical -filter {NAME =~ *THE_MEDIA_4_PCSD*gen_channel_container[2].*gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST}] set_property LOC GTHE3_CHANNEL_X0Y19 [get_cells -hierarchical -filter {NAME =~ *THE_MEDIA_4_PCSD*gen_channel_container[2].*gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST}] + +set_false_path -from [get_pins {design_1_wrapper_i/design_1_i/axi_gpio_mpod_los/U0/gpio_core_1/Dual.gpio_Data_Out_reg[*]/C}] -to [get_pins {THE_MEDIA_4_PCS?/gen_control[*].gen_used_control.THE_MED_CONTROL/THE_RX_FSM/sync_sfp_sigs/gen_others.gen_flipflops[*].sync_q_reg[*]_srl2/D}] diff --git a/hub_test/hub_test.xpr b/hub_test/hub_test.xpr index a219765..e3fabfb 100644 --- a/hub_test/hub_test.xpr +++ b/hub_test/hub_test.xpr @@ -130,6 +130,13 @@ + + + + + + + @@ -529,7 +536,7 @@ - + diff --git a/hub_test/ip/clk_wiz_0/clk_wiz_0.xci b/hub_test/ip/clk_wiz_0/clk_wiz_0.xci index 23a21b9..788e7fa 100644 --- a/hub_test/ip/clk_wiz_0/clk_wiz_0.xci +++ b/hub_test/ip/clk_wiz_0/clk_wiz_0.xci @@ -92,7 +92,7 @@ clkfb_out clkfb_out_p clkfb_stopped - 50.0 + 100.0 100.0 0000 0000 @@ -225,7 +225,7 @@ 0000 0 Input Clock Freq (MHz) Input Jitter (UI) - __primary_________200.000____________0.010 + __primary_________100.000____________0.010 no_secondary_input_clock input_clk_stopped 0 @@ -244,11 +244,11 @@ false false OPTIMIZED - 5.000 + 10.000 0.000 FALSE - 5.000 - 10.0 + 10.000 + 10.000 10.000 0.500 0.000 @@ -290,8 +290,8 @@ 2 Output Output Phase Duty Cycle Pk-to-Pk Phase Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) - clk_out1__100.00000______0.000______50.0______112.316_____89.971 - clk_out2__200.00000______0.000______50.0_______98.146_____89.971 + clk_out1__100.00000______0.000______50.0______130.958_____98.575 + clk_out2__200.00000______0.000______50.0______114.829_____98.575 no_CLK_OUT3_output no_CLK_OUT4_output no_CLK_OUT5_output @@ -341,7 +341,7 @@ clk_in1 MMCM AUTO - 200.000 + 100.000 0.010 10.000 Differential_clock_capable_pin @@ -407,23 +407,23 @@ clkfb_out clkfb_out_p clkfb_stopped - 50.0 + 100.0 0.010 100.0 0.010 Buffer - 112.316 + 130.958 false - 89.971 + 98.575 50.000 100.000 0.000 1 true Buffer - 98.146 + 114.829 false - 89.971 + 98.575 50.000 200.000 0.000 @@ -523,11 +523,11 @@ No_Jitter locked OPTIMIZED - 5.000 + 10.000 0.000 false - 5.000 - 10.0 + 10.000 + 10.000 10.000 0.500 0.000 @@ -602,7 +602,7 @@ clk_in1 MMCM mmcm_adv - 200.000 + 100.000 0.010 10.000 Differential_clock_capable_pin diff --git a/hub_test/ip/clk_wiz_0/clk_wiz_0.xml b/hub_test/ip/clk_wiz_0/clk_wiz_0.xml index 33f5aab..4eae428 100644 --- a/hub_test/ip/clk_wiz_0/clk_wiz_0.xml +++ b/hub_test/ip/clk_wiz_0/clk_wiz_0.xml @@ -1185,7 +1185,7 @@ outputProductCRC - 9:c1f87391 + 9:40f10733 @@ -2241,7 +2241,7 @@ C_PRIM_IN_FREQ - 200.000 + 100.000 C_PRIM_IN_TIMEPERIOD @@ -2349,7 +2349,7 @@ C_INCLK_SUM_ROW1 - __primary_________200.000____________0.010 + __primary_________100.000____________0.010 C_INCLK_SUM_ROW2 @@ -2366,11 +2366,11 @@ C_OUTCLK_SUM_ROW1 - clk_out1__100.00000______0.000______50.0______112.316_____89.971 + clk_out1__100.00000______0.000______50.0______130.958_____98.575 C_OUTCLK_SUM_ROW2 - clk_out2__200.00000______0.000______50.0_______98.146_____89.971 + clk_out2__200.00000______0.000______50.0______114.829_____98.575 C_OUTCLK_SUM_ROW3 @@ -2606,15 +2606,15 @@ C_MMCM_CLKFBOUT_MULT_F - 5.000 + 10.000 C_MMCM_CLKIN1_PERIOD - 5.000 + 10.000 C_MMCM_CLKIN2_PERIOD - 10.0 + 10.000 C_MMCM_CLKOUT4_CASCADE @@ -3022,7 +3022,7 @@ C_CLKIN1_JITTER_PS - 50.0 + 100.0 C_CLKIN2_JITTER_PS @@ -3592,7 +3592,7 @@ PRIM_IN_FREQ - 200.000 + 100.000 PRIM_IN_TIMEPERIOD @@ -3656,7 +3656,7 @@ CLKIN1_JITTER_PS - 50.0 + 100.0 CLKIN2_JITTER_PS @@ -4088,7 +4088,7 @@ MMCM_CLKFBOUT_MULT_F - 5.000 + 10.000 MMCM_CLKFBOUT_PHASE @@ -4100,11 +4100,11 @@ MMCM_CLKIN1_PERIOD - 5.000 + 10.000 MMCM_CLKIN2_PERIOD - 10.0 + 10.000 MMCM_CLKOUT4_CASCADE @@ -4447,22 +4447,22 @@ CLKOUT1_JITTER Clkout1 Jitter - 112.316 + 130.958 CLKOUT1_PHASE_ERROR Clkout1 Phase - 89.971 + 98.575 CLKOUT2_JITTER Clkout2 Jitter - 98.146 + 114.829 CLKOUT2_PHASE_ERROR Clkout2 Phase - 89.971 + 98.575 CLKOUT3_JITTER diff --git a/hub_test/ip/clk_wiz_1/clk_wiz_1.xci b/hub_test/ip/clk_wiz_1/clk_wiz_1.xci new file mode 100644 index 0000000..55b9afc --- /dev/null +++ b/hub_test/ip/clk_wiz_1/clk_wiz_1.xci @@ -0,0 +1,710 @@ + + + xilinx.com + xci + unknown + 1.0 + + + clk_wiz_1 + + + false + 100000000 + false + 100000000 + false + 100000000 + false + 100000000 + + + + 100000000 + 0 + 0 + 0.000 + 1 + LEVEL_HIGH + + + + 100000000 + 0 + 0 + 0.000 + 0 + 0 + + 100000000 + 0 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + MMCM + cddcdone + cddcreq + 0000 + 0000 + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 50.0 + 100.0 + 0000 + 0000 + 100.00000 + 0000 + 0000 + 100.000 + BUFG + 50.0 + false + 100.00000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + VCO + clk_in_sel + clk_out1 + clk_out2 + clk_out3 + clk_out4 + clk_out5 + clk_out6 + clk_out7 + CLK_VALID + NA + daddr + dclk + den + din + 0000 + 1 + 1.0 + 1.0 + 1.0 + 1.0 + 1.0 + 1.0 + dout + drdy + dwe + 93.000 + 1.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + FDBK_AUTO + 0000 + 0000 + 0 + Input Clock Freq (MHz) Input Jitter (UI) + __primary_________200.000____________0.010 + no_secondary_input_clock + input_clk_stopped + 0 + Units_MHz + No_Jitter + locked + 0000 + 0000 + 0000 + false + false + false + false + false + false + false + false + OPTIMIZED + 5.000 + 0.000 + FALSE + 5.000 + 10.0 + 10.000 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + AUTO + 1 + None + 0.010 + 0.010 + FALSE + 64.000 + 2.000 + 1 + Output Output Phase Duty Cycle Pk-to-Pk Phase + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + clk_out1__100.00000______0.000______50.0______112.316_____89.971 + no_CLK_OUT2_output + no_CLK_OUT3_output + no_CLK_OUT4_output + no_CLK_OUT5_output + no_CLK_OUT6_output + no_CLK_OUT7_output + 0 + 0 + 128.000 + 1.000 + WAVEFORM + UNKNOWN + false + false + false + false + false + OPTIMIZED + 1 + 0.000 + 1.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + No notes + 0.010 + power_down + 0000 + 1 + clk_in1 + MMCM + AUTO + 200.000 + 0.010 + 10.000 + Differential_clock_capable_pin + psclk + psdone + psen + psincdec + 100.0 + 0 + reset + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 4000 + 0.004 + STATUS + 11 + 32 + 100.0 + 100.0 + 100.0 + 100.0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 1440.000 + 600.000 + clk_wiz_1 + MMCM + false + empty + cddcdone + cddcreq + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 50.0 + 0.010 + 100.0 + 0.010 + Buffer + 112.316 + false + 89.971 + 50.000 + 100.000 + 0.000 + 1 + true + Buffer + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + Buffer + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + Buffer + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + Buffer + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + Buffer + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + Buffer + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + 600.000 + Custom + Custom + clk_in_sel + clk_out1 + false + clk_out2 + false + clk_out3 + false + clk_out4 + false + clk_out5 + false + clk_out6 + false + clk_out7 + false + CLK_VALID + auto + clk_wiz_1 + daddr + dclk + den + Custom + Custom + din + dout + drdy + dwe + false + false + false + false + false + false + false + false + false + FDBK_AUTO + input_clk_stopped + frequency + Enable_AXI + Units_MHz + Units_UI + UI + No_Jitter + locked + OPTIMIZED + 5.000 + 0.000 + false + 5.000 + 10.0 + 10.000 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + AUTO + 1 + None + 0.010 + 0.010 + false + 1 + false + false + WAVEFORM + false + UNKNOWN + OPTIMIZED + 4 + 0.000 + 10.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + None + 0.010 + power_down + 1 + clk_in1 + MMCM + mmcm_adv + 200.000 + 0.010 + 10.000 + Differential_clock_capable_pin + psclk + psdone + psen + psincdec + 100.0 + REL_PRIMARY + Custom + reset + ACTIVE_HIGH + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 250 + 0.004 + STATUS + empty + 100.0 + 100.0 + 100.0 + 100.0 + false + false + false + false + false + false + false + true + false + false + true + false + false + false + true + false + true + false + false + false + kintexu + + + xcku115 + flvf1924 + VHDL + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 5 + TRUE + . + + . + 2020.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/hub_test/ip/clk_wiz_1/clk_wiz_1.xml b/hub_test/ip/clk_wiz_1/clk_wiz_1.xml new file mode 100644 index 0000000..535ff64 --- /dev/null +++ b/hub_test/ip/clk_wiz_1/clk_wiz_1.xml @@ -0,0 +1,4497 @@ + + + xilinx.com + customized_ip + clk_wiz_1 + 1.0 + + + s_axi_lite + S_AXI_LITE + + + + + + + ARADDR + + + s_axi_araddr + + + + + ARREADY + + + s_axi_arready + + + + + ARVALID + + + s_axi_arvalid + + + + + AWADDR + + + s_axi_awaddr + + + + + AWREADY + + + s_axi_awready + + + + + AWVALID + + + s_axi_awvalid + + + + + BREADY + + + s_axi_bready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + RDATA + + + s_axi_rdata + + + + + RREADY + + + s_axi_rready + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + WDATA + + + s_axi_wdata + + + + + WREADY + + + s_axi_wready + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + + DATA_WIDTH + 1 + + + none + + + + + PROTOCOL + AXI4LITE + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + ID_WIDTH + 0 + + + none + + + + + ADDR_WIDTH + 1 + + + none + + + + + AWUSER_WIDTH + 0 + + + none + + + + + ARUSER_WIDTH + 0 + + + none + + + + + WUSER_WIDTH + 0 + + + none + + + + + RUSER_WIDTH + 0 + + + none + + + + + BUSER_WIDTH + 0 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + HAS_BURST + 0 + + + none + + + + + HAS_LOCK + 0 + + + none + + + + + HAS_PROT + 0 + + + none + + + + + HAS_CACHE + 0 + + + none + + + + + HAS_QOS + 0 + + + none + + + + + HAS_REGION + 0 + + + none + + + + + HAS_WSTRB + 0 + + + none + + + + + HAS_BRESP + 0 + + + none + + + + + HAS_RRESP + 0 + + + none + + + + + SUPPORTS_NARROW_BURST + 0 + + + none + + + + + NUM_READ_OUTSTANDING + 1 + + + none + + + + + NUM_WRITE_OUTSTANDING + 1 + + + none + + + + + MAX_BURST_LENGTH + 1 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + NUM_READ_THREADS + 1 + + + none + + + + + NUM_WRITE_THREADS + 1 + + + none + + + + + RUSER_BITS_PER_BYTE + 0 + + + none + + + + + WUSER_BITS_PER_BYTE + 0 + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + s_axi_aclk + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi_lite + + + ASSOCIATED_RESET + s_axi_aresetn + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + ref_clk + ref_clk + + + + + + + CLK + + + ref_clk + + + + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + ASSOCIATED_RESET + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + s_axi_resetn + S_AXI_RESETN + + + + + + + RST + + + s_axi_aresetn + + + + + + ASSOCIATED_RESET + aresetn + + + POLARITY + ACTIVE_LOW + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + intr + Intr + + + + + + + INTERRUPT + + + ip2intc_irpt + + + + + + SENSITIVITY + LEVEL_HIGH + + + none + + + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + CLK_IN1_D + CLK_IN1_D + Differential Clock input + + + + + + + CLK_N + + + clk_in1_n + + + + + CLK_P + + + clk_in1_p + + + + + + BOARD.ASSOCIATED_PARAM + CLK_IN1_BOARD_INTERFACE + + + + required + + + + + + CAN_DEBUG + false + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + + + + true + + + + + + CLK_IN2_D + CLK_IN2_D + Differential Clock input + + + + + + + CLK_N + + + clk_in2_n + + + + + CLK_P + + + clk_in2_p + + + + + + BOARD.ASSOCIATED_PARAM + CLK_IN2_BOARD_INTERFACE + + + + required + + + + + + CAN_DEBUG + false + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + + + + false + + + + + + CLKFB_IN_D + CLKFB_IN_D + Differential Feedback Clock input + + + + + + + CLK_N + + + clkfb_in_n + + + + + CLK_P + + + clkfb_in_p + + + + + + CAN_DEBUG + false + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + + + + false + + + + + + CLKFB_OUT_D + CLKFB_OUT_D + Differential Feeback Clock Output + + + + + + + CLK_N + + + clkfb_out_n + + + + + CLK_P + + + clkfb_out_p + + + + + + CAN_DEBUG + false + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + + + + false + + + + + + reset + reset + + + + + + + RST + + + reset + + + + + + POLARITY + ACTIVE_HIGH + + + BOARD.ASSOCIATED_PARAM + RESET_BOARD_INTERFACE + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + true + + + + + + resetn + resetn + + + + + + + RST + + + resetn + + + + + + POLARITY + ACTIVE_LOW + + + BOARD.ASSOCIATED_PARAM + RESET_BOARD_INTERFACE + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + clock_CLK_OUT1 + + + + + + + CLK_OUT1 + + + clk_out1 + + + + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + ASSOCIATED_RESET + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + xilinx_elaborateports + Elaborate Ports + :vivado.xilinx.com:elaborate.ports + + + outputProductCRC + 9:10d1178b + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_elaborateports + + + + 0 + + + + + + false + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_elaborateports + + + + 0 + + + + + + false + + + + + + s_axi_awaddr + + in + + 10 + 0 + + + + std_logic_vector + xilinx_elaborateports + + + + 0 + + + + + + false + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_elaborateports + + + + 0 + + + + + + false + + + + + + s_axi_awready + + out + + + std_logic + xilinx_elaborateports + + + + + + + false + + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_elaborateports + + + + 0 + + + + + + false + + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_elaborateports + + + + 0 + + + + + + false + + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_elaborateports + + + + 0 + + + + + + false + + + + + + s_axi_wready + + out + + + std_logic + xilinx_elaborateports + + + + + + + false + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_elaborateports + + + + + + + false + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_elaborateports + + + + + + + false + + + + + + s_axi_bready + + in + + + std_logic + xilinx_elaborateports + + + + 0 + + + + + + false + + + + + + s_axi_araddr + + in + + 10 + 0 + + + + std_logic_vector + xilinx_elaborateports + + + + 0 + + + + + + false + + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_elaborateports + + + + 0 + + + + + + false + + + + + + s_axi_arready + + out + + + std_logic + xilinx_elaborateports + + + + + + + false + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_elaborateports + + + + + + + false + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_elaborateports + + + + + + + false + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_elaborateports + + + + + + + false + + + + + + s_axi_rready + + in + + + std_logic + xilinx_elaborateports + + + + 0 + + + + + + false + + + + + + clk_in1_p + + in + + + std_logic + xilinx_elaborateports + + + + 0 + + + + + + true + + + + + + clk_in1_n + + in + + + std_logic + xilinx_elaborateports + + + + 0 + + + + + + true + + + + + + clk_in2_p + + in + + + std_logic + xilinx_elaborateports + + + + 0 + + + + + + false + + + + + + clk_in2_n + + in + + + std_logic + xilinx_elaborateports + + + + 0 + + + + + + false + + + + + + clkfb_in_p + + in + + + std_logic + xilinx_elaborateports + + + + 0 + + + + + + false + + + + + + clkfb_in_n + + in + + + std_logic + xilinx_elaborateports + + + + 0 + + + + + + false + + + + + + clkfb_out_p + + out + + + std_logic + xilinx_elaborateports + + + + + + + false + + + + + + clkfb_out_n + + out + + + std_logic + xilinx_elaborateports + + + + + + + false + + + + + + reset + + in + + + std_logic + xilinx_elaborateports + + + + 0 + + + + + + true + + + + + + resetn + + in + + + std_logic + xilinx_elaborateports + + + + 0 + + + + + + false + + + + + + ref_clk + + in + + + std_logic + xilinx_elaborateports + + + + 0 + + + + + + false + + + + + + clk_stop + + out + + 3 + 0 + + + + std_logic_vector + xilinx_elaborateports + + + + 0 + + + + + + false + + + + + + clk_glitch + + out + + 3 + 0 + + + + std_logic_vector + xilinx_elaborateports + + + + 0 + + + + + + false + + + + + + interrupt + + out + + + std_logic + xilinx_elaborateports + + + + 0 + + + + + + false + + + + + + clk_oor + + out + + 3 + 0 + + + + std_logic_vector + xilinx_elaborateports + + + + 0 + + + + + + false + + + + + + user_clk0 + + in + + + std_logic + xilinx_elaborateports + + + + 0 + + + + + + false + + + + + + user_clk1 + + in + + + std_logic + xilinx_elaborateports + + + + 0 + + + + + + false + + + + + + user_clk2 + + in + + + std_logic + xilinx_elaborateports + + + + 0 + + + + + + false + + + + + + user_clk3 + + in + + + std_logic + xilinx_elaborateports + + + + 0 + + + + + + false + + + + + + clk_out1 + + out + + + std_logic + xilinx_elaborateports + + + + + + locked + + out + + + std_logic + xilinx_elaborateports + + + + + + + + C_CLKOUT2_USED + 0 + + + C_USER_CLK_FREQ0 + 100.0 + + + C_AUTO_PRIMITIVE + MMCM + + + C_USER_CLK_FREQ1 + 100.0 + + + C_USER_CLK_FREQ2 + 100.0 + + + C_USER_CLK_FREQ3 + 100.0 + + + C_ENABLE_CLOCK_MONITOR + 0 + + + C_ENABLE_USER_CLOCK0 + 0 + + + C_ENABLE_USER_CLOCK1 + 0 + + + C_ENABLE_USER_CLOCK2 + 0 + + + C_ENABLE_USER_CLOCK3 + 0 + + + C_Enable_PLL0 + 0 + + + C_Enable_PLL1 + 0 + + + C_REF_CLK_FREQ + 100.0 + + + C_PRECISION + 1 + + + C_CLKOUT3_USED + 0 + + + C_CLKOUT4_USED + 0 + + + C_CLKOUT5_USED + 0 + + + C_CLKOUT6_USED + 0 + + + C_CLKOUT7_USED + 0 + + + C_USE_CLKOUT1_BAR + 0 + + + C_USE_CLKOUT2_BAR + 0 + + + C_USE_CLKOUT3_BAR + 0 + + + C_USE_CLKOUT4_BAR + 0 + + + c_component_name + clk_wiz_1 + + + C_PLATFORM + UNKNOWN + + + C_USE_FREQ_SYNTH + 1 + + + C_USE_PHASE_ALIGNMENT + 1 + + + C_PRIM_IN_JITTER + 0.010 + + + C_SECONDARY_IN_JITTER + 0.010 + + + C_JITTER_SEL + No_Jitter + + + C_USE_MIN_POWER + 0 + + + C_USE_MIN_O_JITTER + 0 + + + C_USE_MAX_I_JITTER + 0 + + + C_USE_DYN_PHASE_SHIFT + 0 + + + C_USE_INCLK_SWITCHOVER + 0 + + + C_USE_DYN_RECONFIG + 0 + + + C_USE_SPREAD_SPECTRUM + 0 + + + C_USE_FAST_SIMULATION + 0 + + + C_PRIMTYPE_SEL + AUTO + + + C_USE_CLK_VALID + 0 + + + C_PRIM_IN_FREQ + 200.000 + + + C_PRIM_IN_TIMEPERIOD + 10.000 + + + C_IN_FREQ_UNITS + Units_MHz + + + C_SECONDARY_IN_FREQ + 100.000 + + + C_SECONDARY_IN_TIMEPERIOD + 10.000 + + + C_FEEDBACK_SOURCE + FDBK_AUTO + + + C_PRIM_SOURCE + Differential_clock_capable_pin + + + C_PHASESHIFT_MODE + WAVEFORM + + + C_SECONDARY_SOURCE + Single_ended_clock_capable_pin + + + C_CLKFB_IN_SIGNALING + SINGLE + + + C_USE_RESET + 1 + + + C_RESET_LOW + 0 + + + C_USE_LOCKED + 1 + + + C_USE_INCLK_STOPPED + 0 + + + C_USE_CLKFB_STOPPED + 0 + + + C_USE_POWER_DOWN + 0 + + + C_USE_STATUS + 0 + + + C_USE_FREEZE + 0 + + + C_NUM_OUT_CLKS + 1 + + + C_CLKOUT1_DRIVES + BUFG + + + C_CLKOUT2_DRIVES + BUFG + + + C_CLKOUT3_DRIVES + BUFG + + + C_CLKOUT4_DRIVES + BUFG + + + C_CLKOUT5_DRIVES + BUFG + + + C_CLKOUT6_DRIVES + BUFG + + + C_CLKOUT7_DRIVES + BUFG + + + C_INCLK_SUM_ROW0 + Input Clock Freq (MHz) Input Jitter (UI) + + + C_INCLK_SUM_ROW1 + __primary_________200.000____________0.010 + + + C_INCLK_SUM_ROW2 + no_secondary_input_clock + + + C_OUTCLK_SUM_ROW0A + C Outclk Sum Row0a + Output Output Phase Duty Cycle Pk-to-Pk Phase + + + C_OUTCLK_SUM_ROW0B + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + + + C_OUTCLK_SUM_ROW1 + clk_out1__100.00000______0.000______50.0______112.316_____89.971 + + + C_OUTCLK_SUM_ROW2 + no_CLK_OUT2_output + + + C_OUTCLK_SUM_ROW3 + no_CLK_OUT3_output + + + C_OUTCLK_SUM_ROW4 + no_CLK_OUT4_output + + + C_OUTCLK_SUM_ROW5 + no_CLK_OUT5_output + + + C_OUTCLK_SUM_ROW6 + no_CLK_OUT6_output + + + C_OUTCLK_SUM_ROW7 + no_CLK_OUT7_output + + + C_CLKOUT1_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT2_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT3_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT4_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT5_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT6_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT7_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT1_REQUESTED_PHASE + 0.000 + + + C_CLKOUT2_REQUESTED_PHASE + 0.000 + + + C_CLKOUT3_REQUESTED_PHASE + 0.000 + + + C_CLKOUT4_REQUESTED_PHASE + 0.000 + + + C_CLKOUT5_REQUESTED_PHASE + 0.000 + + + C_CLKOUT6_REQUESTED_PHASE + 0.000 + + + C_CLKOUT7_REQUESTED_PHASE + 0.000 + + + C_CLKOUT1_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT2_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT3_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT4_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT5_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT6_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT7_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT1_OUT_FREQ + 100.00000 + + + C_CLKOUT2_OUT_FREQ + 100.000 + + + C_CLKOUT3_OUT_FREQ + 100.000 + + + C_CLKOUT4_OUT_FREQ + 100.000 + + + C_CLKOUT5_OUT_FREQ + 100.000 + + + C_CLKOUT6_OUT_FREQ + 100.000 + + + C_CLKOUT7_OUT_FREQ + 100.000 + + + C_CLKOUT1_PHASE + 0.000 + + + C_CLKOUT2_PHASE + 0.000 + + + C_CLKOUT3_PHASE + 0.000 + + + C_CLKOUT4_PHASE + 0.000 + + + C_CLKOUT5_PHASE + 0.000 + + + C_CLKOUT6_PHASE + 0.000 + + + C_CLKOUT7_PHASE + 0.000 + + + C_CLKOUT1_DUTY_CYCLE + 50.0 + + + C_CLKOUT2_DUTY_CYCLE + 50.000 + + + C_CLKOUT3_DUTY_CYCLE + 50.000 + + + C_CLKOUT4_DUTY_CYCLE + 50.000 + + + C_CLKOUT5_DUTY_CYCLE + 50.000 + + + C_CLKOUT6_DUTY_CYCLE + 50.000 + + + C_CLKOUT7_DUTY_CYCLE + 50.000 + + + C_USE_SAFE_CLOCK_STARTUP + 0 + + + C_USE_CLOCK_SEQUENCING + 0 + + + C_CLKOUT1_SEQUENCE_NUMBER + 1 + + + C_CLKOUT2_SEQUENCE_NUMBER + 1 + + + C_CLKOUT3_SEQUENCE_NUMBER + 1 + + + C_CLKOUT4_SEQUENCE_NUMBER + 1 + + + C_CLKOUT5_SEQUENCE_NUMBER + 1 + + + C_CLKOUT6_SEQUENCE_NUMBER + 1 + + + C_CLKOUT7_SEQUENCE_NUMBER + 1 + + + C_MMCM_NOTES + None + + + C_MMCM_BANDWIDTH + OPTIMIZED + + + C_MMCM_CLKFBOUT_MULT_F + 5.000 + + + C_MMCM_CLKIN1_PERIOD + 5.000 + + + C_MMCM_CLKIN2_PERIOD + 10.0 + + + C_MMCM_CLKOUT4_CASCADE + FALSE + + + C_MMCM_CLOCK_HOLD + FALSE + + + C_MMCM_COMPENSATION + AUTO + + + C_MMCM_DIVCLK_DIVIDE + 1 + + + C_MMCM_REF_JITTER1 + 0.010 + + + C_MMCM_REF_JITTER2 + 0.010 + + + C_MMCM_STARTUP_WAIT + FALSE + + + C_MMCM_CLKOUT0_DIVIDE_F + 10.000 + + + C_MMCM_CLKOUT1_DIVIDE + 1 + + + C_MMCM_CLKOUT2_DIVIDE + 1 + + + C_MMCM_CLKOUT3_DIVIDE + 1 + + + C_MMCM_CLKOUT4_DIVIDE + 1 + + + C_MMCM_CLKOUT5_DIVIDE + 1 + + + C_MMCM_CLKOUT6_DIVIDE + 1 + + + C_MMCM_CLKOUT0_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT1_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT2_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT3_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT4_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT5_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT6_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKFBOUT_PHASE + 0.000 + + + C_MMCM_CLKOUT0_PHASE + 0.000 + + + C_MMCM_CLKOUT1_PHASE + 0.000 + + + C_MMCM_CLKOUT2_PHASE + 0.000 + + + C_MMCM_CLKOUT3_PHASE + 0.000 + + + C_MMCM_CLKOUT4_PHASE + 0.000 + + + C_MMCM_CLKOUT5_PHASE + 0.000 + + + C_MMCM_CLKOUT6_PHASE + 0.000 + + + C_MMCM_CLKFBOUT_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT0_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT1_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT2_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT3_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT4_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT5_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT6_USE_FINE_PS + FALSE + + + C_PLL_NOTES + No notes + + + C_PLL_BANDWIDTH + OPTIMIZED + + + C_PLL_CLK_FEEDBACK + CLKFBOUT + + + C_PLL_CLKFBOUT_MULT + 1 + + + C_PLL_CLKIN_PERIOD + 1.000 + + + C_PLL_COMPENSATION + SYSTEM_SYNCHRONOUS + + + C_PLL_DIVCLK_DIVIDE + 1 + + + C_PLL_REF_JITTER + 0.010 + + + C_PLL_CLKOUT0_DIVIDE + 1 + + + C_PLL_CLKOUT1_DIVIDE + 1 + + + C_PLL_CLKOUT2_DIVIDE + 1 + + + C_PLL_CLKOUT3_DIVIDE + 1 + + + C_PLL_CLKOUT4_DIVIDE + 1 + + + C_PLL_CLKOUT5_DIVIDE + 1 + + + C_PLL_CLKOUT0_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT1_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT2_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT3_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT4_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT5_DUTY_CYCLE + 0.500 + + + C_PLL_CLKFBOUT_PHASE + 0.000 + + + C_PLL_CLKOUT0_PHASE + 0.000 + + + C_PLL_CLKOUT1_PHASE + 0.000 + + + C_PLL_CLKOUT2_PHASE + 0.000 + + + C_PLL_CLKOUT3_PHASE + 0.000 + + + C_PLL_CLKOUT4_PHASE + 0.000 + + + C_PLL_CLKOUT5_PHASE + 0.000 + + + C_CLOCK_MGR_TYPE + NA + + + C_OVERRIDE_MMCM + 0 + + + C_OVERRIDE_PLL + 0 + + + C_PRIMARY_PORT + clk_in1 + + + C_SECONDARY_PORT + clk_in2 + + + C_CLK_OUT1_PORT + clk_out1 + + + C_CLK_OUT2_PORT + clk_out2 + + + C_CLK_OUT3_PORT + clk_out3 + + + C_CLK_OUT4_PORT + clk_out4 + + + C_CLK_OUT5_PORT + clk_out5 + + + C_CLK_OUT6_PORT + clk_out6 + + + C_CLK_OUT7_PORT + clk_out7 + + + C_RESET_PORT + reset + + + C_LOCKED_PORT + locked + + + C_CLKFB_IN_PORT + clkfb_in + + + C_CLKFB_IN_P_PORT + clkfb_in_p + + + C_CLKFB_IN_N_PORT + clkfb_in_n + + + C_CLKFB_OUT_PORT + clkfb_out + + + C_CLKFB_OUT_P_PORT + clkfb_out_p + + + C_CLKFB_OUT_N_PORT + clkfb_out_n + + + C_POWER_DOWN_PORT + power_down + + + C_DADDR_PORT + daddr + + + C_DCLK_PORT + dclk + + + C_DRDY_PORT + drdy + + + C_DWE_PORT + dwe + + + C_DIN_PORT + din + + + C_DOUT_PORT + dout + + + C_DEN_PORT + den + + + C_PSCLK_PORT + psclk + + + C_PSEN_PORT + psen + + + C_PSINCDEC_PORT + psincdec + + + C_PSDONE_PORT + psdone + + + C_CLK_VALID_PORT + CLK_VALID + + + C_STATUS_PORT + STATUS + + + C_CLK_IN_SEL_PORT + clk_in_sel + + + C_INPUT_CLK_STOPPED_PORT + input_clk_stopped + + + C_CLKFB_STOPPED_PORT + clkfb_stopped + + + C_CLKIN1_JITTER_PS + 50.0 + + + C_CLKIN2_JITTER_PS + 100.0 + + + C_PRIMITIVE + MMCM + + + C_SS_MODE + CENTER_HIGH + + + C_SS_MOD_PERIOD + 4000 + + + C_SS_MOD_TIME + 0.004 + + + C_HAS_CDDC + 0 + + + C_CDDCDONE_PORT + cddcdone + + + C_CDDCREQ_PORT + cddcreq + + + C_CLKOUTPHY_MODE + VCO + + + C_ENABLE_CLKOUTPHY + 0 + + + C_INTERFACE_SELECTION + 0 + + + C_S_AXI_ADDR_WIDTH + C S Axi Addr Width + 11 + + + C_S_AXI_DATA_WIDTH + C S Axi Data Width + 32 + + + C_POWER_REG + 0000 + + + C_CLKOUT0_1 + 0000 + + + C_CLKOUT0_2 + 0000 + + + C_CLKOUT1_1 + 0000 + + + C_CLKOUT1_2 + 0000 + + + C_CLKOUT2_1 + 0000 + + + C_CLKOUT2_2 + 0000 + + + C_CLKOUT3_1 + 0000 + + + C_CLKOUT3_2 + 0000 + + + C_CLKOUT4_1 + 0000 + + + C_CLKOUT4_2 + 0000 + + + C_CLKOUT5_1 + 0000 + + + C_CLKOUT5_2 + 0000 + + + C_CLKOUT6_1 + 0000 + + + C_CLKOUT6_2 + 0000 + + + C_CLKFBOUT_1 + 0000 + + + C_CLKFBOUT_2 + 0000 + + + C_DIVCLK + 0000 + + + C_LOCK_1 + 0000 + + + C_LOCK_2 + 0000 + + + C_LOCK_3 + 0000 + + + C_FILTER_1 + 0000 + + + C_FILTER_2 + 0000 + + + C_DIVIDE1_AUTO + 1 + + + C_DIVIDE2_AUTO + 1.0 + + + C_DIVIDE3_AUTO + 1.0 + + + C_DIVIDE4_AUTO + 1.0 + + + C_DIVIDE5_AUTO + 1.0 + + + C_DIVIDE6_AUTO + 1.0 + + + C_DIVIDE7_AUTO + 1.0 + + + C_PLLBUFGCEDIV + false + + + C_MMCMBUFGCEDIV + false + + + C_PLLBUFGCEDIV1 + false + + + C_PLLBUFGCEDIV2 + false + + + C_PLLBUFGCEDIV3 + false + + + C_PLLBUFGCEDIV4 + false + + + C_MMCMBUFGCEDIV1 + false + + + C_MMCMBUFGCEDIV2 + false + + + C_MMCMBUFGCEDIV3 + false + + + C_MMCMBUFGCEDIV4 + false + + + C_MMCMBUFGCEDIV5 + false + + + C_MMCMBUFGCEDIV6 + false + + + C_MMCMBUFGCEDIV7 + false + + + C_CLKOUT1_MATCHED_ROUTING + false + + + C_CLKOUT2_MATCHED_ROUTING + false + + + C_CLKOUT3_MATCHED_ROUTING + false + + + C_CLKOUT4_MATCHED_ROUTING + false + + + C_CLKOUT5_MATCHED_ROUTING + false + + + C_CLKOUT6_MATCHED_ROUTING + false + + + C_CLKOUT7_MATCHED_ROUTING + false + + + C_CLKOUT0_ACTUAL_FREQ + 100.00000 + + + C_CLKOUT1_ACTUAL_FREQ + 100.000 + + + C_CLKOUT2_ACTUAL_FREQ + 100.000 + + + C_CLKOUT3_ACTUAL_FREQ + 100.000 + + + C_CLKOUT4_ACTUAL_FREQ + 100.000 + + + C_CLKOUT5_ACTUAL_FREQ + 100.000 + + + C_CLKOUT6_ACTUAL_FREQ + 100.000 + + + C_M_MAX + 64.000 + + + C_M_MIN + 2.000 + + + C_D_MAX + 93.000 + + + C_D_MIN + 1.000 + + + C_O_MAX + 128.000 + + + C_O_MIN + 1.000 + + + C_VCO_MIN + 600.000 + + + C_VCO_MAX + 1440.000 + + + + + + choice_list_1d3de01d + WAVEFORM + LATENCY + + + choice_list_876bfc32 + UI + PS + + + choice_list_a9bdfce0 + LOW + HIGH + OPTIMIZED + + + choice_list_ac75ef1e + Custom + + + choice_list_b9d38208 + CLKFBOUT + CLKOUT0 + + + choice_list_d0ea4aeb + MMCM + PLL + Auto + + + choice_pairs_035ca1c3 + SYSTEM_SYNCHRONOUS + SOURCE_SYNCHRONOUS + INTERNAL + EXTERNAL + + + choice_pairs_0920eb1b + Custom + sys_diff_clock + + + choice_pairs_11d71346 + Single_ended_clock_capable_pin + Differential_clock_capable_pin + Global_buffer + No_buffer + + + choice_pairs_15c806d5 + FDBK_AUTO + FDBK_AUTO_OFFCHIP + FDBK_ONCHIP + FDBK_OFFCHIP + + + choice_pairs_340369e0 + Custom + sys_clock + sys_diff_clock + + + choice_pairs_39d99e50 + Buffer + Buffer_with_CE + BUFG + BUFGCE + BUFGCE_DIV + No_buffer + + + choice_pairs_3c2d3ec7 + SINGLE + DIFF + + + choice_pairs_77d3d587 + MMCM + PLL + BUFGCE_DIV + + + choice_pairs_8b28f1f7 + Enable_AXI + Enable_DRP + + + choice_pairs_8eea9b32 + Units_MHz + Units_ns + + + choice_pairs_94e02745 + AUTO + EXTERNAL + INTERNAL + BUF_IN + ZHOLD + + + choice_pairs_a4fbc00c + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_a8642b4c + No_Jitter + Min_O_Jitter + Max_I_Jitter + + + choice_pairs_c5ef7212 + Units_UI + Units_ps + + + choice_pairs_e1c87518 + REL_PRIMARY + REL_SECONDARY + + + choice_pairs_f4e10086 + CENTER_HIGH + CENTER_LOW + DOWN_HIGH + DOWN_LOW + + + choice_pairs_f669c2f5 + frequency + Time + + + The Clocking Wizard creates an HDL file (Verilog or VHDL) that contains a clocking circuit customized to the user's clocking requirements. + + + Component_Name + clk_wiz_1 + + + USER_CLK_FREQ0 + User Frequency(MHz) + 100.0 + + + USER_CLK_FREQ1 + User Frequency(MHz) + 100.0 + + + USER_CLK_FREQ2 + User Frequency(MHz) + 100.0 + + + USER_CLK_FREQ3 + User Frequency(MHz) + 100.0 + + + ENABLE_CLOCK_MONITOR + Enable Clock Monitoring + false + + + ENABLE_USER_CLOCK0 + User Clock + false + + + ENABLE_USER_CLOCK1 + User Clock + false + + + ENABLE_USER_CLOCK2 + User Clock + false + + + ENABLE_USER_CLOCK3 + User Clock + false + + + Enable_PLL0 + User Clock + false + + + Enable_PLL1 + User Clock + false + + + REF_CLK_FREQ + Reference Frequency(MHz) + 100.0 + + + PRECISION + Tolerance(MHz) + 1 + + + PRIMITIVE + Primitive + MMCM + + + PRIMTYPE_SEL + Primtype Sel + mmcm_adv + + + CLOCK_MGR_TYPE + Clock Mgr Type + auto + + + USE_FREQ_SYNTH + true + + + USE_SPREAD_SPECTRUM + false + + + USE_PHASE_ALIGNMENT + true + + + USE_MIN_POWER + false + + + USE_DYN_PHASE_SHIFT + false + + + USE_DYN_RECONFIG + false + + + JITTER_SEL + No_Jitter + + + PRIM_IN_FREQ + 200.000 + + + PRIM_IN_TIMEPERIOD + 10.000 + + + IN_FREQ_UNITS + Units_MHz + + + PHASESHIFT_MODE + WAVEFORM + + + IN_JITTER_UNITS + Units_UI + + + RELATIVE_INCLK + REL_PRIMARY + + + USE_INCLK_SWITCHOVER + false + + + SECONDARY_IN_FREQ + 100.000 + + + SECONDARY_IN_TIMEPERIOD + 10.000 + + + SECONDARY_PORT + clk_in2 + + + SECONDARY_SOURCE + Single_ended_clock_capable_pin + + + JITTER_OPTIONS + UI + + + CLKIN1_UI_JITTER + 0.010 + + + CLKIN2_UI_JITTER + 0.010 + + + PRIM_IN_JITTER + 0.010 + + + SECONDARY_IN_JITTER + 0.010 + + + CLKIN1_JITTER_PS + 50.0 + + + CLKIN2_JITTER_PS + 100.0 + + + CLKOUT1_USED + true + + + CLKOUT2_USED + false + + + CLKOUT3_USED + false + + + CLKOUT4_USED + false + + + CLKOUT5_USED + false + + + CLKOUT6_USED + false + + + CLKOUT7_USED + false + + + NUM_OUT_CLKS + 1 + + + CLK_OUT1_USE_FINE_PS_GUI + false + + + CLK_OUT2_USE_FINE_PS_GUI + false + + + CLK_OUT3_USE_FINE_PS_GUI + false + + + CLK_OUT4_USE_FINE_PS_GUI + false + + + CLK_OUT5_USE_FINE_PS_GUI + false + + + CLK_OUT6_USE_FINE_PS_GUI + false + + + CLK_OUT7_USE_FINE_PS_GUI + false + + + PRIMARY_PORT + clk_in1 + + + CLK_OUT1_PORT + clk_out1 + + + CLK_OUT2_PORT + clk_out2 + + + CLK_OUT3_PORT + clk_out3 + + + CLK_OUT4_PORT + clk_out4 + + + CLK_OUT5_PORT + clk_out5 + + + CLK_OUT6_PORT + clk_out6 + + + CLK_OUT7_PORT + clk_out7 + + + DADDR_PORT + daddr + + + DCLK_PORT + dclk + + + DRDY_PORT + drdy + + + DWE_PORT + dwe + + + DIN_PORT + din + + + DOUT_PORT + dout + + + DEN_PORT + den + + + PSCLK_PORT + psclk + + + PSEN_PORT + psen + + + PSINCDEC_PORT + psincdec + + + PSDONE_PORT + psdone + + + CLKOUT1_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT1_REQUESTED_PHASE + 0.000 + + + CLKOUT1_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT2_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT2_REQUESTED_PHASE + 0.000 + + + CLKOUT2_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT3_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT3_REQUESTED_PHASE + 0.000 + + + CLKOUT3_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT4_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT4_REQUESTED_PHASE + 0.000 + + + CLKOUT4_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT5_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT5_REQUESTED_PHASE + 0.000 + + + CLKOUT5_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT6_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT6_REQUESTED_PHASE + 0.000 + + + CLKOUT6_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT7_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT7_REQUESTED_PHASE + 0.000 + + + CLKOUT7_REQUESTED_DUTY_CYCLE + 50.000 + + + USE_MAX_I_JITTER + false + + + USE_MIN_O_JITTER + false + + + CLKOUT1_MATCHED_ROUTING + false + + + CLKOUT2_MATCHED_ROUTING + false + + + CLKOUT3_MATCHED_ROUTING + false + + + CLKOUT4_MATCHED_ROUTING + false + + + CLKOUT5_MATCHED_ROUTING + false + + + CLKOUT6_MATCHED_ROUTING + false + + + CLKOUT7_MATCHED_ROUTING + false + + + PRIM_SOURCE + Differential_clock_capable_pin + + + CLKOUT1_DRIVES + Buffer + + + CLKOUT2_DRIVES + Buffer + + + CLKOUT3_DRIVES + Buffer + + + CLKOUT4_DRIVES + Buffer + + + CLKOUT5_DRIVES + Buffer + + + CLKOUT6_DRIVES + Buffer + + + CLKOUT7_DRIVES + Buffer + + + FEEDBACK_SOURCE + FDBK_AUTO + + + CLKFB_IN_SIGNALING + SINGLE + + + CLKFB_IN_PORT + clkfb_in + + + CLKFB_IN_P_PORT + clkfb_in_p + + + CLKFB_IN_N_PORT + clkfb_in_n + + + CLKFB_OUT_PORT + clkfb_out + + + CLKFB_OUT_P_PORT + clkfb_out_p + + + CLKFB_OUT_N_PORT + clkfb_out_n + + + PLATFORM + UNKNOWN + + + SUMMARY_STRINGS + empty + + + USE_LOCKED + true + + + CALC_DONE + empty + + + USE_RESET + true + + + USE_POWER_DOWN + false + + + USE_STATUS + false + + + USE_FREEZE + false + + + USE_CLK_VALID + false + + + USE_INCLK_STOPPED + false + + + USE_CLKFB_STOPPED + false + + + RESET_PORT + reset + + + LOCKED_PORT + locked + + + POWER_DOWN_PORT + power_down + + + CLK_VALID_PORT + CLK_VALID + + + STATUS_PORT + STATUS + + + CLK_IN_SEL_PORT + clk_in_sel + + + INPUT_CLK_STOPPED_PORT + input_clk_stopped + + + CLKFB_STOPPED_PORT + clkfb_stopped + + + SS_MODE + CENTER_HIGH + + + SS_MOD_FREQ + 250 + + + SS_MOD_TIME + 0.004 + + + OVERRIDE_MMCM + false + + + MMCM_NOTES + None + + + MMCM_DIVCLK_DIVIDE + 1 + + + MMCM_BANDWIDTH + OPTIMIZED + + + MMCM_CLKFBOUT_MULT_F + 5.000 + + + MMCM_CLKFBOUT_PHASE + 0.000 + + + MMCM_CLKFBOUT_USE_FINE_PS + false + + + MMCM_CLKIN1_PERIOD + 5.000 + + + MMCM_CLKIN2_PERIOD + 10.0 + + + MMCM_CLKOUT4_CASCADE + false + + + MMCM_CLOCK_HOLD + false + + + MMCM_COMPENSATION + AUTO + + + MMCM_REF_JITTER1 + 0.010 + + + MMCM_REF_JITTER2 + 0.010 + + + MMCM_STARTUP_WAIT + false + + + MMCM_CLKOUT0_DIVIDE_F + 10.000 + + + MMCM_CLKOUT0_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT0_PHASE + 0.000 + + + MMCM_CLKOUT0_USE_FINE_PS + false + + + MMCM_CLKOUT1_DIVIDE + 1 + + + MMCM_CLKOUT1_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT1_PHASE + 0.000 + + + MMCM_CLKOUT1_USE_FINE_PS + false + + + MMCM_CLKOUT2_DIVIDE + 1 + + + MMCM_CLKOUT2_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT2_PHASE + 0.000 + + + MMCM_CLKOUT2_USE_FINE_PS + false + + + MMCM_CLKOUT3_DIVIDE + 1 + + + MMCM_CLKOUT3_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT3_PHASE + 0.000 + + + MMCM_CLKOUT3_USE_FINE_PS + false + + + MMCM_CLKOUT4_DIVIDE + 1 + + + MMCM_CLKOUT4_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT4_PHASE + 0.000 + + + MMCM_CLKOUT4_USE_FINE_PS + false + + + MMCM_CLKOUT5_DIVIDE + 1 + + + MMCM_CLKOUT5_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT5_PHASE + 0.000 + + + MMCM_CLKOUT5_USE_FINE_PS + false + + + MMCM_CLKOUT6_DIVIDE + 1 + + + MMCM_CLKOUT6_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT6_PHASE + 0.000 + + + MMCM_CLKOUT6_USE_FINE_PS + false + + + OVERRIDE_PLL + false + + + PLL_NOTES + None + + + PLL_BANDWIDTH + OPTIMIZED + + + PLL_CLKFBOUT_MULT + 4 + + + PLL_CLKFBOUT_PHASE + 0.000 + + + PLL_CLK_FEEDBACK + CLKFBOUT + + + PLL_DIVCLK_DIVIDE + 1 + + + PLL_CLKIN_PERIOD + 10.000 + + + PLL_COMPENSATION + SYSTEM_SYNCHRONOUS + + + PLL_REF_JITTER + 0.010 + + + PLL_CLKOUT0_DIVIDE + 1 + + + PLL_CLKOUT0_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT0_PHASE + 0.000 + + + PLL_CLKOUT1_DIVIDE + 1 + + + PLL_CLKOUT1_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT1_PHASE + 0.000 + + + PLL_CLKOUT2_DIVIDE + 1 + + + PLL_CLKOUT2_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT2_PHASE + 0.000 + + + PLL_CLKOUT3_DIVIDE + 1 + + + PLL_CLKOUT3_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT3_PHASE + 0.000 + + + PLL_CLKOUT4_DIVIDE + 1 + + + PLL_CLKOUT4_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT4_PHASE + 0.000 + + + PLL_CLKOUT5_DIVIDE + 1 + + + PLL_CLKOUT5_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT5_PHASE + 0.000 + + + RESET_TYPE + Reset Type + ACTIVE_HIGH + + + USE_SAFE_CLOCK_STARTUP + false + + + USE_CLOCK_SEQUENCING + false + + + CLKOUT1_SEQUENCE_NUMBER + 1 + + + CLKOUT2_SEQUENCE_NUMBER + 1 + + + CLKOUT3_SEQUENCE_NUMBER + 1 + + + CLKOUT4_SEQUENCE_NUMBER + 1 + + + CLKOUT5_SEQUENCE_NUMBER + 1 + + + CLKOUT6_SEQUENCE_NUMBER + 1 + + + CLKOUT7_SEQUENCE_NUMBER + 1 + + + USE_BOARD_FLOW + Generate Board based IO Constraints + false + + + CLK_IN1_BOARD_INTERFACE + Custom + + + CLK_IN2_BOARD_INTERFACE + Custom + + + DIFF_CLK_IN1_BOARD_INTERFACE + Custom + + + DIFF_CLK_IN2_BOARD_INTERFACE + Custom + + + AUTO_PRIMITIVE + MMCM + + + RESET_BOARD_INTERFACE + Custom + + + ENABLE_CDDC + false + + + CDDCDONE_PORT + cddcdone + + + CDDCREQ_PORT + cddcreq + + + ENABLE_CLKOUTPHY + false + + + CLKOUTPHY_REQUESTED_FREQ + 600.000 + + + CLKOUT1_JITTER + Clkout1 Jitter + 112.316 + + + CLKOUT1_PHASE_ERROR + Clkout1 Phase + 89.971 + + + CLKOUT2_JITTER + Clkout2 Jitter + 0.0 + + + CLKOUT2_PHASE_ERROR + Clkout2 Phase + 0.0 + + + CLKOUT3_JITTER + Clkout3 Jitter + 0.0 + + + CLKOUT3_PHASE_ERROR + Clkout3 Phase + 0.0 + + + CLKOUT4_JITTER + Clkout4 Jitter + 0.0 + + + CLKOUT4_PHASE_ERROR + Clkout4 Phase + 0.0 + + + CLKOUT5_JITTER + Clkout5 Jitter + 0.0 + + + CLKOUT5_PHASE_ERROR + Clkout5 Phase + 0.0 + + + CLKOUT6_JITTER + Clkout6 Jitter + 0.0 + + + CLKOUT6_PHASE_ERROR + Clkout6 Phase + 0.0 + + + CLKOUT7_JITTER + Clkout7 Jitter + 0.0 + + + CLKOUT7_PHASE_ERROR + Clkout7 Phase + 0.0 + + + INPUT_MODE + frequency + + + INTERFACE_SELECTION + Enable_AXI + + + AXI_DRP + Write DRP registers + false + + + PHASE_DUTY_CONFIG + Phase Duty Cycle Config + false + + + + + Clocking Wizard + + XPM_CDC + + 5 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.1 + + + + + + + + diff --git a/hub_test/scripts/generate_software.tcl b/hub_test/scripts/generate_software.tcl index 678fcf4..5c7d9a7 100644 --- a/hub_test/scripts/generate_software.tcl +++ b/hub_test/scripts/generate_software.tcl @@ -2,5 +2,7 @@ setws vitis_workspace platform create -name "hub_test_platform" -hw hub_test.xsa domain create -name "hub_test_domain" -os standalone -proc microblaze_0 app create -name init -domain hub_test_domain -template "Empty Application" +app config -name init -set build-config Release importsources -name init -path sw/init.c +importsources -name init -path ../../si5345/ app build -name init diff --git a/hub_test/src/hub_test.vhd b/hub_test/src/hub_test.vhd index 2b4f355..cdaea5e 100644 --- a/hub_test/src/hub_test.vhd +++ b/hub_test/src/hub_test.vhd @@ -13,30 +13,46 @@ use work.version.all; entity hub_test is port ( - MGTREFCLK_P : in std_logic; - MGTREFCLK_N : in std_logic; - - RXN : in std_logic_vector(11 downto 0); - RXP : in std_logic_vector(11 downto 0); - TXN : out std_logic_vector(11 downto 0); - TXP : out std_logic_vector(11 downto 0); - - CLK_200_P : in std_logic; - CLK_200_N : in std_logic; - - MPOD_RESET_N : out std_logic_vector(3 downto 0); - - SDA : inout std_logic; - SCL : inout std_logic; - - TRG_OUT_0_P : out std_logic; - TRG_OUT_0_N : out std_logic; - TRG_OUT_1_P : out std_logic; - TRG_OUT_1_N : out std_logic; - TRG_OUT_2_P : out std_logic; - TRG_OUT_2_N : out std_logic; - TRG_OUT_3_P : out std_logic; - TRG_OUT_3_N : out std_logic + CLK_200_P : in std_logic; + CLK_200_N : in std_logic; + + SI5345_IN0_P : out std_logic; -- 100 MHz + SI5345_IN0_N : out std_logic; + SI5345_OUT7_P : in std_logic; -- 100 MHz + SI5345_OUT7_N : in std_logic; + + MPOD_RX1_RESET_N : out STD_LOGIC; + MPOD_RX2_RESET_N : out STD_LOGIC; + MPOD_TX1_RESET_N : out STD_LOGIC; + MPOD_TX2_RESET_N : out STD_LOGIC; + SI5345_RST_N : out std_logic; + SI5345_I2C_SEL : out std_logic; + SI5345_LOL_N : in std_logic; + PCA9546A_DEVS_RESET_N : out STD_LOGIC; + PCA9546A_PCIE_RESET_N : out STD_LOGIC; + PEX_I2C_SEL0 : out STD_LOGIC; + PEX_I2C_SEL1 : out STD_LOGIC; + UC_RESET_N : out STD_LOGIC; + + MGTREFCLK_P : in std_logic; -- 100 MHz, sync. with SI5345_IN0_P + MGTREFCLK_N : in std_logic; + + RXN : in std_logic_vector(11 downto 0); + RXP : in std_logic_vector(11 downto 0); + TXN : out std_logic_vector(11 downto 0); + TXP : out std_logic_vector(11 downto 0); + + SDA : inout std_logic; + SCL : inout std_logic; + + TRG_OUT_0_P : out std_logic; + TRG_OUT_0_N : out std_logic; + TRG_OUT_1_P : out std_logic; + TRG_OUT_1_N : out std_logic; + TRG_OUT_2_P : out std_logic; + TRG_OUT_2_N : out std_logic; + TRG_OUT_3_P : out std_logic; + TRG_OUT_3_N : out std_logic ); end entity hub_test; @@ -60,10 +76,29 @@ architecture behavioral of hub_test is ); end component; + component clk_wiz_1 + port ( + clk_out1 : out std_logic; + reset : in std_logic; + locked : out std_logic; + clk_in1_p : in std_logic; + clk_in1_n : in std_logic + ); + end component; + + signal baseclk_100 : std_logic; + signal baseclk_locked : std_logic; + signal baseclk_out : std_logic; + signal microblaze_reset : std_logic; + signal resets_from_microblaze : std_logic_vector(7 downto 0); + + signal sysclk_reset : std_logic; signal sysclk_100 : std_logic; signal sysclk_200 : std_logic; signal sysclk_locked : std_logic; - signal sysclk_not_locked : std_logic; + + signal usrclk_vec : std_logic_vector(3 downto 0); + signal usrclk_double_vec : std_logic_vector(3 downto 0); signal mgtrefclk : std_logic; @@ -185,18 +220,49 @@ architecture behavioral of hub_test is signal ms_count : integer range 0 to MS_PERIOD_COUNTS - 1 := 0; signal trg_out : std_logic := '0'; begin - MPOD_RESET_N <= "1111"; + THE_BASECLK : clk_wiz_1 + port map ( + clk_out1 => baseclk_100, + reset => '0', + locked => baseclk_locked, + clk_in1_p => CLK_200_P, + clk_in1_n => CLK_200_N + ); + microblaze_reset <= not baseclk_locked; + + ODDRE1_baseclk : ODDRE1 + generic map ( + IS_C_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + SIM_DEVICE => "ULTRASCALE", + SRVAL => '0' + ) + port map ( + Q => baseclk_out, + C => baseclk_100, + D1 => '1', + D2 => '0', + SR => microblaze_reset + ); + OBUFDS_baseclk : OBUFDS + port map ( + O => SI5345_IN0_P, + OB => SI5345_IN0_N, + I => baseclk_out + ); + + sysclk_reset <= not SI5345_LOL_N; THE_SYSCLK : clk_wiz_0 port map ( clk_out1 => sysclk_100, clk_out2 => sysclk_200, - reset => '0', + reset => sysclk_reset, locked => sysclk_locked, - clk_in1_p => CLK_200_P, - clk_in1_n => CLK_200_N + clk_in1_p => SI5345_OUT7_P, + clk_in1_n => SI5345_OUT7_N ); - sysclk_not_locked <= not sysclk_locked; THE_MGTREFCLK0_X0Y3 : IBUFDS_GTE3 port map ( @@ -251,6 +317,8 @@ begin DEBUG_OUT => open ); + usrclk_vec <= sysclk_100 & sysclk_100 & sysclk_100 & sysclk_100; + usrclk_double_vec <= sysclk_200 & sysclk_200 & sysclk_200 & sysclk_200; THE_MEDIA_4_PCSB : entity work.med_xcku_sfp_sync_4 generic map ( @@ -261,6 +329,16 @@ begin SYSCLK => sysclk_100, CLK_200 => sysclk_200, GTREFCLK => mgtrefclk, + RXOUTCLK => open, + TXOUTCLK => open, + RXUSRCLK => usrclk_vec, + RXUSRCLK_DOUBLE => usrclk_double_vec, + TXUSRCLK => usrclk_vec, + TXUSRCLK_DOUBLE => usrclk_double_vec, + RXUSRCLK_ACTIVE => sysclk_locked, + TXUSRCLK_ACTIVE => sysclk_locked, + RXPMARESETDONE => open, + TXPMARESETDONE => open, RESET => reset, CLEAR => clear, RXN => RXN(3 downto 0), @@ -351,6 +429,16 @@ begin SYSCLK => sysclk_100, CLK_200 => sysclk_200, GTREFCLK => mgtrefclk, + RXOUTCLK => open, + TXOUTCLK => open, + RXUSRCLK => usrclk_vec, + RXUSRCLK_DOUBLE => usrclk_double_vec, + TXUSRCLK => usrclk_vec, + TXUSRCLK_DOUBLE => usrclk_double_vec, + RXUSRCLK_ACTIVE => sysclk_locked, + TXUSRCLK_ACTIVE => sysclk_locked, + RXPMARESETDONE => open, + TXPMARESETDONE => open, RESET => reset, CLEAR => clear, RXN => RXN(7 downto 4), @@ -393,6 +481,16 @@ begin SYSCLK => sysclk_100, CLK_200 => sysclk_200, GTREFCLK => mgtrefclk, + RXOUTCLK => open, + TXOUTCLK => open, + RXUSRCLK => usrclk_vec, + RXUSRCLK_DOUBLE => usrclk_double_vec, + TXUSRCLK => usrclk_vec, + TXUSRCLK_DOUBLE => usrclk_double_vec, + RXUSRCLK_ACTIVE => sysclk_locked, + TXUSRCLK_ACTIVE => sysclk_locked, + RXPMARESETDONE => open, + TXPMARESETDONE => open, RESET => reset, CLEAR => clear, RXN => RXN(11 downto 8), @@ -610,7 +708,7 @@ begin design_1_wrapper_i : entity work.design_1_wrapper port map ( - CLK => sysclk_100, + CLK => baseclk_100, I2C_scl_io => SCL, I2C_sda_io => SDA, MPOD_LOS_0_tri_o(11 downto 0) => mpod_a_los, @@ -621,6 +719,19 @@ begin MPOD_TXDIS_0_tri_i(23 downto 12) => mpod_b_txdis, MPOD_TXDIS_1_tri_i(11 downto 0) => mpod_c_txdis, MPOD_TXDIS_1_tri_i(23 downto 12) => mpod_d_txdis, - RESET => sysclk_not_locked + RESET => microblaze_reset, + RESETS_tri_o => resets_from_microblaze ); + + MPOD_RX1_RESET_N <= resets_from_microblaze(0); + MPOD_RX2_RESET_N <= resets_from_microblaze(1); + MPOD_TX1_RESET_N <= resets_from_microblaze(2); + MPOD_TX2_RESET_N <= resets_from_microblaze(3); + SI5345_RST_N <= resets_from_microblaze(4); + PCA9546A_DEVS_RESET_N <= resets_from_microblaze(5); + PCA9546A_PCIE_RESET_N <= resets_from_microblaze(6); + UC_RESET_N <= resets_from_microblaze(7); + SI5345_I2C_SEL <= '1'; + PEX_I2C_SEL0 <= '1'; + PEX_I2C_SEL1 <= '1'; end architecture; diff --git a/hub_test/sw/init.c b/hub_test/sw/init.c index 6ff53b2..173f82f 100644 --- a/hub_test/sw/init.c +++ b/hub_test/sw/init.c @@ -6,13 +6,24 @@ #include "xil_cache.h" #include "xil_printf.h" -int read_reg(u8 addr, u8 reg, u8 *val); -int write_reg(u8 addr, u8 reg, u8 val); +#include "Si5345-RevD-CRI_100E-Registers.h" +#define NUM_PAGES (12) + +#define SUCCESS (0) +#define ERR_SEND (1) +#define ERR_RECEIVE (2) +#define ERR_PAGE_NUM (3) + +static int read_reg(u8 addr, u8 reg, u8 *val); +static int write_reg(u8 addr, u8 reg, u8 val); +static int write_pca9546a_ctrl_reg(u8 val); +static int set_si5345_page(u8 page); +static int write_si5345_regs(); +static int update_mpods(); int main() { - unsigned res; - u8 val; + int res; #ifdef XPAR_MICROBLAZE_USE_ICACHE Xil_ICacheEnable(); @@ -21,18 +32,125 @@ int main() Xil_DCacheEnable(); #endif - sleep(1); + print("Resetting external devices.\r\n"); + XGpio_WriteReg(XPAR_AXI_GPIO_RESETS_BASEADDR, + (0 * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET, 0x00000000); + usleep(1); + XGpio_WriteReg(XPAR_AXI_GPIO_RESETS_BASEADDR, + (0 * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET, 0xFFFFFFFF); + + print("\r\n"); + print("Writing PCA9546A control register.\r\n"); + while ((res = write_pca9546a_ctrl_reg(0x04)) != SUCCESS) { + xil_printf("Error %d\r\n", res); + sleep(1); + } + print("OK\r\n"); + + print("Writing Si5345 registers.\r\n"); + while ((res = write_si5345_regs()) != SUCCESS) { + xil_printf("Error %d\r\n", res); + sleep(1); + } + print("OK\r\n"); + + print("Writing PCA9546A control register.\r\n"); + while ((res = write_pca9546a_ctrl_reg(0x08)) != SUCCESS) { + xil_printf("Error %d\r\n", res); + sleep(1); + } + print("OK\r\n"); + + print("Entering register R/W loop.\r\n"); + for (;;) { + if (update_mpods() == SUCCESS) + print("."); + else + print("E"); - val = 0x08; - print("\r\nWriting PCA9546A control register... "); - res = XIic_Send(XPAR_IIC_0_BASEADDR, 0x70, &val, 1, XIIC_STOP); - if (!res) { - print("Error.\r\n"); - return -1; - } else { - xil_printf("Done.\r\n", val); + sleep(1); } +#ifdef XPAR_MICROBLAZE_USE_DCACHE + Xil_DCacheDisable(); +#endif +#ifdef XPAR_MICROBLAZE_USE_ICACHE + Xil_ICacheDisable(); +#endif + + return SUCCESS; +} + +static int read_reg(u8 addr, u8 reg, u8 *val) +{ + if (XIic_Send(XPAR_IIC_0_BASEADDR, addr, ®, 1, XIIC_REPEATED_START) != 1) + return ERR_SEND; + + if (XIic_Recv(XPAR_IIC_0_BASEADDR, addr, val, 1, XIIC_STOP) != 1) + return ERR_RECEIVE; + + return SUCCESS; +} + +static int write_reg(u8 addr, u8 reg, u8 val) +{ + u8 writeval[2] = {reg, val}; + + if (XIic_Send(XPAR_IIC_0_BASEADDR, addr, writeval, 2, XIIC_STOP) != 2) + return ERR_SEND; + + return SUCCESS; +} + +static int write_pca9546a_ctrl_reg(u8 val) +{ + if (XIic_Send(XPAR_IIC_0_BASEADDR, 0x70, &val, 1, XIIC_STOP) != 1) + return ERR_SEND; + + return SUCCESS; +} + +static int set_si5345_page(u8 page) +{ + if (page >= NUM_PAGES) + return ERR_PAGE_NUM; + + return write_reg(0x68, 0x01, page); +} + +static int write_si5345_regs() +{ + int i; + int res; + u16 addr; + u8 val; + u8 page; + + page = 0xFF; + for (i = 0; i < SI5345_REVD_REG_CONFIG_NUM_REGS; ++i) { + addr = si5345_revd_registers[i].address; + val = si5345_revd_registers[i].value; + + if (page != ((addr >> 8) & 0xFF)) { + page = ((addr >> 8) & 0xFF); + if ((res = set_si5345_page(page)) != SUCCESS) + return res; + } + + if ((res = write_reg(0x68, addr & 0xFF, val)) != SUCCESS) + return res; + + // Required wait time according to the registers file + if (i == 2) + usleep(300); + } + + return SUCCESS; +} + + +static int update_mpods() +{ // 30/2C is RX/TX-MPOD A // 31/2D is RX/TX-MPOD C // 32/2E is RX/TX-MPOD D @@ -48,127 +166,87 @@ int main() // RX reg 10/TX reg 93 7..0 is ch 7..0 // MTP fibers 12..1 correspond to MPOD ch's 11..0 - for (;;) { - u32 gpio_val; - - // RX LOS - gpio_val = 0; - - if (read_reg(0x30, 10, &val)) - return -1; - gpio_val |= ((u32)val & 0xFF) << 0; - - if (read_reg(0x30, 9, &val)) - return -1; - gpio_val |= ((u32)val & 0x0F) << 8; - - if (read_reg(0x33, 10, &val)) - return -1; - gpio_val |= ((u32)val & 0xFF) << 12; + int res; + u32 gpio_val; + u8 val; - if (read_reg(0x33, 9, &val)) - return -1; - gpio_val |= ((u32)val & 0x0F) << 20; + // RX LOS + gpio_val = 0; - XGpio_WriteReg(XPAR_AXI_GPIO_MPOD_LOS_BASEADDR, XGPIO_DATA_OFFSET, gpio_val); + if ((res = read_reg(0x30, 10, &val)) != SUCCESS) + return res; + gpio_val |= ((u32)val & 0xFF) << 0; - gpio_val = 0; + if ((res = read_reg(0x30, 9, &val)) != SUCCESS) + return res; + gpio_val |= ((u32)val & 0x0F) << 8; - if (read_reg(0x31, 10, &val)) - return -1; - gpio_val |= ((u32)val & 0xFF) << 0; + if ((res = read_reg(0x33, 10, &val)) != SUCCESS) + return res; + gpio_val |= ((u32)val & 0xFF) << 12; - if (read_reg(0x31, 9, &val)) - return -1; - gpio_val |= ((u32)val & 0x0F) << 8; + if ((res = read_reg(0x33, 9, &val)) != SUCCESS) + return res; + gpio_val |= ((u32)val & 0x0F) << 20; - if (read_reg(0x32, 10, &val)) - return -1; - gpio_val |= ((u32)val & 0xFF) << 12; + XGpio_WriteReg(XPAR_AXI_GPIO_MPOD_LOS_BASEADDR, XGPIO_DATA_OFFSET, gpio_val); - if (read_reg(0x32, 9, &val)) - return -1; - gpio_val |= ((u32)val & 0x0F) << 20; + gpio_val = 0; - XGpio_WriteReg(XPAR_AXI_GPIO_MPOD_LOS_BASEADDR, XGPIO_DATA2_OFFSET, gpio_val); + if ((res = read_reg(0x31, 10, &val)) != SUCCESS) + return res; + gpio_val |= ((u32)val & 0xFF) << 0; - // TX Disable - gpio_val = XGpio_ReadReg(XPAR_AXI_GPIO_MPOD_TXDIS_BASEADDR, XGPIO_DATA_OFFSET); + if ((res = read_reg(0x31, 9, &val)) != SUCCESS) + return res; + gpio_val |= ((u32)val & 0x0F) << 8; - val = (gpio_val >> 0) & 0xFF; - if (write_reg(0x2C, 93, val)) - return -1; + if ((res = read_reg(0x32, 10, &val)) != SUCCESS) + return res; + gpio_val |= ((u32)val & 0xFF) << 12; - val = (gpio_val >> 8) & 0x0F; - if (write_reg(0x2C, 92, val)) - return -1; + if ((res = read_reg(0x32, 9, &val)) != SUCCESS) + return res; + gpio_val |= ((u32)val & 0x0F) << 20; - val = (gpio_val >> 12) & 0xFF; - if (write_reg(0x2F, 93, val)) - return -1; + XGpio_WriteReg(XPAR_AXI_GPIO_MPOD_LOS_BASEADDR, XGPIO_DATA2_OFFSET, gpio_val); - val = (gpio_val >> 20) & 0x0F; - if (write_reg(0x2F, 92, val)) - return -1; + // TX Disable + gpio_val = XGpio_ReadReg(XPAR_AXI_GPIO_MPOD_TXDIS_BASEADDR, XGPIO_DATA_OFFSET); - gpio_val = XGpio_ReadReg(XPAR_AXI_GPIO_MPOD_TXDIS_BASEADDR, XGPIO_DATA2_OFFSET); + val = (gpio_val >> 0) & 0xFF; + if ((res = write_reg(0x2C, 93, val)) != SUCCESS) + return res; - val = (gpio_val >> 0) & 0xFF; - if (write_reg(0x2D, 93, val)) - return -1; + val = (gpio_val >> 8) & 0x0F; + if ((res = write_reg(0x2C, 92, val)) != SUCCESS) + return res; - val = (gpio_val >> 8) & 0x0F; - if (write_reg(0x2D, 92, val)) - return -1; + val = (gpio_val >> 12) & 0xFF; + if ((res = write_reg(0x2F, 93, val)) != SUCCESS) + return res; - val = (gpio_val >> 12) & 0xFF; - if (write_reg(0x2E, 93, val)) - return -1; + val = (gpio_val >> 20) & 0x0F; + if ((res = write_reg(0x2F, 92, val)) != SUCCESS) + return res; - val = (gpio_val >> 20) & 0x0F; - if (write_reg(0x2E, 92, val)) - return -1; + gpio_val = XGpio_ReadReg(XPAR_AXI_GPIO_MPOD_TXDIS_BASEADDR, XGPIO_DATA2_OFFSET); - sleep(1); - } + val = (gpio_val >> 0) & 0xFF; + if ((res = write_reg(0x2D, 93, val)) != SUCCESS) + return res; -#ifdef XPAR_MICROBLAZE_USE_DCACHE - Xil_DCacheDisable(); -#endif -#ifdef XPAR_MICROBLAZE_USE_ICACHE - Xil_ICacheDisable(); -#endif + val = (gpio_val >> 8) & 0x0F; + if ((res = write_reg(0x2D, 92, val)) != SUCCESS) + return res; - return 0; -} + val = (gpio_val >> 12) & 0xFF; + if ((res = write_reg(0x2E, 93, val)) != SUCCESS) + return res; -int read_reg(u8 addr, u8 reg, u8 *val){ - int res; - - xil_printf("R dev 0x%02x reg %3d -> ", addr, reg); - res = XIic_Send(XPAR_IIC_0_BASEADDR, addr, ®, 1, XIIC_REPEATED_START); - if (!res) { - print("Write error.\r\n"); - return -1; - } - res = XIic_Recv(XPAR_IIC_0_BASEADDR, addr, val, 1, XIIC_STOP); - if (!res) { - print("Read error.\r\n"); - return -1; - } - xil_printf("0x%02x\r\n", *val); - return 0; -} + val = (gpio_val >> 20) & 0x0F; + if ((res = write_reg(0x2E, 92, val)) != SUCCESS) + return res; -int write_reg(u8 addr, u8 reg, u8 val){ - u8 writeval[2] = {reg, val}; - int res; - - xil_printf("W dev 0x%02x reg %3d <- 0x%02x\r\n", addr, reg, val); - res = XIic_Send(XPAR_IIC_0_BASEADDR, addr, writeval, 2, XIIC_STOP); - if (!res) { - print("Write error.\r\n"); - return -1; - } - return 0; + return SUCCESS; }