From: Michael Boehmer <mboehmer@ph.tum.de>
Date: Fri, 4 Feb 2022 23:24:12 +0000 (+0100)
Subject: before TDC
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=977a985250d66bbafe974b731b29bb8d9be77709;p=trbnet.git

before TDC
---

diff --git a/special/phaser_core.vhd b/special/phaser_core.vhd
index db36867..7f11e36 100644
--- a/special/phaser_core.vhd
+++ b/special/phaser_core.vhd
@@ -1,6 +1,8 @@
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
+library ECP3;
+use ECP3.components.all;
 
 library work;
 
@@ -24,13 +26,14 @@ architecture phaser_core_arch of phaser_core is
 -- Signals
   signal ping_i         : std_logic;
   signal pong_i         : std_logic;
+  signal ping_i_q       : std_logic;
+  signal pong_i_q       : std_logic;
   signal phase_x        : std_logic;
-  signal phase          : std_logic;
 
   attribute HGROUP : string;
   attribute BBOX   : string;
   attribute HGROUP of phaser_core_arch : architecture is "phaser_core_group";
-  attribute BBOX   of phaser_core_arch : architecture is "1,1";
+  attribute BBOX   of phaser_core_arch : architecture is "1,2";
   attribute syn_sharing : string;
   attribute syn_sharing of phaser_core_arch : architecture is "off";
   attribute syn_hier : string;
@@ -42,14 +45,25 @@ begin
 -- we want all logic in here in one PFU (defined timing)!
 ---------------------------------------------------------------------------
 
+--  PINGFF : FD1S3AX port map ( CK => CLK_PING, D => PING_IN, Q => ping_i );
+--  PONGFF : FD1S3AX port map ( CK => CLK_PONG, D => PONG_IN, Q => pong_i );
+--
+--  PINQFF : FD1S3AX port map ( CK => SAMPLE_CLK, D => ping_i, Q => ping_i_q );
+--  PONQFF : FD1S3AX port map ( CK => SAMPLE_CLK, D => pong_i, Q => pong_i_q );
+--
+--  PHXLUT: LUT4 generic map ( INIT => b"0000_0000_0000_0110")
+--    port map ( A => ping_i_q, B => pong_i_q, C => '0', D => '0', Z => phase_x );
+        
   -- slice 0
-  ping_i  <= PING_IN when rising_edge(CLK_PING);   -- FF
+  ping_i   <= PING_IN when rising_edge(CLK_PING);   -- FF
   -- slice 1
-  pong_i  <= PONG_IN when rising_edge(CLK_PONG);   -- FF
+  pong_i   <= PONG_IN when rising_edge(CLK_PONG);   -- FF
   -- slice 2
-  phase_x <= ping_i xor pong_i;                    -- LUT4
-  phase   <= phase_x when rising_edge(SAMPLE_CLK); -- FF
+  ping_i_q <= ping_i  when rising_edge(SAMPLE_CLK); -- FF
+  pong_i_q <= pong_i  when rising_edge(SAMPLE_CLK); -- FF
+  -- slice 3
+  phase_x  <= ping_i_q xor pong_i_q;                -- LUT4
 
-  PHASE_OUT <= phase;
+  PHASE_OUT <= phase_x;
 
 end architecture;
diff --git a/special/phaser_core_ORIG.vhd b/special/phaser_core_ORIG.vhd
new file mode 100644
index 0000000..db36867
--- /dev/null
+++ b/special/phaser_core_ORIG.vhd
@@ -0,0 +1,55 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+
+entity phaser_core is
+  port(
+    SAMPLE_CLK    : in  std_logic;
+    PING_IN       : in  std_logic; -- TX K
+    CLK_PING      : in  std_logic; -- TX CLK
+    PONG_IN       : in  std_logic; -- RX K
+    CLK_PONG      : in  std_logic; -- RX CLK
+    PHASE_OUT     : out std_logic
+  );
+end entity phaser_core;
+
+architecture phaser_core_arch of phaser_core is
+
+-- Components
+
+-- state machine signals
+
+-- Signals
+  signal ping_i         : std_logic;
+  signal pong_i         : std_logic;
+  signal phase_x        : std_logic;
+  signal phase          : std_logic;
+
+  attribute HGROUP : string;
+  attribute BBOX   : string;
+  attribute HGROUP of phaser_core_arch : architecture is "phaser_core_group";
+  attribute BBOX   of phaser_core_arch : architecture is "1,1";
+  attribute syn_sharing : string;
+  attribute syn_sharing of phaser_core_arch : architecture is "off";
+  attribute syn_hier : string;
+  attribute syn_hier of phaser_core_arch : architecture is "hard";
+  
+begin
+
+---------------------------------------------------------------------------
+-- we want all logic in here in one PFU (defined timing)!
+---------------------------------------------------------------------------
+
+  -- slice 0
+  ping_i  <= PING_IN when rising_edge(CLK_PING);   -- FF
+  -- slice 1
+  pong_i  <= PONG_IN when rising_edge(CLK_PONG);   -- FF
+  -- slice 2
+  phase_x <= ping_i xor pong_i;                    -- LUT4
+  phase   <= phase_x when rising_edge(SAMPLE_CLK); -- FF
+
+  PHASE_OUT <= phase;
+
+end architecture;