From: Jan Michel Date: Wed, 17 Dec 2014 15:55:07 +0000 (+0100) Subject: added MAC component X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=97c9eef8e67a837ab3e401f3ba582256a85360e8;p=trb3.git added MAC component --- diff --git a/ADC/cores/mulacc2.ipx b/ADC/cores/mulacc2.ipx new file mode 100644 index 0000000..93ce490 --- /dev/null +++ b/ADC/cores/mulacc2.ipx @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/ADC/cores/mulacc2.lpc b/ADC/cores/mulacc2.lpc new file mode 100644 index 0000000..3b0fedd --- /dev/null +++ b/ADC/cores/mulacc2.lpc @@ -0,0 +1,67 @@ +[Device] +Family=latticeecp3 +PartType=LAE3-17EA +PartName=LAE3-17EA-6FN484E +SpeedGrade=6 +Package=FPBGA484 +OperatingCondition=AUTO +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=MAC +CoreRevision=4.2 +ModuleName=mulacc2 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=12/17/2014 +Time=16:27:11 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +widtha=9 +widthb=16 +widthp=41 +gsr=ENABLED +area_speed=Area +reset=SYNC +addsub=Add +InputA=Parallel +InputB=Parallel +SignedA=Signed +SignedB=Unsigned +shiftouta=0 +shiftoutb=0 +EnIRA=1 +EnIRB=1 +EnPR=0 +EnOR=1 +EnRST=1 +EnCE=1 +EnIRA=1 +EnIRAClk=CLK0 +EnIRACE=CE0 +EnIRARST=RST0 +EnIRB=1 +EnIRBClk=CLK0 +EnIRBCE=CE0 +EnIRBRST=RST0 +EnPR=0 +EnPRClk= +EnPRCE= +EnPRRST= +EnOR=1 +EnORClk=InputA +EnORCE=CE0 +EnORRST=InputA + +[Command] +cmd_line= -w -n mulacc2 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type dspmac -widtha 9 -widthb 16 -widthp 41 -area -load -macadd -signed -unsignedb -rega -regaclk CLK0 -regace CE0 -regarst RST0 -regb -regbclk CLK0 -regbce CE0 -regbrst RST0 -rego -regoclk CLK0 -regorst RST0 -regoce CE0 -enable_sync -clk0 -ce0 -rst0 diff --git a/ADC/cores/mulacc2.vhd b/ADC/cores/mulacc2.vhd new file mode 100644 index 0000000..8768371 --- /dev/null +++ b/ADC/cores/mulacc2.vhd @@ -0,0 +1,1150 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.2.0.134 +-- Module Version: 4.2 +--/d/jspc29/lattice/diamond/3.2_x64/ispfpga/bin/lin64/scuba -w -n mulacc2 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type dspmac -widtha 9 -widthb 16 -widthp 41 -area -load -macadd -signed -unsignedb -rega -regaclk CLK0 -regace CE0 -regarst RST0 -regb -regbclk CLK0 -regbce CE0 -regbrst RST0 -rego -regoclk CLK0 -regorst RST0 -regoce CE0 -enable_sync -clk0 -ce0 -rst0 + +-- Wed Dec 17 16:27:11 2014 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity mulacc2 is + port ( + CLK0: in std_logic; + CE0: in std_logic; + RST0: in std_logic; + ACCUMSLOAD: in std_logic; + A: in std_logic_vector(8 downto 0); + B: in std_logic_vector(15 downto 0); + LD: in std_logic_vector(40 downto 0); + OVERFLOW: out std_logic; + ACCUM: out std_logic_vector(40 downto 0)); +end mulacc2; + +architecture Structure of mulacc2 is + + -- internal signal declarations + signal high_inv: std_logic; + signal mulacc2_alu_signedr_1_0: std_logic; + signal mulacc2_alu_output_r_1_0_53: std_logic; + signal mulacc2_alu_output_r_1_0_52: std_logic; + signal mulacc2_alu_output_r_1_0_51: std_logic; + signal mulacc2_alu_output_r_1_0_50: std_logic; + signal mulacc2_alu_output_r_1_0_49: std_logic; + signal mulacc2_alu_output_r_1_0_48: std_logic; + signal mulacc2_alu_output_r_1_0_47: std_logic; + signal mulacc2_alu_output_r_1_0_46: std_logic; + signal mulacc2_alu_output_r_1_0_45: std_logic; + signal mulacc2_alu_output_r_1_0_44: std_logic; + signal mulacc2_alu_output_r_1_0_43: std_logic; + signal mulacc2_alu_output_r_1_0_42: std_logic; + signal mulacc2_alu_output_r_1_0_41: std_logic; + signal mulacc2_alu_output_r_1_0_40: std_logic; + signal mulacc2_alu_output_r_1_0_39: std_logic; + signal mulacc2_alu_output_r_1_0_38: std_logic; + signal mulacc2_alu_output_r_1_0_37: std_logic; + signal mulacc2_alu_output_r_1_0_36: std_logic; + signal mulacc2_alu_output_r_1_0_35: std_logic; + signal mulacc2_alu_output_r_1_0_34: std_logic; + signal mulacc2_alu_output_r_1_0_33: std_logic; + signal mulacc2_alu_output_r_1_0_32: std_logic; + signal mulacc2_alu_output_r_1_0_31: std_logic; + signal mulacc2_alu_output_r_1_0_30: std_logic; + signal mulacc2_alu_output_r_1_0_29: std_logic; + signal mulacc2_alu_output_r_1_0_28: std_logic; + signal mulacc2_alu_output_r_1_0_27: std_logic; + signal mulacc2_alu_output_r_1_0_26: std_logic; + signal mulacc2_alu_output_r_1_0_25: std_logic; + signal mulacc2_alu_output_r_1_0_24: std_logic; + signal mulacc2_alu_output_r_1_0_23: std_logic; + signal mulacc2_alu_output_r_1_0_22: std_logic; + signal mulacc2_alu_output_r_1_0_21: std_logic; + signal mulacc2_alu_output_r_1_0_20: std_logic; + signal mulacc2_alu_output_r_1_0_19: std_logic; + signal mulacc2_alu_output_r_1_0_18: std_logic; + signal mulacc2_alu_output_r_1_0_17: std_logic; + signal mulacc2_alu_output_r_1_0_16: std_logic; + signal mulacc2_alu_output_r_1_0_15: std_logic; + signal mulacc2_alu_output_r_1_0_14: std_logic; + signal mulacc2_alu_output_r_1_0_13: std_logic; + signal mulacc2_alu_output_r_1_0_12: std_logic; + signal mulacc2_alu_output_r_1_0_11: std_logic; + signal mulacc2_alu_output_r_1_0_10: std_logic; + signal mulacc2_alu_output_r_1_0_9: std_logic; + signal mulacc2_alu_output_r_1_0_8: std_logic; + signal mulacc2_alu_output_r_1_0_7: std_logic; + signal mulacc2_alu_output_r_1_0_6: std_logic; + signal mulacc2_alu_output_r_1_0_5: std_logic; + signal mulacc2_alu_output_r_1_0_4: std_logic; + signal mulacc2_alu_output_r_1_0_3: std_logic; + signal mulacc2_alu_output_r_1_0_2: std_logic; + signal mulacc2_alu_output_r_1_0_1: std_logic; + signal mulacc2_alu_output_r_1_0_0: std_logic; + signal mulacc2_alu_signedcin_1_0: std_logic; + signal mulacc2_alu_in_cin_1_0_53: std_logic; + signal mulacc2_alu_in_cin_1_0_52: std_logic; + signal mulacc2_alu_in_cin_1_0_51: std_logic; + signal mulacc2_alu_in_cin_1_0_50: std_logic; + signal mulacc2_alu_in_cin_1_0_49: std_logic; + signal mulacc2_alu_in_cin_1_0_48: std_logic; + signal mulacc2_alu_in_cin_1_0_47: std_logic; + signal mulacc2_alu_in_cin_1_0_46: std_logic; + signal mulacc2_alu_in_cin_1_0_45: std_logic; + signal mulacc2_alu_in_cin_1_0_44: std_logic; + signal mulacc2_alu_in_cin_1_0_43: std_logic; + signal mulacc2_alu_in_cin_1_0_42: std_logic; + signal mulacc2_alu_in_cin_1_0_41: std_logic; + signal mulacc2_alu_in_cin_1_0_40: std_logic; + signal mulacc2_alu_in_cin_1_0_39: std_logic; + signal mulacc2_alu_in_cin_1_0_38: std_logic; + signal mulacc2_alu_in_cin_1_0_37: std_logic; + signal mulacc2_alu_in_cin_1_0_36: std_logic; + signal mulacc2_alu_in_cin_1_0_35: std_logic; + signal mulacc2_alu_in_cin_1_0_34: std_logic; + signal mulacc2_alu_in_cin_1_0_33: std_logic; + signal mulacc2_alu_in_cin_1_0_32: std_logic; + signal mulacc2_alu_in_cin_1_0_31: std_logic; + signal mulacc2_alu_in_cin_1_0_30: std_logic; + signal mulacc2_alu_in_cin_1_0_29: std_logic; + signal mulacc2_alu_in_cin_1_0_28: std_logic; + signal mulacc2_alu_in_cin_1_0_27: std_logic; + signal mulacc2_alu_in_cin_1_0_26: std_logic; + signal mulacc2_alu_in_cin_1_0_25: std_logic; + signal mulacc2_alu_in_cin_1_0_24: std_logic; + signal mulacc2_alu_in_cin_1_0_23: std_logic; + signal mulacc2_alu_in_cin_1_0_22: std_logic; + signal mulacc2_alu_in_cin_1_0_21: std_logic; + signal mulacc2_alu_in_cin_1_0_20: std_logic; + signal mulacc2_alu_in_cin_1_0_19: std_logic; + signal mulacc2_alu_in_cin_1_0_18: std_logic; + signal mulacc2_alu_in_cin_1_0_17: std_logic; + signal mulacc2_alu_in_cin_1_0_16: std_logic; + signal mulacc2_alu_in_cin_1_0_15: std_logic; + signal mulacc2_alu_in_cin_1_0_14: std_logic; + signal mulacc2_alu_in_cin_1_0_13: std_logic; + signal mulacc2_alu_in_cin_1_0_12: std_logic; + signal mulacc2_alu_in_cin_1_0_11: std_logic; + signal mulacc2_alu_in_cin_1_0_10: std_logic; + signal mulacc2_alu_in_cin_1_0_9: std_logic; + signal mulacc2_alu_in_cin_1_0_8: std_logic; + signal mulacc2_alu_in_cin_1_0_7: std_logic; + signal mulacc2_alu_in_cin_1_0_6: std_logic; + signal mulacc2_alu_in_cin_1_0_5: std_logic; + signal mulacc2_alu_in_cin_1_0_4: std_logic; + signal mulacc2_alu_in_cin_1_0_3: std_logic; + signal mulacc2_alu_in_cin_1_0_2: std_logic; + signal mulacc2_alu_in_cin_1_0_1: std_logic; + signal mulacc2_alu_in_cin_1_0_0: std_logic; + signal mulacc2_0_mult_out_rob_0_17: std_logic; + signal mulacc2_0_mult_out_roa_0_17: std_logic; + signal mulacc2_0_mult_out_rob_0_16: std_logic; + signal mulacc2_0_mult_out_roa_0_16: std_logic; + signal mulacc2_0_mult_out_rob_0_15: std_logic; + signal mulacc2_0_mult_out_roa_0_15: std_logic; + signal mulacc2_0_mult_out_rob_0_14: std_logic; + signal mulacc2_0_mult_out_roa_0_14: std_logic; + signal mulacc2_0_mult_out_rob_0_13: std_logic; + signal mulacc2_0_mult_out_roa_0_13: std_logic; + signal mulacc2_0_mult_out_rob_0_12: std_logic; + signal mulacc2_0_mult_out_roa_0_12: std_logic; + signal mulacc2_0_mult_out_rob_0_11: std_logic; + signal mulacc2_0_mult_out_roa_0_11: std_logic; + signal mulacc2_0_mult_out_rob_0_10: std_logic; + signal mulacc2_0_mult_out_roa_0_10: std_logic; + signal mulacc2_0_mult_out_rob_0_9: std_logic; + signal mulacc2_0_mult_out_roa_0_9: std_logic; + signal mulacc2_0_mult_out_rob_0_8: std_logic; + signal mulacc2_0_mult_out_roa_0_8: std_logic; + signal mulacc2_0_mult_out_rob_0_7: std_logic; + signal mulacc2_0_mult_out_roa_0_7: std_logic; + signal mulacc2_0_mult_out_rob_0_6: std_logic; + signal mulacc2_0_mult_out_roa_0_6: std_logic; + signal mulacc2_0_mult_out_rob_0_5: std_logic; + signal mulacc2_0_mult_out_roa_0_5: std_logic; + signal mulacc2_0_mult_out_rob_0_4: std_logic; + signal mulacc2_0_mult_out_roa_0_4: std_logic; + signal mulacc2_0_mult_out_rob_0_3: std_logic; + signal mulacc2_0_mult_out_roa_0_3: std_logic; + signal mulacc2_0_mult_out_rob_0_2: std_logic; + signal mulacc2_0_mult_out_roa_0_2: std_logic; + signal mulacc2_0_mult_out_rob_0_1: std_logic; + signal mulacc2_0_mult_out_roa_0_1: std_logic; + signal mulacc2_0_mult_out_rob_0_0: std_logic; + signal mulacc2_0_mult_out_roa_0_0: std_logic; + signal mulacc2_0_mult_out_p_0_35: std_logic; + signal mulacc2_0_mult_out_p_0_34: std_logic; + signal mulacc2_0_mult_out_p_0_33: std_logic; + signal mulacc2_0_mult_out_p_0_32: std_logic; + signal mulacc2_0_mult_out_p_0_31: std_logic; + signal mulacc2_0_mult_out_p_0_30: std_logic; + signal mulacc2_0_mult_out_p_0_29: std_logic; + signal mulacc2_0_mult_out_p_0_28: std_logic; + signal mulacc2_0_mult_out_p_0_27: std_logic; + signal mulacc2_0_mult_out_p_0_26: std_logic; + signal mulacc2_0_mult_out_p_0_25: std_logic; + signal mulacc2_0_mult_out_p_0_24: std_logic; + signal mulacc2_0_mult_out_p_0_23: std_logic; + signal mulacc2_0_mult_out_p_0_22: std_logic; + signal mulacc2_0_mult_out_p_0_21: std_logic; + signal mulacc2_0_mult_out_p_0_20: std_logic; + signal mulacc2_0_mult_out_p_0_19: std_logic; + signal mulacc2_0_mult_out_p_0_18: std_logic; + signal mulacc2_0_mult_out_p_0_17: std_logic; + signal mulacc2_0_mult_out_p_0_16: std_logic; + signal mulacc2_0_mult_out_p_0_15: std_logic; + signal mulacc2_0_mult_out_p_0_14: std_logic; + signal mulacc2_0_mult_out_p_0_13: std_logic; + signal mulacc2_0_mult_out_p_0_12: std_logic; + signal mulacc2_0_mult_out_p_0_11: std_logic; + signal mulacc2_0_mult_out_p_0_10: std_logic; + signal mulacc2_0_mult_out_p_0_9: std_logic; + signal mulacc2_0_mult_out_p_0_8: std_logic; + signal mulacc2_0_mult_out_p_0_7: std_logic; + signal mulacc2_0_mult_out_p_0_6: std_logic; + signal mulacc2_0_mult_out_p_0_5: std_logic; + signal mulacc2_0_mult_out_p_0_4: std_logic; + signal mulacc2_0_mult_out_p_0_3: std_logic; + signal mulacc2_0_mult_out_p_0_2: std_logic; + signal mulacc2_0_mult_out_p_0_1: std_logic; + signal mulacc2_0_mult_out_p_0_0: std_logic; + signal mulacc2_0_mult_out_signedp_0: std_logic; + signal mulacc2_0_mult_out_rob_1_17: std_logic; + signal mulacc2_0_mult_out_roa_1_17: std_logic; + signal mulacc2_0_mult_out_rob_1_16: std_logic; + signal mulacc2_0_mult_out_roa_1_16: std_logic; + signal mulacc2_0_mult_out_rob_1_15: std_logic; + signal mulacc2_0_mult_out_roa_1_15: std_logic; + signal mulacc2_0_mult_out_rob_1_14: std_logic; + signal mulacc2_0_mult_out_roa_1_14: std_logic; + signal mulacc2_0_mult_out_rob_1_13: std_logic; + signal mulacc2_0_mult_out_roa_1_13: std_logic; + signal mulacc2_0_mult_out_rob_1_12: std_logic; + signal mulacc2_0_mult_out_roa_1_12: std_logic; + signal mulacc2_0_mult_out_rob_1_11: std_logic; + signal mulacc2_0_mult_out_roa_1_11: std_logic; + signal mulacc2_0_mult_out_rob_1_10: std_logic; + signal mulacc2_0_mult_out_roa_1_10: std_logic; + signal mulacc2_0_mult_out_rob_1_9: std_logic; + signal mulacc2_0_mult_out_roa_1_9: std_logic; + signal mulacc2_0_mult_out_rob_1_8: std_logic; + signal mulacc2_0_mult_out_roa_1_8: std_logic; + signal mulacc2_0_mult_out_rob_1_7: std_logic; + signal mulacc2_0_mult_out_roa_1_7: std_logic; + signal mulacc2_0_mult_out_rob_1_6: std_logic; + signal mulacc2_0_mult_out_roa_1_6: std_logic; + signal mulacc2_0_mult_out_rob_1_5: std_logic; + signal mulacc2_0_mult_out_roa_1_5: std_logic; + signal mulacc2_0_mult_out_rob_1_4: std_logic; + signal mulacc2_0_mult_out_roa_1_4: std_logic; + signal mulacc2_0_mult_out_rob_1_3: std_logic; + signal mulacc2_0_mult_out_roa_1_3: std_logic; + signal mulacc2_0_mult_out_rob_1_2: std_logic; + signal mulacc2_0_mult_out_roa_1_2: std_logic; + signal mulacc2_0_mult_out_rob_1_1: std_logic; + signal mulacc2_0_mult_out_roa_1_1: std_logic; + signal mulacc2_0_mult_out_rob_1_0: std_logic; + signal mulacc2_0_mult_out_roa_1_0: std_logic; + signal mulacc2_0_mult_out_p_1_35: std_logic; + signal mulacc2_0_mult_out_p_1_34: std_logic; + signal mulacc2_0_mult_out_p_1_33: std_logic; + signal mulacc2_0_mult_out_p_1_32: std_logic; + signal mulacc2_0_mult_out_p_1_31: std_logic; + signal mulacc2_0_mult_out_p_1_30: std_logic; + signal mulacc2_0_mult_out_p_1_29: std_logic; + signal mulacc2_0_mult_out_p_1_28: std_logic; + signal mulacc2_0_mult_out_p_1_27: std_logic; + signal mulacc2_0_mult_out_p_1_26: std_logic; + signal mulacc2_0_mult_out_p_1_25: std_logic; + signal mulacc2_0_mult_out_p_1_24: std_logic; + signal mulacc2_0_mult_out_p_1_23: std_logic; + signal mulacc2_0_mult_out_p_1_22: std_logic; + signal mulacc2_0_mult_out_p_1_21: std_logic; + signal mulacc2_0_mult_out_p_1_20: std_logic; + signal mulacc2_0_mult_out_p_1_19: std_logic; + signal mulacc2_0_mult_out_p_1_18: std_logic; + signal mulacc2_0_mult_out_p_1_17: std_logic; + signal mulacc2_0_mult_out_p_1_16: std_logic; + signal mulacc2_0_mult_out_p_1_15: std_logic; + signal mulacc2_0_mult_out_p_1_14: std_logic; + signal mulacc2_0_mult_out_p_1_13: std_logic; + signal mulacc2_0_mult_out_p_1_12: std_logic; + signal mulacc2_0_mult_out_p_1_11: std_logic; + signal mulacc2_0_mult_out_p_1_10: std_logic; + signal mulacc2_0_mult_out_p_1_9: std_logic; + signal mulacc2_0_mult_out_p_1_8: std_logic; + signal mulacc2_0_mult_out_p_1_7: std_logic; + signal mulacc2_0_mult_out_p_1_6: std_logic; + signal mulacc2_0_mult_out_p_1_5: std_logic; + signal mulacc2_0_mult_out_p_1_4: std_logic; + signal mulacc2_0_mult_out_p_1_3: std_logic; + signal mulacc2_0_mult_out_p_1_2: std_logic; + signal mulacc2_0_mult_out_p_1_1: std_logic; + signal mulacc2_0_mult_out_p_1_0: std_logic; + signal mulacc2_0_mult_out_signedp_1: std_logic; + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component MULT18X18C + generic (RESETMODE : in String; GSR : in String; + MULT_BYPASS : in String; CAS_MATCH_REG : in String; + REG_OUTPUT_RST : in String; REG_OUTPUT_CE : in String; + REG_OUTPUT_CLK : in String; REG_PIPELINE_RST : in String; + REG_PIPELINE_CE : in String; + REG_PIPELINE_CLK : in String; REG_INPUTB_RST : in String; + REG_INPUTB_CE : in String; REG_INPUTB_CLK : in String; + REG_INPUTA_RST : in String; REG_INPUTA_CE : in String; + REG_INPUTA_CLK : in String); + port (A17: in std_logic; A16: in std_logic; A15: in std_logic; + A14: in std_logic; A13: in std_logic; A12: in std_logic; + A11: in std_logic; A10: in std_logic; A9: in std_logic; + A8: in std_logic; A7: in std_logic; A6: in std_logic; + A5: in std_logic; A4: in std_logic; A3: in std_logic; + A2: in std_logic; A1: in std_logic; A0: in std_logic; + B17: in std_logic; B16: in std_logic; B15: in std_logic; + B14: in std_logic; B13: in std_logic; B12: in std_logic; + B11: in std_logic; B10: in std_logic; B9: in std_logic; + B8: in std_logic; B7: in std_logic; B6: in std_logic; + B5: in std_logic; B4: in std_logic; B3: in std_logic; + B2: in std_logic; B1: in std_logic; B0: in std_logic; + SIGNEDA: in std_logic; SIGNEDB: in std_logic; + SOURCEA: in std_logic; SOURCEB: in std_logic; + CE0: in std_logic; CE1: in std_logic; CE2: in std_logic; + CE3: in std_logic; CLK0: in std_logic; CLK1: in std_logic; + CLK2: in std_logic; CLK3: in std_logic; + RST0: in std_logic; RST1: in std_logic; + RST2: in std_logic; RST3: in std_logic; + SRIA17: in std_logic; SRIA16: in std_logic; + SRIA15: in std_logic; SRIA14: in std_logic; + SRIA13: in std_logic; SRIA12: in std_logic; + SRIA11: in std_logic; SRIA10: in std_logic; + SRIA9: in std_logic; SRIA8: in std_logic; + SRIA7: in std_logic; SRIA6: in std_logic; + SRIA5: in std_logic; SRIA4: in std_logic; + SRIA3: in std_logic; SRIA2: in std_logic; + SRIA1: in std_logic; SRIA0: in std_logic; + SRIB17: in std_logic; SRIB16: in std_logic; + SRIB15: in std_logic; SRIB14: in std_logic; + SRIB13: in std_logic; SRIB12: in std_logic; + SRIB11: in std_logic; SRIB10: in std_logic; + SRIB9: in std_logic; SRIB8: in std_logic; + SRIB7: in std_logic; SRIB6: in std_logic; + SRIB5: in std_logic; SRIB4: in std_logic; + SRIB3: in std_logic; SRIB2: in std_logic; + SRIB1: in std_logic; SRIB0: in std_logic; + SROA17: out std_logic; SROA16: out std_logic; + SROA15: out std_logic; SROA14: out std_logic; + SROA13: out std_logic; SROA12: out std_logic; + SROA11: out std_logic; SROA10: out std_logic; + SROA9: out std_logic; SROA8: out std_logic; + SROA7: out std_logic; SROA6: out std_logic; + SROA5: out std_logic; SROA4: out std_logic; + SROA3: out std_logic; SROA2: out std_logic; + SROA1: out std_logic; SROA0: out std_logic; + SROB17: out std_logic; SROB16: out std_logic; + SROB15: out std_logic; SROB14: out std_logic; + SROB13: out std_logic; SROB12: out std_logic; + SROB11: out std_logic; SROB10: out std_logic; + SROB9: out std_logic; SROB8: out std_logic; + SROB7: out std_logic; SROB6: out std_logic; + SROB5: out std_logic; SROB4: out std_logic; + SROB3: out std_logic; SROB2: out std_logic; + SROB1: out std_logic; SROB0: out std_logic; + ROA17: out std_logic; ROA16: out std_logic; + ROA15: out std_logic; ROA14: out std_logic; + ROA13: out std_logic; ROA12: out std_logic; + ROA11: out std_logic; ROA10: out std_logic; + ROA9: out std_logic; ROA8: out std_logic; + ROA7: out std_logic; ROA6: out std_logic; + ROA5: out std_logic; ROA4: out std_logic; + ROA3: out std_logic; ROA2: out std_logic; + ROA1: out std_logic; ROA0: out std_logic; + ROB17: out std_logic; ROB16: out std_logic; + ROB15: out std_logic; ROB14: out std_logic; + ROB13: out std_logic; ROB12: out std_logic; + ROB11: out std_logic; ROB10: out std_logic; + ROB9: out std_logic; ROB8: out std_logic; + ROB7: out std_logic; ROB6: out std_logic; + ROB5: out std_logic; ROB4: out std_logic; + ROB3: out std_logic; ROB2: out std_logic; + ROB1: out std_logic; ROB0: out std_logic; + P35: out std_logic; P34: out std_logic; + P33: out std_logic; P32: out std_logic; + P31: out std_logic; P30: out std_logic; + P29: out std_logic; P28: out std_logic; + P27: out std_logic; P26: out std_logic; + P25: out std_logic; P24: out std_logic; + P23: out std_logic; P22: out std_logic; + P21: out std_logic; P20: out std_logic; + P19: out std_logic; P18: out std_logic; + P17: out std_logic; P16: out std_logic; + P15: out std_logic; P14: out std_logic; + P13: out std_logic; P12: out std_logic; + P11: out std_logic; P10: out std_logic; P9: out std_logic; + P8: out std_logic; P7: out std_logic; P6: out std_logic; + P5: out std_logic; P4: out std_logic; P3: out std_logic; + P2: out std_logic; P1: out std_logic; P0: out std_logic; + SIGNEDP: out std_logic); + end component; + component ALU54A + generic (LEGACY : in String; MULT9_MODE : in String; + RESETMODE : in String; GSR : in String; + RNDPAT : in String; MASKPAT : in String; + MCPAT : in String; MASK01 : in String; + MASKPAT_SOURCE : in String; MCPAT_SOURCE : in String; + REG_FLAG_RST : in String; REG_FLAG_CE : in String; + REG_FLAG_CLK : in String; REG_OUTPUT1_RST : in String; + REG_OUTPUT1_CE : in String; REG_OUTPUT1_CLK : in String; + REG_OUTPUT0_RST : in String; REG_OUTPUT0_CE : in String; + REG_OUTPUT0_CLK : in String; + REG_OPCODEIN_1_RST : in String; + REG_OPCODEIN_1_CE : in String; + REG_OPCODEIN_1_CLK : in String; + REG_OPCODEIN_0_RST : in String; + REG_OPCODEIN_0_CE : in String; + REG_OPCODEIN_0_CLK : in String; + REG_OPCODEOP1_1_CLK : in String; + REG_OPCODEOP1_0_CLK : in String; + REG_OPCODEOP0_1_RST : in String; + REG_OPCODEOP0_1_CE : in String; + REG_OPCODEOP0_1_CLK : in String; + REG_OPCODEOP0_0_RST : in String; + REG_OPCODEOP0_0_CE : in String; + REG_OPCODEOP0_0_CLK : in String; + REG_INPUTC1_RST : in String; REG_INPUTC1_CE : in String; + REG_INPUTC1_CLK : in String; REG_INPUTC0_RST : in String; + REG_INPUTC0_CE : in String; REG_INPUTC0_CLK : in String); + port (CE0: in std_logic; CE1: in std_logic; CE2: in std_logic; + CE3: in std_logic; CLK0: in std_logic; CLK1: in std_logic; + CLK2: in std_logic; CLK3: in std_logic; + RST0: in std_logic; RST1: in std_logic; + RST2: in std_logic; RST3: in std_logic; + SIGNEDIA: in std_logic; SIGNEDIB: in std_logic; + A35: in std_logic; A34: in std_logic; A33: in std_logic; + A32: in std_logic; A31: in std_logic; A30: in std_logic; + A29: in std_logic; A28: in std_logic; A27: in std_logic; + A26: in std_logic; A25: in std_logic; A24: in std_logic; + A23: in std_logic; A22: in std_logic; A21: in std_logic; + A20: in std_logic; A19: in std_logic; A18: in std_logic; + A17: in std_logic; A16: in std_logic; A15: in std_logic; + A14: in std_logic; A13: in std_logic; A12: in std_logic; + A11: in std_logic; A10: in std_logic; A9: in std_logic; + A8: in std_logic; A7: in std_logic; A6: in std_logic; + A5: in std_logic; A4: in std_logic; A3: in std_logic; + A2: in std_logic; A1: in std_logic; A0: in std_logic; + B35: in std_logic; B34: in std_logic; B33: in std_logic; + B32: in std_logic; B31: in std_logic; B30: in std_logic; + B29: in std_logic; B28: in std_logic; B27: in std_logic; + B26: in std_logic; B25: in std_logic; B24: in std_logic; + B23: in std_logic; B22: in std_logic; B21: in std_logic; + B20: in std_logic; B19: in std_logic; B18: in std_logic; + B17: in std_logic; B16: in std_logic; B15: in std_logic; + B14: in std_logic; B13: in std_logic; B12: in std_logic; + B11: in std_logic; B10: in std_logic; B9: in std_logic; + B8: in std_logic; B7: in std_logic; B6: in std_logic; + B5: in std_logic; B4: in std_logic; B3: in std_logic; + B2: in std_logic; B1: in std_logic; B0: in std_logic; + C53: in std_logic; C52: in std_logic; C51: in std_logic; + C50: in std_logic; C49: in std_logic; C48: in std_logic; + C47: in std_logic; C46: in std_logic; C45: in std_logic; + C44: in std_logic; C43: in std_logic; C42: in std_logic; + C41: in std_logic; C40: in std_logic; C39: in std_logic; + C38: in std_logic; C37: in std_logic; C36: in std_logic; + C35: in std_logic; C34: in std_logic; C33: in std_logic; + C32: in std_logic; C31: in std_logic; C30: in std_logic; + C29: in std_logic; C28: in std_logic; C27: in std_logic; + C26: in std_logic; C25: in std_logic; C24: in std_logic; + C23: in std_logic; C22: in std_logic; C21: in std_logic; + C20: in std_logic; C19: in std_logic; C18: in std_logic; + C17: in std_logic; C16: in std_logic; C15: in std_logic; + C14: in std_logic; C13: in std_logic; C12: in std_logic; + C11: in std_logic; C10: in std_logic; C9: in std_logic; + C8: in std_logic; C7: in std_logic; C6: in std_logic; + C5: in std_logic; C4: in std_logic; C3: in std_logic; + C2: in std_logic; C1: in std_logic; C0: in std_logic; + MA35: in std_logic; MA34: in std_logic; + MA33: in std_logic; MA32: in std_logic; + MA31: in std_logic; MA30: in std_logic; + MA29: in std_logic; MA28: in std_logic; + MA27: in std_logic; MA26: in std_logic; + MA25: in std_logic; MA24: in std_logic; + MA23: in std_logic; MA22: in std_logic; + MA21: in std_logic; MA20: in std_logic; + MA19: in std_logic; MA18: in std_logic; + MA17: in std_logic; MA16: in std_logic; + MA15: in std_logic; MA14: in std_logic; + MA13: in std_logic; MA12: in std_logic; + MA11: in std_logic; MA10: in std_logic; MA9: in std_logic; + MA8: in std_logic; MA7: in std_logic; MA6: in std_logic; + MA5: in std_logic; MA4: in std_logic; MA3: in std_logic; + MA2: in std_logic; MA1: in std_logic; MA0: in std_logic; + MB35: in std_logic; MB34: in std_logic; + MB33: in std_logic; MB32: in std_logic; + MB31: in std_logic; MB30: in std_logic; + MB29: in std_logic; MB28: in std_logic; + MB27: in std_logic; MB26: in std_logic; + MB25: in std_logic; MB24: in std_logic; + MB23: in std_logic; MB22: in std_logic; + MB21: in std_logic; MB20: in std_logic; + MB19: in std_logic; MB18: in std_logic; + MB17: in std_logic; MB16: in std_logic; + MB15: in std_logic; MB14: in std_logic; + MB13: in std_logic; MB12: in std_logic; + MB11: in std_logic; MB10: in std_logic; MB9: in std_logic; + MB8: in std_logic; MB7: in std_logic; MB6: in std_logic; + MB5: in std_logic; MB4: in std_logic; MB3: in std_logic; + MB2: in std_logic; MB1: in std_logic; MB0: in std_logic; + CIN53: in std_logic; CIN52: in std_logic; + CIN51: in std_logic; CIN50: in std_logic; + CIN49: in std_logic; CIN48: in std_logic; + CIN47: in std_logic; CIN46: in std_logic; + CIN45: in std_logic; CIN44: in std_logic; + CIN43: in std_logic; CIN42: in std_logic; + CIN41: in std_logic; CIN40: in std_logic; + CIN39: in std_logic; CIN38: in std_logic; + CIN37: in std_logic; CIN36: in std_logic; + CIN35: in std_logic; CIN34: in std_logic; + CIN33: in std_logic; CIN32: in std_logic; + CIN31: in std_logic; CIN30: in std_logic; + CIN29: in std_logic; CIN28: in std_logic; + CIN27: in std_logic; CIN26: in std_logic; + CIN25: in std_logic; CIN24: in std_logic; + CIN23: in std_logic; CIN22: in std_logic; + CIN21: in std_logic; CIN20: in std_logic; + CIN19: in std_logic; CIN18: in std_logic; + CIN17: in std_logic; CIN16: in std_logic; + CIN15: in std_logic; CIN14: in std_logic; + CIN13: in std_logic; CIN12: in std_logic; + CIN11: in std_logic; CIN10: in std_logic; + CIN9: in std_logic; CIN8: in std_logic; + CIN7: in std_logic; CIN6: in std_logic; + CIN5: in std_logic; CIN4: in std_logic; + CIN3: in std_logic; CIN2: in std_logic; + CIN1: in std_logic; CIN0: in std_logic; + SIGNEDCIN: in std_logic; OP10: in std_logic; + OP9: in std_logic; OP8: in std_logic; OP7: in std_logic; + OP6: in std_logic; OP5: in std_logic; OP4: in std_logic; + OP3: in std_logic; OP2: in std_logic; OP1: in std_logic; + OP0: in std_logic; R53: out std_logic; R52: out std_logic; + R51: out std_logic; R50: out std_logic; + R49: out std_logic; R48: out std_logic; + R47: out std_logic; R46: out std_logic; + R45: out std_logic; R44: out std_logic; + R43: out std_logic; R42: out std_logic; + R41: out std_logic; R40: out std_logic; + R39: out std_logic; R38: out std_logic; + R37: out std_logic; R36: out std_logic; + R35: out std_logic; R34: out std_logic; + R33: out std_logic; R32: out std_logic; + R31: out std_logic; R30: out std_logic; + R29: out std_logic; R28: out std_logic; + R27: out std_logic; R26: out std_logic; + R25: out std_logic; R24: out std_logic; + R23: out std_logic; R22: out std_logic; + R21: out std_logic; R20: out std_logic; + R19: out std_logic; R18: out std_logic; + R17: out std_logic; R16: out std_logic; + R15: out std_logic; R14: out std_logic; + R13: out std_logic; R12: out std_logic; + R11: out std_logic; R10: out std_logic; R9: out std_logic; + R8: out std_logic; R7: out std_logic; R6: out std_logic; + R5: out std_logic; R4: out std_logic; R3: out std_logic; + R2: out std_logic; R1: out std_logic; R0: out std_logic; + EQZ: out std_logic; EQZM: out std_logic; + EQOM: out std_logic; EQPAT: out std_logic; + EQPATB: out std_logic; OVER: out std_logic; + UNDER: out std_logic; OVERUNDER: out std_logic; + SIGNEDR: out std_logic); + end component; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + INV_0: INV + port map (A=>scuba_vhi, Z=>high_inv); + + dsp_alu_0: ALU54A + generic map (REG_OPCODEIN_1_RST=> "RST0", REG_OPCODEIN_1_CE=> "CE0", + REG_OPCODEIN_1_CLK=> "NONE", REG_OPCODEIN_0_RST=> "RST0", + REG_OPCODEIN_0_CE=> "CE0", REG_OPCODEIN_0_CLK=> "NONE", + REG_OPCODEOP1_1_CLK=> "NONE", REG_OPCODEOP1_0_CLK=> "NONE", + REG_OPCODEOP0_1_RST=> "RST0", REG_OPCODEOP0_1_CE=> "CE0", + REG_OPCODEOP0_1_CLK=> "NONE", REG_OPCODEOP0_0_RST=> "RST0", + REG_OPCODEOP0_0_CE=> "CE0", REG_OPCODEOP0_0_CLK=> "NONE", + REG_INPUTC1_RST=> "RST0", REG_INPUTC1_CE=> "CE0", + REG_INPUTC1_CLK=> "NONE", REG_INPUTC0_RST=> "RST0", + REG_INPUTC0_CE=> "CE0", REG_INPUTC0_CLK=> "NONE", LEGACY=> "ENABLED", + REG_FLAG_RST=> "RST0", REG_FLAG_CE=> "CE0", REG_FLAG_CLK=> "CLK0", + REG_OUTPUT1_RST=> "RST0", REG_OUTPUT1_CE=> "CE0", + REG_OUTPUT1_CLK=> "CLK0", REG_OUTPUT0_RST=> "RST0", + REG_OUTPUT0_CE=> "CE0", REG_OUTPUT0_CLK=> "CLK0", MULT9_MODE=> "DISABLED", + RNDPAT=> "0x00000000000000", MASKPAT=> "0x00000000000000", MCPAT=> "0x00000000000000", + MASK01=> "0x27FFFFFFFFFFFF", MASKPAT_SOURCE=> "STATIC", + MCPAT_SOURCE=> "STATIC", RESETMODE=> "SYNC", GSR=> "ENABLED") + port map (CE0=>CE0, CE1=>scuba_vhi, CE2=>scuba_vhi, + CE3=>scuba_vhi, CLK0=>CLK0, CLK1=>scuba_vlo, CLK2=>scuba_vlo, + CLK3=>scuba_vlo, RST0=>RST0, RST1=>scuba_vlo, + RST2=>scuba_vlo, RST3=>scuba_vlo, + SIGNEDIA=>mulacc2_0_mult_out_signedp_0, + SIGNEDIB=>mulacc2_0_mult_out_signedp_1, + A35=>mulacc2_0_mult_out_rob_0_17, + A34=>mulacc2_0_mult_out_rob_0_16, + A33=>mulacc2_0_mult_out_rob_0_15, + A32=>mulacc2_0_mult_out_rob_0_14, + A31=>mulacc2_0_mult_out_rob_0_13, + A30=>mulacc2_0_mult_out_rob_0_12, + A29=>mulacc2_0_mult_out_rob_0_11, + A28=>mulacc2_0_mult_out_rob_0_10, + A27=>mulacc2_0_mult_out_rob_0_9, + A26=>mulacc2_0_mult_out_rob_0_8, + A25=>mulacc2_0_mult_out_rob_0_7, + A24=>mulacc2_0_mult_out_rob_0_6, + A23=>mulacc2_0_mult_out_rob_0_5, + A22=>mulacc2_0_mult_out_rob_0_4, + A21=>mulacc2_0_mult_out_rob_0_3, + A20=>mulacc2_0_mult_out_rob_0_2, + A19=>mulacc2_0_mult_out_rob_0_1, + A18=>mulacc2_0_mult_out_rob_0_0, + A17=>mulacc2_0_mult_out_roa_0_17, + A16=>mulacc2_0_mult_out_roa_0_16, + A15=>mulacc2_0_mult_out_roa_0_15, + A14=>mulacc2_0_mult_out_roa_0_14, + A13=>mulacc2_0_mult_out_roa_0_13, + A12=>mulacc2_0_mult_out_roa_0_12, + A11=>mulacc2_0_mult_out_roa_0_11, + A10=>mulacc2_0_mult_out_roa_0_10, + A9=>mulacc2_0_mult_out_roa_0_9, + A8=>mulacc2_0_mult_out_roa_0_8, + A7=>mulacc2_0_mult_out_roa_0_7, + A6=>mulacc2_0_mult_out_roa_0_6, + A5=>mulacc2_0_mult_out_roa_0_5, + A4=>mulacc2_0_mult_out_roa_0_4, + A3=>mulacc2_0_mult_out_roa_0_3, + A2=>mulacc2_0_mult_out_roa_0_2, + A1=>mulacc2_0_mult_out_roa_0_1, + A0=>mulacc2_0_mult_out_roa_0_0, + B35=>mulacc2_0_mult_out_rob_1_17, + B34=>mulacc2_0_mult_out_rob_1_16, + B33=>mulacc2_0_mult_out_rob_1_15, + B32=>mulacc2_0_mult_out_rob_1_14, + B31=>mulacc2_0_mult_out_rob_1_13, + B30=>mulacc2_0_mult_out_rob_1_12, + B29=>mulacc2_0_mult_out_rob_1_11, + B28=>mulacc2_0_mult_out_rob_1_10, + B27=>mulacc2_0_mult_out_rob_1_9, + B26=>mulacc2_0_mult_out_rob_1_8, + B25=>mulacc2_0_mult_out_rob_1_7, + B24=>mulacc2_0_mult_out_rob_1_6, + B23=>mulacc2_0_mult_out_rob_1_5, + B22=>mulacc2_0_mult_out_rob_1_4, + B21=>mulacc2_0_mult_out_rob_1_3, + B20=>mulacc2_0_mult_out_rob_1_2, + B19=>mulacc2_0_mult_out_rob_1_1, + B18=>mulacc2_0_mult_out_rob_1_0, + B17=>mulacc2_0_mult_out_roa_1_17, + B16=>mulacc2_0_mult_out_roa_1_16, + B15=>mulacc2_0_mult_out_roa_1_15, + B14=>mulacc2_0_mult_out_roa_1_14, + B13=>mulacc2_0_mult_out_roa_1_13, + B12=>mulacc2_0_mult_out_roa_1_12, + B11=>mulacc2_0_mult_out_roa_1_11, + B10=>mulacc2_0_mult_out_roa_1_10, + B9=>mulacc2_0_mult_out_roa_1_9, + B8=>mulacc2_0_mult_out_roa_1_8, + B7=>mulacc2_0_mult_out_roa_1_7, + B6=>mulacc2_0_mult_out_roa_1_6, + B5=>mulacc2_0_mult_out_roa_1_5, + B4=>mulacc2_0_mult_out_roa_1_4, + B3=>mulacc2_0_mult_out_roa_1_3, + B2=>mulacc2_0_mult_out_roa_1_2, + B1=>mulacc2_0_mult_out_roa_1_1, + B0=>mulacc2_0_mult_out_roa_1_0, C53=>scuba_vlo, + C52=>scuba_vlo, C51=>scuba_vlo, C50=>scuba_vlo, + C49=>scuba_vlo, C48=>scuba_vlo, C47=>scuba_vlo, + C46=>scuba_vlo, C45=>scuba_vlo, C44=>scuba_vlo, + C43=>scuba_vlo, C42=>scuba_vlo, C41=>scuba_vlo, + C40=>scuba_vlo, C39=>scuba_vlo, C38=>scuba_vlo, + C37=>scuba_vlo, C36=>scuba_vlo, C35=>scuba_vlo, + C34=>scuba_vlo, C33=>scuba_vlo, C32=>scuba_vlo, + C31=>scuba_vlo, C30=>scuba_vlo, C29=>scuba_vlo, + C28=>scuba_vlo, C27=>scuba_vlo, C26=>scuba_vlo, + C25=>scuba_vlo, C24=>scuba_vlo, C23=>scuba_vlo, + C22=>scuba_vlo, C21=>scuba_vlo, C20=>scuba_vlo, + C19=>scuba_vlo, C18=>scuba_vlo, C17=>LD(40), C16=>LD(40), + C15=>LD(40), C14=>LD(39), C13=>LD(38), C12=>LD(37), + C11=>LD(36), C10=>LD(35), C9=>LD(34), C8=>LD(33), C7=>LD(32), + C6=>LD(31), C5=>LD(30), C4=>LD(29), C3=>LD(28), C2=>LD(27), + C1=>LD(26), C0=>LD(25), MA35=>mulacc2_0_mult_out_p_0_35, + MA34=>mulacc2_0_mult_out_p_0_34, + MA33=>mulacc2_0_mult_out_p_0_33, + MA32=>mulacc2_0_mult_out_p_0_32, + MA31=>mulacc2_0_mult_out_p_0_31, + MA30=>mulacc2_0_mult_out_p_0_30, + MA29=>mulacc2_0_mult_out_p_0_29, + MA28=>mulacc2_0_mult_out_p_0_28, + MA27=>mulacc2_0_mult_out_p_0_27, + MA26=>mulacc2_0_mult_out_p_0_26, + MA25=>mulacc2_0_mult_out_p_0_25, + MA24=>mulacc2_0_mult_out_p_0_24, + MA23=>mulacc2_0_mult_out_p_0_23, + MA22=>mulacc2_0_mult_out_p_0_22, + MA21=>mulacc2_0_mult_out_p_0_21, + MA20=>mulacc2_0_mult_out_p_0_20, + MA19=>mulacc2_0_mult_out_p_0_19, + MA18=>mulacc2_0_mult_out_p_0_18, + MA17=>mulacc2_0_mult_out_p_0_17, + MA16=>mulacc2_0_mult_out_p_0_16, + MA15=>mulacc2_0_mult_out_p_0_15, + MA14=>mulacc2_0_mult_out_p_0_14, + MA13=>mulacc2_0_mult_out_p_0_13, + MA12=>mulacc2_0_mult_out_p_0_12, + MA11=>mulacc2_0_mult_out_p_0_11, + MA10=>mulacc2_0_mult_out_p_0_10, + MA9=>mulacc2_0_mult_out_p_0_9, MA8=>mulacc2_0_mult_out_p_0_8, + MA7=>mulacc2_0_mult_out_p_0_7, MA6=>mulacc2_0_mult_out_p_0_6, + MA5=>mulacc2_0_mult_out_p_0_5, MA4=>mulacc2_0_mult_out_p_0_4, + MA3=>mulacc2_0_mult_out_p_0_3, MA2=>mulacc2_0_mult_out_p_0_2, + MA1=>mulacc2_0_mult_out_p_0_1, MA0=>mulacc2_0_mult_out_p_0_0, + MB35=>mulacc2_0_mult_out_p_1_35, + MB34=>mulacc2_0_mult_out_p_1_34, + MB33=>mulacc2_0_mult_out_p_1_33, + MB32=>mulacc2_0_mult_out_p_1_32, + MB31=>mulacc2_0_mult_out_p_1_31, + MB30=>mulacc2_0_mult_out_p_1_30, + MB29=>mulacc2_0_mult_out_p_1_29, + MB28=>mulacc2_0_mult_out_p_1_28, + MB27=>mulacc2_0_mult_out_p_1_27, + MB26=>mulacc2_0_mult_out_p_1_26, + MB25=>mulacc2_0_mult_out_p_1_25, + MB24=>mulacc2_0_mult_out_p_1_24, + MB23=>mulacc2_0_mult_out_p_1_23, + MB22=>mulacc2_0_mult_out_p_1_22, + MB21=>mulacc2_0_mult_out_p_1_21, + MB20=>mulacc2_0_mult_out_p_1_20, + MB19=>mulacc2_0_mult_out_p_1_19, + MB18=>mulacc2_0_mult_out_p_1_18, + MB17=>mulacc2_0_mult_out_p_1_17, + MB16=>mulacc2_0_mult_out_p_1_16, + MB15=>mulacc2_0_mult_out_p_1_15, + MB14=>mulacc2_0_mult_out_p_1_14, + MB13=>mulacc2_0_mult_out_p_1_13, + MB12=>mulacc2_0_mult_out_p_1_12, + MB11=>mulacc2_0_mult_out_p_1_11, + MB10=>mulacc2_0_mult_out_p_1_10, + MB9=>mulacc2_0_mult_out_p_1_9, MB8=>mulacc2_0_mult_out_p_1_8, + MB7=>mulacc2_0_mult_out_p_1_7, MB6=>mulacc2_0_mult_out_p_1_6, + MB5=>mulacc2_0_mult_out_p_1_5, MB4=>mulacc2_0_mult_out_p_1_4, + MB3=>mulacc2_0_mult_out_p_1_3, MB2=>mulacc2_0_mult_out_p_1_2, + MB1=>mulacc2_0_mult_out_p_1_1, MB0=>mulacc2_0_mult_out_p_1_0, + CIN53=>mulacc2_alu_in_cin_1_0_53, + CIN52=>mulacc2_alu_in_cin_1_0_52, + CIN51=>mulacc2_alu_in_cin_1_0_51, + CIN50=>mulacc2_alu_in_cin_1_0_50, + CIN49=>mulacc2_alu_in_cin_1_0_49, + CIN48=>mulacc2_alu_in_cin_1_0_48, + CIN47=>mulacc2_alu_in_cin_1_0_47, + CIN46=>mulacc2_alu_in_cin_1_0_46, + CIN45=>mulacc2_alu_in_cin_1_0_45, + CIN44=>mulacc2_alu_in_cin_1_0_44, + CIN43=>mulacc2_alu_in_cin_1_0_43, + CIN42=>mulacc2_alu_in_cin_1_0_42, + CIN41=>mulacc2_alu_in_cin_1_0_41, + CIN40=>mulacc2_alu_in_cin_1_0_40, + CIN39=>mulacc2_alu_in_cin_1_0_39, + CIN38=>mulacc2_alu_in_cin_1_0_38, + CIN37=>mulacc2_alu_in_cin_1_0_37, + CIN36=>mulacc2_alu_in_cin_1_0_36, + CIN35=>mulacc2_alu_in_cin_1_0_35, + CIN34=>mulacc2_alu_in_cin_1_0_34, + CIN33=>mulacc2_alu_in_cin_1_0_33, + CIN32=>mulacc2_alu_in_cin_1_0_32, + CIN31=>mulacc2_alu_in_cin_1_0_31, + CIN30=>mulacc2_alu_in_cin_1_0_30, + CIN29=>mulacc2_alu_in_cin_1_0_29, + CIN28=>mulacc2_alu_in_cin_1_0_28, + CIN27=>mulacc2_alu_in_cin_1_0_27, + CIN26=>mulacc2_alu_in_cin_1_0_26, + CIN25=>mulacc2_alu_in_cin_1_0_25, + CIN24=>mulacc2_alu_in_cin_1_0_24, + CIN23=>mulacc2_alu_in_cin_1_0_23, + CIN22=>mulacc2_alu_in_cin_1_0_22, + CIN21=>mulacc2_alu_in_cin_1_0_21, + CIN20=>mulacc2_alu_in_cin_1_0_20, + CIN19=>mulacc2_alu_in_cin_1_0_19, + CIN18=>mulacc2_alu_in_cin_1_0_18, + CIN17=>mulacc2_alu_in_cin_1_0_17, + CIN16=>mulacc2_alu_in_cin_1_0_16, + CIN15=>mulacc2_alu_in_cin_1_0_15, + CIN14=>mulacc2_alu_in_cin_1_0_14, + CIN13=>mulacc2_alu_in_cin_1_0_13, + CIN12=>mulacc2_alu_in_cin_1_0_12, + CIN11=>mulacc2_alu_in_cin_1_0_11, + CIN10=>mulacc2_alu_in_cin_1_0_10, + CIN9=>mulacc2_alu_in_cin_1_0_9, + CIN8=>mulacc2_alu_in_cin_1_0_8, + CIN7=>mulacc2_alu_in_cin_1_0_7, + CIN6=>mulacc2_alu_in_cin_1_0_6, + CIN5=>mulacc2_alu_in_cin_1_0_5, + CIN4=>mulacc2_alu_in_cin_1_0_4, + CIN3=>mulacc2_alu_in_cin_1_0_3, + CIN2=>mulacc2_alu_in_cin_1_0_2, + CIN1=>mulacc2_alu_in_cin_1_0_1, + CIN0=>mulacc2_alu_in_cin_1_0_0, + SIGNEDCIN=>mulacc2_alu_signedcin_1_0, OP10=>scuba_vlo, + OP9=>scuba_vhi, OP8=>scuba_vlo, OP7=>scuba_vlo, + OP6=>scuba_vlo, OP5=>scuba_vlo, OP4=>scuba_vlo, + OP3=>scuba_vlo, OP2=>scuba_vhi, OP1=>ACCUMSLOAD, + OP0=>scuba_vlo, R53=>mulacc2_alu_output_r_1_0_53, + R52=>mulacc2_alu_output_r_1_0_52, + R51=>mulacc2_alu_output_r_1_0_51, + R50=>mulacc2_alu_output_r_1_0_50, + R49=>mulacc2_alu_output_r_1_0_49, + R48=>mulacc2_alu_output_r_1_0_48, + R47=>mulacc2_alu_output_r_1_0_47, + R46=>mulacc2_alu_output_r_1_0_46, + R45=>mulacc2_alu_output_r_1_0_45, + R44=>mulacc2_alu_output_r_1_0_44, + R43=>mulacc2_alu_output_r_1_0_43, + R42=>mulacc2_alu_output_r_1_0_42, + R41=>mulacc2_alu_output_r_1_0_41, + R40=>mulacc2_alu_output_r_1_0_40, + R39=>mulacc2_alu_output_r_1_0_39, + R38=>mulacc2_alu_output_r_1_0_38, + R37=>mulacc2_alu_output_r_1_0_37, + R36=>mulacc2_alu_output_r_1_0_36, + R35=>mulacc2_alu_output_r_1_0_35, + R34=>mulacc2_alu_output_r_1_0_34, + R33=>mulacc2_alu_output_r_1_0_33, + R32=>mulacc2_alu_output_r_1_0_32, + R31=>mulacc2_alu_output_r_1_0_31, + R30=>mulacc2_alu_output_r_1_0_30, + R29=>mulacc2_alu_output_r_1_0_29, + R28=>mulacc2_alu_output_r_1_0_28, + R27=>mulacc2_alu_output_r_1_0_27, + R26=>mulacc2_alu_output_r_1_0_26, + R25=>mulacc2_alu_output_r_1_0_25, + R24=>mulacc2_alu_output_r_1_0_24, + R23=>mulacc2_alu_output_r_1_0_23, + R22=>mulacc2_alu_output_r_1_0_22, + R21=>mulacc2_alu_output_r_1_0_21, + R20=>mulacc2_alu_output_r_1_0_20, + R19=>mulacc2_alu_output_r_1_0_19, + R18=>mulacc2_alu_output_r_1_0_18, + R17=>mulacc2_alu_output_r_1_0_17, + R16=>mulacc2_alu_output_r_1_0_16, + R15=>mulacc2_alu_output_r_1_0_15, + R14=>mulacc2_alu_output_r_1_0_14, + R13=>mulacc2_alu_output_r_1_0_13, + R12=>mulacc2_alu_output_r_1_0_12, + R11=>mulacc2_alu_output_r_1_0_11, + R10=>mulacc2_alu_output_r_1_0_10, + R9=>mulacc2_alu_output_r_1_0_9, + R8=>mulacc2_alu_output_r_1_0_8, + R7=>mulacc2_alu_output_r_1_0_7, + R6=>mulacc2_alu_output_r_1_0_6, + R5=>mulacc2_alu_output_r_1_0_5, + R4=>mulacc2_alu_output_r_1_0_4, + R3=>mulacc2_alu_output_r_1_0_3, + R2=>mulacc2_alu_output_r_1_0_2, + R1=>mulacc2_alu_output_r_1_0_1, + R0=>mulacc2_alu_output_r_1_0_0, EQZ=>open, EQZM=>open, + EQOM=>open, EQPAT=>open, EQPATB=>open, OVER=>open, + UNDER=>open, OVERUNDER=>OVERFLOW, + SIGNEDR=>mulacc2_alu_signedr_1_0); + + dsp_mult_1: MULT18X18C + generic map (MULT_BYPASS=> "ENABLED", CAS_MATCH_REG=> "FALSE", + RESETMODE=> "SYNC", GSR=> "ENABLED", REG_OUTPUT_RST=> "RST0", + REG_OUTPUT_CE=> "CE0", REG_OUTPUT_CLK=> "NONE", REG_PIPELINE_RST=> "RST0", + REG_PIPELINE_CE=> "CE0", REG_PIPELINE_CLK=> "NONE", + REG_INPUTB_RST=> "RST0", REG_INPUTB_CE=> "CE0", REG_INPUTB_CLK=> "NONE", + REG_INPUTA_RST=> "RST0", REG_INPUTA_CE=> "CE0", REG_INPUTA_CLK=> "NONE") + port map (A17=>LD(6), A16=>LD(5), A15=>LD(4), A14=>LD(3), + A13=>LD(2), A12=>LD(1), A11=>LD(0), A10=>scuba_vlo, + A9=>scuba_vlo, A8=>scuba_vlo, A7=>scuba_vlo, A6=>scuba_vlo, + A5=>scuba_vlo, A4=>scuba_vlo, A3=>scuba_vlo, A2=>scuba_vlo, + A1=>scuba_vlo, A0=>scuba_vlo, B17=>LD(24), B16=>LD(23), + B15=>LD(22), B14=>LD(21), B13=>LD(20), B12=>LD(19), + B11=>LD(18), B10=>LD(17), B9=>LD(16), B8=>LD(15), B7=>LD(14), + B6=>LD(13), B5=>LD(12), B4=>LD(11), B3=>LD(10), B2=>LD(9), + B1=>LD(8), B0=>LD(7), SIGNEDA=>scuba_vhi, SIGNEDB=>scuba_vhi, + SOURCEA=>scuba_vlo, SOURCEB=>scuba_vlo, CE0=>CE0, + CE1=>scuba_vhi, CE2=>scuba_vhi, CE3=>scuba_vhi, CLK0=>CLK0, + CLK1=>scuba_vlo, CLK2=>scuba_vlo, CLK3=>scuba_vlo, + RST0=>RST0, RST1=>scuba_vlo, RST2=>scuba_vlo, + RST3=>scuba_vlo, SRIA17=>scuba_vlo, SRIA16=>scuba_vlo, + SRIA15=>scuba_vlo, SRIA14=>scuba_vlo, SRIA13=>scuba_vlo, + SRIA12=>scuba_vlo, SRIA11=>scuba_vlo, SRIA10=>scuba_vlo, + SRIA9=>scuba_vlo, SRIA8=>scuba_vlo, SRIA7=>scuba_vlo, + SRIA6=>scuba_vlo, SRIA5=>scuba_vlo, SRIA4=>scuba_vlo, + SRIA3=>scuba_vlo, SRIA2=>scuba_vlo, SRIA1=>scuba_vlo, + SRIA0=>scuba_vlo, SRIB17=>scuba_vlo, SRIB16=>scuba_vlo, + SRIB15=>scuba_vlo, SRIB14=>scuba_vlo, SRIB13=>scuba_vlo, + SRIB12=>scuba_vlo, SRIB11=>scuba_vlo, SRIB10=>scuba_vlo, + SRIB9=>scuba_vlo, SRIB8=>scuba_vlo, SRIB7=>scuba_vlo, + SRIB6=>scuba_vlo, SRIB5=>scuba_vlo, SRIB4=>scuba_vlo, + SRIB3=>scuba_vlo, SRIB2=>scuba_vlo, SRIB1=>scuba_vlo, + SRIB0=>scuba_vlo, SROA17=>open, SROA16=>open, SROA15=>open, + SROA14=>open, SROA13=>open, SROA12=>open, SROA11=>open, + SROA10=>open, SROA9=>open, SROA8=>open, SROA7=>open, + SROA6=>open, SROA5=>open, SROA4=>open, SROA3=>open, + SROA2=>open, SROA1=>open, SROA0=>open, SROB17=>open, + SROB16=>open, SROB15=>open, SROB14=>open, SROB13=>open, + SROB12=>open, SROB11=>open, SROB10=>open, SROB9=>open, + SROB8=>open, SROB7=>open, SROB6=>open, SROB5=>open, + SROB4=>open, SROB3=>open, SROB2=>open, SROB1=>open, + SROB0=>open, ROA17=>mulacc2_0_mult_out_roa_0_17, + ROA16=>mulacc2_0_mult_out_roa_0_16, + ROA15=>mulacc2_0_mult_out_roa_0_15, + ROA14=>mulacc2_0_mult_out_roa_0_14, + ROA13=>mulacc2_0_mult_out_roa_0_13, + ROA12=>mulacc2_0_mult_out_roa_0_12, + ROA11=>mulacc2_0_mult_out_roa_0_11, + ROA10=>mulacc2_0_mult_out_roa_0_10, + ROA9=>mulacc2_0_mult_out_roa_0_9, + ROA8=>mulacc2_0_mult_out_roa_0_8, + ROA7=>mulacc2_0_mult_out_roa_0_7, + ROA6=>mulacc2_0_mult_out_roa_0_6, + ROA5=>mulacc2_0_mult_out_roa_0_5, + ROA4=>mulacc2_0_mult_out_roa_0_4, + ROA3=>mulacc2_0_mult_out_roa_0_3, + ROA2=>mulacc2_0_mult_out_roa_0_2, + ROA1=>mulacc2_0_mult_out_roa_0_1, + ROA0=>mulacc2_0_mult_out_roa_0_0, + ROB17=>mulacc2_0_mult_out_rob_0_17, + ROB16=>mulacc2_0_mult_out_rob_0_16, + ROB15=>mulacc2_0_mult_out_rob_0_15, + ROB14=>mulacc2_0_mult_out_rob_0_14, + ROB13=>mulacc2_0_mult_out_rob_0_13, + ROB12=>mulacc2_0_mult_out_rob_0_12, + ROB11=>mulacc2_0_mult_out_rob_0_11, + ROB10=>mulacc2_0_mult_out_rob_0_10, + ROB9=>mulacc2_0_mult_out_rob_0_9, + ROB8=>mulacc2_0_mult_out_rob_0_8, + ROB7=>mulacc2_0_mult_out_rob_0_7, + ROB6=>mulacc2_0_mult_out_rob_0_6, + ROB5=>mulacc2_0_mult_out_rob_0_5, + ROB4=>mulacc2_0_mult_out_rob_0_4, + ROB3=>mulacc2_0_mult_out_rob_0_3, + ROB2=>mulacc2_0_mult_out_rob_0_2, + ROB1=>mulacc2_0_mult_out_rob_0_1, + ROB0=>mulacc2_0_mult_out_rob_0_0, + P35=>mulacc2_0_mult_out_p_0_35, + P34=>mulacc2_0_mult_out_p_0_34, + P33=>mulacc2_0_mult_out_p_0_33, + P32=>mulacc2_0_mult_out_p_0_32, + P31=>mulacc2_0_mult_out_p_0_31, + P30=>mulacc2_0_mult_out_p_0_30, + P29=>mulacc2_0_mult_out_p_0_29, + P28=>mulacc2_0_mult_out_p_0_28, + P27=>mulacc2_0_mult_out_p_0_27, + P26=>mulacc2_0_mult_out_p_0_26, + P25=>mulacc2_0_mult_out_p_0_25, + P24=>mulacc2_0_mult_out_p_0_24, + P23=>mulacc2_0_mult_out_p_0_23, + P22=>mulacc2_0_mult_out_p_0_22, + P21=>mulacc2_0_mult_out_p_0_21, + P20=>mulacc2_0_mult_out_p_0_20, + P19=>mulacc2_0_mult_out_p_0_19, + P18=>mulacc2_0_mult_out_p_0_18, + P17=>mulacc2_0_mult_out_p_0_17, + P16=>mulacc2_0_mult_out_p_0_16, + P15=>mulacc2_0_mult_out_p_0_15, + P14=>mulacc2_0_mult_out_p_0_14, + P13=>mulacc2_0_mult_out_p_0_13, + P12=>mulacc2_0_mult_out_p_0_12, + P11=>mulacc2_0_mult_out_p_0_11, + P10=>mulacc2_0_mult_out_p_0_10, P9=>mulacc2_0_mult_out_p_0_9, + P8=>mulacc2_0_mult_out_p_0_8, P7=>mulacc2_0_mult_out_p_0_7, + P6=>mulacc2_0_mult_out_p_0_6, P5=>mulacc2_0_mult_out_p_0_5, + P4=>mulacc2_0_mult_out_p_0_4, P3=>mulacc2_0_mult_out_p_0_3, + P2=>mulacc2_0_mult_out_p_0_2, P1=>mulacc2_0_mult_out_p_0_1, + P0=>mulacc2_0_mult_out_p_0_0, + SIGNEDP=>mulacc2_0_mult_out_signedp_0); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + dsp_mult_0: MULT18X18C + generic map (MULT_BYPASS=> "DISABLED", CAS_MATCH_REG=> "FALSE", + RESETMODE=> "SYNC", GSR=> "ENABLED", REG_OUTPUT_RST=> "RST0", + REG_OUTPUT_CE=> "CE0", REG_OUTPUT_CLK=> "NONE", REG_PIPELINE_RST=> "RST0", + REG_PIPELINE_CE=> "CE0", REG_PIPELINE_CLK=> "NONE", + REG_INPUTB_RST=> "RST0", REG_INPUTB_CE=> "CE0", REG_INPUTB_CLK=> "CLK0", + REG_INPUTA_RST=> "RST0", REG_INPUTA_CE=> "CE0", REG_INPUTA_CLK=> "CLK0") + port map (A17=>A(8), A16=>A(7), A15=>A(6), A14=>A(5), A13=>A(4), + A12=>A(3), A11=>A(2), A10=>A(1), A9=>A(0), A8=>scuba_vlo, + A7=>scuba_vlo, A6=>scuba_vlo, A5=>scuba_vlo, A4=>scuba_vlo, + A3=>scuba_vlo, A2=>scuba_vlo, A1=>scuba_vlo, A0=>scuba_vlo, + B17=>B(15), B16=>B(14), B15=>B(13), B14=>B(12), B13=>B(11), + B12=>B(10), B11=>B(9), B10=>B(8), B9=>B(7), B8=>B(6), + B7=>B(5), B6=>B(4), B5=>B(3), B4=>B(2), B3=>B(1), B2=>B(0), + B1=>scuba_vlo, B0=>scuba_vlo, SIGNEDA=>scuba_vhi, + SIGNEDB=>scuba_vlo, SOURCEA=>scuba_vlo, SOURCEB=>scuba_vlo, + CE0=>CE0, CE1=>scuba_vhi, CE2=>scuba_vhi, CE3=>scuba_vhi, + CLK0=>CLK0, CLK1=>scuba_vlo, CLK2=>scuba_vlo, + CLK3=>scuba_vlo, RST0=>RST0, RST1=>scuba_vlo, + RST2=>scuba_vlo, RST3=>scuba_vlo, SRIA17=>scuba_vlo, + SRIA16=>scuba_vlo, SRIA15=>scuba_vlo, SRIA14=>scuba_vlo, + SRIA13=>scuba_vlo, SRIA12=>scuba_vlo, SRIA11=>scuba_vlo, + SRIA10=>scuba_vlo, SRIA9=>scuba_vlo, SRIA8=>scuba_vlo, + SRIA7=>scuba_vlo, SRIA6=>scuba_vlo, SRIA5=>scuba_vlo, + SRIA4=>scuba_vlo, SRIA3=>scuba_vlo, SRIA2=>scuba_vlo, + SRIA1=>scuba_vlo, SRIA0=>scuba_vlo, SRIB17=>scuba_vlo, + SRIB16=>scuba_vlo, SRIB15=>scuba_vlo, SRIB14=>scuba_vlo, + SRIB13=>scuba_vlo, SRIB12=>scuba_vlo, SRIB11=>scuba_vlo, + SRIB10=>scuba_vlo, SRIB9=>scuba_vlo, SRIB8=>scuba_vlo, + SRIB7=>scuba_vlo, SRIB6=>scuba_vlo, SRIB5=>scuba_vlo, + SRIB4=>scuba_vlo, SRIB3=>scuba_vlo, SRIB2=>scuba_vlo, + SRIB1=>scuba_vlo, SRIB0=>scuba_vlo, SROA17=>open, + SROA16=>open, SROA15=>open, SROA14=>open, SROA13=>open, + SROA12=>open, SROA11=>open, SROA10=>open, SROA9=>open, + SROA8=>open, SROA7=>open, SROA6=>open, SROA5=>open, + SROA4=>open, SROA3=>open, SROA2=>open, SROA1=>open, + SROA0=>open, SROB17=>open, SROB16=>open, SROB15=>open, + SROB14=>open, SROB13=>open, SROB12=>open, SROB11=>open, + SROB10=>open, SROB9=>open, SROB8=>open, SROB7=>open, + SROB6=>open, SROB5=>open, SROB4=>open, SROB3=>open, + SROB2=>open, SROB1=>open, SROB0=>open, + ROA17=>mulacc2_0_mult_out_roa_1_17, + ROA16=>mulacc2_0_mult_out_roa_1_16, + ROA15=>mulacc2_0_mult_out_roa_1_15, + ROA14=>mulacc2_0_mult_out_roa_1_14, + ROA13=>mulacc2_0_mult_out_roa_1_13, + ROA12=>mulacc2_0_mult_out_roa_1_12, + ROA11=>mulacc2_0_mult_out_roa_1_11, + ROA10=>mulacc2_0_mult_out_roa_1_10, + ROA9=>mulacc2_0_mult_out_roa_1_9, + ROA8=>mulacc2_0_mult_out_roa_1_8, + ROA7=>mulacc2_0_mult_out_roa_1_7, + ROA6=>mulacc2_0_mult_out_roa_1_6, + ROA5=>mulacc2_0_mult_out_roa_1_5, + ROA4=>mulacc2_0_mult_out_roa_1_4, + ROA3=>mulacc2_0_mult_out_roa_1_3, + ROA2=>mulacc2_0_mult_out_roa_1_2, + ROA1=>mulacc2_0_mult_out_roa_1_1, + ROA0=>mulacc2_0_mult_out_roa_1_0, + ROB17=>mulacc2_0_mult_out_rob_1_17, + ROB16=>mulacc2_0_mult_out_rob_1_16, + ROB15=>mulacc2_0_mult_out_rob_1_15, + ROB14=>mulacc2_0_mult_out_rob_1_14, + ROB13=>mulacc2_0_mult_out_rob_1_13, + ROB12=>mulacc2_0_mult_out_rob_1_12, + ROB11=>mulacc2_0_mult_out_rob_1_11, + ROB10=>mulacc2_0_mult_out_rob_1_10, + ROB9=>mulacc2_0_mult_out_rob_1_9, + ROB8=>mulacc2_0_mult_out_rob_1_8, + ROB7=>mulacc2_0_mult_out_rob_1_7, + ROB6=>mulacc2_0_mult_out_rob_1_6, + ROB5=>mulacc2_0_mult_out_rob_1_5, + ROB4=>mulacc2_0_mult_out_rob_1_4, + ROB3=>mulacc2_0_mult_out_rob_1_3, + ROB2=>mulacc2_0_mult_out_rob_1_2, + ROB1=>mulacc2_0_mult_out_rob_1_1, + ROB0=>mulacc2_0_mult_out_rob_1_0, + P35=>mulacc2_0_mult_out_p_1_35, + P34=>mulacc2_0_mult_out_p_1_34, + P33=>mulacc2_0_mult_out_p_1_33, + P32=>mulacc2_0_mult_out_p_1_32, + P31=>mulacc2_0_mult_out_p_1_31, + P30=>mulacc2_0_mult_out_p_1_30, + P29=>mulacc2_0_mult_out_p_1_29, + P28=>mulacc2_0_mult_out_p_1_28, + P27=>mulacc2_0_mult_out_p_1_27, + P26=>mulacc2_0_mult_out_p_1_26, + P25=>mulacc2_0_mult_out_p_1_25, + P24=>mulacc2_0_mult_out_p_1_24, + P23=>mulacc2_0_mult_out_p_1_23, + P22=>mulacc2_0_mult_out_p_1_22, + P21=>mulacc2_0_mult_out_p_1_21, + P20=>mulacc2_0_mult_out_p_1_20, + P19=>mulacc2_0_mult_out_p_1_19, + P18=>mulacc2_0_mult_out_p_1_18, + P17=>mulacc2_0_mult_out_p_1_17, + P16=>mulacc2_0_mult_out_p_1_16, + P15=>mulacc2_0_mult_out_p_1_15, + P14=>mulacc2_0_mult_out_p_1_14, + P13=>mulacc2_0_mult_out_p_1_13, + P12=>mulacc2_0_mult_out_p_1_12, + P11=>mulacc2_0_mult_out_p_1_11, + P10=>mulacc2_0_mult_out_p_1_10, P9=>mulacc2_0_mult_out_p_1_9, + P8=>mulacc2_0_mult_out_p_1_8, P7=>mulacc2_0_mult_out_p_1_7, + P6=>mulacc2_0_mult_out_p_1_6, P5=>mulacc2_0_mult_out_p_1_5, + P4=>mulacc2_0_mult_out_p_1_4, P3=>mulacc2_0_mult_out_p_1_3, + P2=>mulacc2_0_mult_out_p_1_2, P1=>mulacc2_0_mult_out_p_1_1, + P0=>mulacc2_0_mult_out_p_1_0, + SIGNEDP=>mulacc2_0_mult_out_signedp_1); + + ACCUM(40) <= mulacc2_alu_output_r_1_0_51; + ACCUM(39) <= mulacc2_alu_output_r_1_0_50; + ACCUM(38) <= mulacc2_alu_output_r_1_0_49; + ACCUM(37) <= mulacc2_alu_output_r_1_0_48; + ACCUM(36) <= mulacc2_alu_output_r_1_0_47; + ACCUM(35) <= mulacc2_alu_output_r_1_0_46; + ACCUM(34) <= mulacc2_alu_output_r_1_0_45; + ACCUM(33) <= mulacc2_alu_output_r_1_0_44; + ACCUM(32) <= mulacc2_alu_output_r_1_0_43; + ACCUM(31) <= mulacc2_alu_output_r_1_0_42; + ACCUM(30) <= mulacc2_alu_output_r_1_0_41; + ACCUM(29) <= mulacc2_alu_output_r_1_0_40; + ACCUM(28) <= mulacc2_alu_output_r_1_0_39; + ACCUM(27) <= mulacc2_alu_output_r_1_0_38; + ACCUM(26) <= mulacc2_alu_output_r_1_0_37; + ACCUM(25) <= mulacc2_alu_output_r_1_0_36; + ACCUM(24) <= mulacc2_alu_output_r_1_0_35; + ACCUM(23) <= mulacc2_alu_output_r_1_0_34; + ACCUM(22) <= mulacc2_alu_output_r_1_0_33; + ACCUM(21) <= mulacc2_alu_output_r_1_0_32; + ACCUM(20) <= mulacc2_alu_output_r_1_0_31; + ACCUM(19) <= mulacc2_alu_output_r_1_0_30; + ACCUM(18) <= mulacc2_alu_output_r_1_0_29; + ACCUM(17) <= mulacc2_alu_output_r_1_0_28; + ACCUM(16) <= mulacc2_alu_output_r_1_0_27; + ACCUM(15) <= mulacc2_alu_output_r_1_0_26; + ACCUM(14) <= mulacc2_alu_output_r_1_0_25; + ACCUM(13) <= mulacc2_alu_output_r_1_0_24; + ACCUM(12) <= mulacc2_alu_output_r_1_0_23; + ACCUM(11) <= mulacc2_alu_output_r_1_0_22; + ACCUM(10) <= mulacc2_alu_output_r_1_0_21; + ACCUM(9) <= mulacc2_alu_output_r_1_0_20; + ACCUM(8) <= mulacc2_alu_output_r_1_0_19; + ACCUM(7) <= mulacc2_alu_output_r_1_0_18; + ACCUM(6) <= mulacc2_alu_output_r_1_0_17; + ACCUM(5) <= mulacc2_alu_output_r_1_0_16; + ACCUM(4) <= mulacc2_alu_output_r_1_0_15; + ACCUM(3) <= mulacc2_alu_output_r_1_0_14; + ACCUM(2) <= mulacc2_alu_output_r_1_0_13; + ACCUM(1) <= mulacc2_alu_output_r_1_0_12; + ACCUM(0) <= mulacc2_alu_output_r_1_0_11; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of mulacc2 is + for Structure + for all:INV use entity ecp3.INV(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:MULT18X18C use entity ecp3.MULT18X18C(V); end for; + for all:ALU54A use entity ecp3.ALU54A(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on