From: local account Date: Thu, 18 May 2017 08:23:17 +0000 (+0200) Subject: Addes Flash support and minor fixes for MachXO34300E X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=98135723f6be48425cf5eddaeb73800d844ba5a1;p=dirich.git Addes Flash support and minor fixes for MachXO34300E --- diff --git a/thresholds/config_compile_gsi.pl b/thresholds/config_compile_gsi.pl index a356297..7a3b0a7 100644 --- a/thresholds/config_compile_gsi.pl +++ b/thresholds/config_compile_gsi.pl @@ -1,6 +1,11 @@ + #Familyname => 'MachXO3LF', + #Devicename => 'LCMXO3LF-6900C', + #Package => 'CABGA256', + #Speedgrade => '5', + Familyname => 'MachXO3LF', -Devicename => 'LCMXO3LF-6900C', -Package => 'CABGA256', +Devicename => 'LCMXO3LF-4300E', +Package => 'WLCSP81', Speedgrade => '5', TOPNAME => "thresholds", @@ -15,7 +20,7 @@ nodelist_file => 'nodelist_frankfurt.txt', #Include only necessary lpf files -#pinout_file => '', #name of pin-out file, if not equal TOPNAME +pinout_file => 'thresholds', #name of pin-out file, if not equal TOPNAME include_TDC => 0, include_GBE => 0, diff --git a/thresholds/thresholds.prj b/thresholds/thresholds.prj index b2787ad..56eac69 100644 --- a/thresholds/thresholds.prj +++ b/thresholds/thresholds.prj @@ -7,13 +7,14 @@ #add_file -vhdl -lib work "/d/jspc29/lattice/diamond/3.6_x64/cae_library/synthesis/vhdl/machxo3lf.vhd" #add_file -vhdl -lib work "../../trbnet/lattice/machxo3/fifo_9x2k_oreg.vhd" +#add file -vhdl -lib work "./test/machxo3lf.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" add_file -vhdl -lib work "../../dirich/code/spi_slave.vhd" add_file -vhdl -lib work "../../logicbox/code/sedcheck.vhd" add_file -vhdl -lib work "../code/pwm_machxo.vhd" add_file -vhdl -lib work "../../logicbox/UFM_control/UFM_control.vhd" add_file -vhdl -lib work "../../logicbox/cores/flashram.vhd" -add_file -vhdl -lib work "cores/flash.vhd" +add_file -vhdl -lib work "../../logicbox/cores/flash.vhd" #add_file -vhdl -lib work "../../logicbox/cores/flashram.vhd" @@ -39,8 +40,10 @@ set_option -job par_1 -add par #device options set_option -technology MACHXO3LF -set_option -part LCMXO3LF_6900C -set_option -package BG256C +#set_option -part LCMXO3LF_6900C +#set_option -package BG256C +set_option -part LCMXO3LF_4300E +set_option -package UWG81 set_option -speed_grade -5 set_option -part_companion "" diff --git a/thresholds/thresholds.vhd b/thresholds/thresholds.vhd index 2a00fa1..060e78c 100644 --- a/thresholds/thresholds.vhd +++ b/thresholds/thresholds.vhd @@ -10,12 +10,14 @@ use work.trb_net_std.all; entity thresholds is port( - ID : in std_logic; - OUTPUT : out std_logic_vector(15 downto 0); + DAC_FLAG : in std_logic; --ID + OUTPUT : out std_logic_vector(16 downto 1); MISO_OUT : out std_logic; MOSI_IN : in std_logic; SCLK_IN : in std_logic; - CS_IN : in std_logic + CS_IN : in std_logic--; + --LED : out std_logic_vector(7 downto 0); + --DIPSW : in std_logic_vector(3 downto 0) ); end entity; @@ -36,18 +38,21 @@ architecture arch of thresholds is signal sed_debug : std_logic_vector(31 downto 0); signal controlsed_i : std_logic_vector(3 downto 0); - signal pwm_data_i : std_logic_vector(15 downto 0); - signal pwm_write_i : std_logic; - signal pwm_addr_i : std_logic_vector(4 downto 0); - signal pwm_data_ii : std_logic_vector(15 downto 0); - signal pwm_write_ii : std_logic; - signal pwm_addr_ii : std_logic_vector(4 downto 0); + signal pwm_data_i : std_logic_vector(15 downto 0):= x"6000"; + signal pwm_write_i : std_logic; + signal pwm_addr_i : std_logic_vector(4 downto 0); + signal pwm_data_ii : std_logic_vector(15 downto 0); + signal pwm_write_ii : std_logic; + signal pwm_addr_ii : std_logic_vector(4 downto 0); + signal pwm_data_iii : std_logic_vector(15 downto 0); + signal pwm_write_iii : std_logic; + signal pwm_addr_iii : std_logic_vector(4 downto 0); -- signal flashram_reset : std_logic; --signal flashram_write_i: std_logic; signal flashram_data_i : std_logic_vector(7 downto 0); - signal flashram_data_o : std_logic_vector(7 downto 0); - signal ram_data : ram_t := (others =>("0000000000000000"));--: std_logic_vector(15 downto 0); + signal flashram_data_o : std_logic_vector(7 downto 0) := "00000010"; + signal ram_data : ram_t := (others =>("0000000000100001"));--: std_logic_vector(15 downto 0); --signal ram_data_o : ram_t := (others =>("0000000000000000"));--std_logic_vector(15 downto 0); signal flash_command : std_logic; @@ -56,16 +61,25 @@ architecture arch of thresholds is signal flash_busy : std_logic; signal flash_err : std_logic; - signal compensate_i : signed(15 downto 0); - signal pwm_i : std_logic_vector(15 downto 0); + signal compensate_i : signed(15 downto 0) := (others =>'0'); + signal pwm_i : std_logic_vector(16 downto 1); signal ufm_bus_ready_in : std_logic; signal ufm_bus_ready_out : std_logic; signal ufm_databyte_counter : unsigned(14 downto 0); - signal ram_data_f_spi_addr : std_logic_vector( 7 downto 0); - signal ram_data_f_spi_data : std_logic_vector(15 downto 0); - signal ram_data_f_spi_write : std_logic; + signal ram_spi_addr : std_logic_vector( 7 downto 0); + signal ram_spi_data : std_logic_vector(15 downto 0):= "0000111100001111"; + signal ram_spi_write : std_logic; + signal show_flash_err : std_logic := '0'; + signal ram_spi_read :std_logic := '0'; + signal flash_temp : std_logic_vector(7 downto 0); + + --type state_type is (Start,IDLE,c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,c15); --type of state machine. + --signal state: state_type := Start; + --signal init : std_logic:='1'; + +-- signal temp : std_logic_vector(3 downto 0):= "0000"; component OSCH generic (NOM_FREQ: string := "33.25"); @@ -112,56 +126,205 @@ THE_SPI : entity work.spi_slave DEBUG => open ); - - -PROC_REGS : process begin - wait until rising_edge(clk_i); - bus_ready <= '0'; - pwm_write_i <= '0'; - flash_go <= '0'; - ram_data_f_spi_write <= '0'; + - if pwm_write_ii = '1' then - pwm_data_i <= pwm_data_ii; - pwm_addr_i <= pwm_addr_ii; - pwm_write_i <= pwm_write_ii; - - elsif bus_read = '1' then - bus_ready <= '1'; - if spi_addr >= x"10" and spi_addr < x"20" then - spi_tx_data <= ram_data(to_integer(unsigned(spi_addr))); +-- count : process (clk_i) +-- begin +-- if rising_edge(clk_i) then +-- if temp="1001" then +-- temp<="0000"; +-- else +-- temp <= std_logic_vector(unsigned(temp) + 1); +-- end if; +-- end if; +-- +-- end process; + +-- state_machine : process (clk_i) +-- begin +-- if rising_edge(clk_i) then +-- pwm_write_i <= '0'; +-- --pwm_data_i <= x"6000"; +-- case state is +-- when Start => --when current state is "s0" +-- if init = '1' then +-- pwm_write_i <= '0'; +-- state <= c0; +-- end if; +-- +-- when c0 => pwm_write_i <= '1'; +-- pwm_addr_i <= "00000"; +-- state <= c1; +-- +-- when c1 => pwm_write_i <= '1'; +-- pwm_addr_i <= "00001"; +-- state <= c2; +-- +-- when c2 => pwm_write_i <= '1'; +-- pwm_addr_i <= "00010"; +-- state <= c3; +-- +-- when c3 => pwm_write_i <= '1'; +-- pwm_addr_i <= "00011"; +-- state <= c4; +-- +-- when c4 => pwm_write_i <= '1'; +-- pwm_addr_i <= "00100"; +-- state <= c5; +-- +-- when c5 => pwm_write_i <= '1'; +-- pwm_addr_i <= "00101"; +-- state <= c6; +-- +-- when c6 => pwm_write_i <= '1'; +-- pwm_addr_i <= "00110"; +-- state <= c7; +-- +-- when c7 => pwm_write_i <= '1'; +-- pwm_addr_i <= "00111"; +-- state <= c8; +-- +-- when c8 => pwm_write_i <= '1'; +-- pwm_addr_i <= "01000"; +-- state <= c9; +-- +-- when c9 => pwm_write_i <= '1'; +-- pwm_addr_i <= "01001"; +-- state <= c10; +-- +-- when c10 => pwm_write_i <= '1'; +-- pwm_addr_i <= "01010"; +-- state <= c11; +-- +-- when c11 => pwm_write_i <= '1'; +-- pwm_addr_i <= "01011"; +-- state <= c12; +-- +-- when c12 => pwm_write_i <= '1'; +-- pwm_addr_i <= "01100"; +-- state <= c13; +-- +-- when c13 => pwm_write_i <= '1'; +-- pwm_addr_i <= "01101"; +-- state <= c14; +-- +-- when c14 => pwm_write_i <= '1'; +-- pwm_addr_i <= "01110"; +-- state <= c15; +-- +-- when c15 => pwm_write_i <= '1'; +-- pwm_addr_i <= "01111"; +-- init <= '0'; +-- state <= IDLE; +-- init <= '0'; +-- +-- when IDLE => pwm_write_i <= pwm_write_ii; +-- pwm_addr_i <= pwm_addr_ii; +-- pwm_data_i <= pwm_data_ii; +-- +-- end case; +-- +-- end if; +-- end process; + + +PWM_select : process begin + wait until rising_edge(clk_i); + + pwm_write_i <= '0'; + if pwm_write_ii = '1' then + pwm_data_i <= pwm_data_ii; + pwm_addr_i <= pwm_addr_ii; + pwm_write_i <= pwm_write_ii; else - case spi_addr is - when x"30" => spi_tx_data <= std_logic_vector(compensate_i); - when x"ee" => spi_tx_data <= sed_debug(15 downto 0); - when x"ef" => spi_tx_data <= sed_debug(31 downto 16); - when others => null; - end case; + pwm_data_i <= pwm_data_iii; + pwm_addr_i <= pwm_addr_iii; + pwm_write_i <= pwm_write_iii; end if; + +end process; + - elsif bus_write = '1' then - if spi_addr < x"10" then -- 0 to 15 0x00 to 0x10 -- write directly to pwm - if flash_busy = '0' or flash_command = '0' then -- avoid conflict with writing from flash - pwm_data_i <= spi_rx_data(15 downto 0); - pwm_addr_i <= spi_addr(4 downto 0); - pwm_write_i <= '1'; - end if; - elsif spi_addr >= x"10" and spi_addr < x"20" then -- write to ram - --ram_data(to_integer(unsigned(spi_addr(3 downto 0)))) <= spi_rx_data; - ram_data_f_spi_write <= '1'; - ram_data_f_spi_addr <= spi_addr; - ram_data_f_spi_data <= spi_rx_data; - else - case spi_addr is - -- when x"20" => flash_command <= spi_rx_data(0); --read/write to flash; - -- flash_go <= '1'; - when x"30" => compensate_i <= spi_rx_data(15 downto 0);--signed(uart_rx_data(15 downto 0); - when x"ee" => controlsed_i <= spi_rx_data(3 downto 0); - end case; +PROC_REGS : process begin + wait until rising_edge(clk_i); + bus_ready <= '0'; + pwm_write_iii <= '0'; + flash_go <= '0'; + ram_spi_write <= '0'; + ram_spi_read <= '0'; + + if bus_read = '1' then + bus_ready <= '1'; + + if (spi_addr >= x"10") and (spi_addr < X"20") then + spi_tx_data <= ram_data(to_integer(unsigned(spi_addr(4 downto 0)))); -- Read RAM + else + case spi_addr is + --when x"10" => spi_tx_data <= reg_spi_o(15 downto 0); + --when x"11" => spi_tx_data <= reg_spi_o(31 downto 16); + when x"ee" => spi_tx_data <= sed_debug(15 downto 0); + when x"ef" => spi_tx_data <= sed_debug(31 downto 16); + -- + when others => null; + end case; + end if; + elsif bus_write = '1' then + if (spi_addr >= x"00") and (spi_addr < x"10") then -- write directly to PWM + pwm_data_iii <= spi_rx_data; + pwm_addr_iii <= spi_addr(4 downto 0); + pwm_write_iii <= '1'; + elsif ( spi_addr >= x"10") and (spi_addr < x"20") then -- write to RAM + ram_spi_data(15 downto 0) <= spi_rx_data; + ram_spi_write <= '1'; + ram_spi_addr <= "0000" & spi_addr(3 downto 0); + pwm_data_iii <= spi_rx_data; + pwm_addr_iii <= spi_addr(4 downto 0); + pwm_write_iii <= '1'; + else + case spi_addr is + when x"20" => flash_command <= '1'; --write to flash; + flash_go <= '1'; + when x"21" => flash_command <= '0'; --read from flash; + flash_go <= '1'; + when x"22" => compensate_i <= signed(spi_rx_data(15 downto 0));--signed(uart_rx_data(15 downto 0); + when x"ee" => controlsed_i <= spi_rx_data(3 downto 0); + when others => null; + end case; + end if; end if; - end if; end process; +-- ManSel : process begin +-- wait until rising_edge(clk_i); +-- flash_go <= '0'; +-- ram_spi_write <= '0'; +-- --ram_spi_read <= '0'; +-- if pwm_write_ii = '1' then +-- pwm_data_i <= pwm_data_ii; +-- pwm_addr_i <= pwm_addr_ii; +-- pwm_write_i <= pwm_write_ii; +-- elsif DIPSW(0) = '0' then +-- case DIPSW(3 downto 1) is +-- when "000" => ram_spi_data(15 downto 0) <= "1100011100111000"; +-- ram_spi_write <= '1'; +-- ram_spi_addr <= "00000" & DIPSW(3 downto 1); +-- --when "010" => ram_spi_read <= '1'; +-- when "011" => flash_command <= '0'; --read from flash; +-- flash_go <= '1'; +-- when "100" => flash_command <= '1'; --write to flash; +-- flash_go <= '1'; +-- when "101" => ram_spi_data(15 downto 0) <= "0000011000101010"; +-- ram_spi_write <= '1'; +-- ram_spi_addr <= "00000" & DIPSW(3 downto 1); +-- when others => null; +-- end case; +-- else +-- LED <= not ram_data(to_integer(unsigned(DIPSW(3 downto 1))))(7 downto 0); +-- end if; +-- +-- +-- end process; + THE_SED : entity work.sedcheck port map( @@ -190,154 +353,69 @@ THE_PWM_GEN : entity work.pwm_generator ); --TODO connect to output according to ID -OUTPUT <= pwm_i; - +process(pwm_i,DAC_FLAG) + begin + if DAC_FLAG = '1' then + OUTPUT <= pwm_i; + else + OUTPUT(1) <= pwm_i(15); + OUTPUT(2) <= pwm_i(13); + OUTPUT(3) <= pwm_i(8); + OUTPUT(4) <= pwm_i(5); + OUTPUT(5) <= pwm_i(16); + OUTPUT(6) <= pwm_i(4); + OUTPUT(7) <= pwm_i(3); + OUTPUT(8) <= pwm_i(6); + OUTPUT(9) <= pwm_i(2); + OUTPUT(10) <= pwm_i(1); + OUTPUT(11) <= pwm_i(7); + OUTPUT(12) <= pwm_i(9); + OUTPUT(13) <= pwm_i(14); + OUTPUT(14) <= pwm_i(12); + OUTPUT(15) <= pwm_i(10); + OUTPUT(16) <= pwm_i(11); + + end if; + end process; --------------------------------------------------------------------------- -- Flash Controller --------------------------------------------------------------------------- ---THE_UFM : entity work.UFM_control --- generic map( --- NO_DATAPAGES => 2, --- UFM_STARTPAGE => "00"&x"00" --- ) --- port map( --- CLK => clk_i, --- CMD => flash_command, --- GO => flash_go, --- BUSY => flash_busy, --- RESET => '0', --- DATA_IN => flashram_data_i, --- DATA_OUT => flashram_data_o, --- DATABYTE_COUNTER => ufm_databyte_counter, --specifies current databyte --- BUS_READY_IN => ufm_bus_ready_in, --- BUS_READY_OUT => ufm_bus_ready_out, --- FLASH_ERROR => flash_err --- ); - +THE_UFM : entity work.UFM_control + generic map( + NO_DATAPAGES => 2, + UFM_STARTPAGE => "00"&x"00" + ) + port map( + CLK => clk_i, + CMD => flash_command, + GO => flash_go, + BUSY => flash_busy, + RESET => '0', + DATA_IN => flashram_data_i, + DATA_OUT => flashram_data_o, + DATABYTE_COUNTER => ufm_databyte_counter, --specifies current databyte + BUS_READY_IN => ufm_bus_ready_in, + BUS_READY_OUT => ufm_bus_ready_out, + FLASH_ERROR => flash_err + ); ---PROC_REGS_FLASH: process begin ---wait until rising_edge( clk_i ); + +-- PROC_REGS_FLASH: process begin +-- wait until rising_edge( clk_i ); -- ufm_bus_ready_in <= '0'; -- pwm_write_ii <= '0'; --- if flash_command = '0' and ufm_bus_ready_out = '1' then --- -- copy data from UFM to registers --- ufm_bus_ready_in <= '1'; --- case to_integer ( ufm_databyte_counter ) is --- when 0 => ram_data( 0)( 7 downto 0) <= flashram_data_o; --- pwm_write_ii <= '0'; --- pwm_data_ii( 7 downto 0) <= flashram_data_o; --- when 1 => ram_data( 0)(15 downto 8) <= flashram_data_o; --- pwm_write_ii <= '1'; --- pwm_addr_ii <= "00000"; --- pwm_data_ii( 15 downto 8) <= flashram_data_o; --- when 2 => ram_data( 1)( 7 downto 0) <= flashram_data_o; --- pwm_write_ii <= '0'; --- pwm_data_ii( 7 downto 0) <= flashram_data_o; --- when 3 => ram_data( 1)(15 downto 8) <= flashram_data_o; --- pwm_write_ii <= '1'; --- pwm_addr_ii <= "00001"; --- pwm_data_ii( 15 downto 8) <= flashram_data_o; --- when 4 => ram_data( 2)( 7 downto 0) <= flashram_data_o; --- pwm_write_ii <= '0'; --- pwm_data_ii( 7 downto 0) <= flashram_data_o; --- when 5 => ram_data( 2)(15 downto 8) <= flashram_data_o; --- pwm_write_ii <= '1'; --- pwm_addr_ii <= "00010"; --- pwm_data_ii( 15 downto 8) <= flashram_data_o; --- when 6 => ram_data( 3)( 7 downto 0) <= flashram_data_o; --- pwm_write_ii <= '0'; --- pwm_data_ii( 7 downto 0) <= flashram_data_o; --- when 7 => ram_data( 3)(15 downto 8) <= flashram_data_o; --- pwm_write_ii <= '1'; --- pwm_addr_ii <= "00011"; --- pwm_data_ii( 15 downto 8) <= flashram_data_o; --- when 8 => ram_data( 4)( 7 downto 0) <= flashram_data_o; --- pwm_write_ii <= '0'; --- pwm_data_ii( 7 downto 0) <= flashram_data_o; --- when 9 => ram_data( 4)(15 downto 8) <= flashram_data_o; --- pwm_write_ii <= '1'; --- pwm_addr_ii <= "00100"; --- pwm_data_ii( 15 downto 8) <= flashram_data_o; --- when 10 => ram_data( 5)( 7 downto 0) <= flashram_data_o; --- pwm_write_ii <= '0'; --- pwm_data_ii( 7 downto 0) <= flashram_data_o; --- when 11 => ram_data( 5)(15 downto 8) <= flashram_data_o; --- pwm_write_ii <= '1'; --- pwm_addr_ii <= "00101"; --- pwm_data_ii( 15 downto 8) <= flashram_data_o; --- when 12 => ram_data( 6)( 7 downto 0) <= flashram_data_o; --- pwm_write_ii <= '0'; --- pwm_data_ii( 7 downto 0) <= flashram_data_o; --- when 13 => ram_data( 6)(15 downto 8) <= flashram_data_o; --- pwm_write_ii <= '1'; --- pwm_addr_ii <= "00110"; --- pwm_data_ii( 15 downto 8) <= flashram_data_o; --- when 14 => ram_data( 7)( 7 downto 0) <= flashram_data_o; --- pwm_write_ii <= '0'; --- pwm_data_ii( 7 downto 0) <= flashram_data_o; --- when 15 => ram_data( 7)(15 downto 8) <= flashram_data_o; --- pwm_write_ii <= '1'; --- pwm_addr_ii <= "00111"; --- pwm_data_ii( 15 downto 8) <= flashram_data_o; --- when 16 => ram_data( 8)( 7 downto 0) <= flashram_data_o; --- pwm_write_ii <= '0'; --- pwm_data_ii( 7 downto 0) <= flashram_data_o; --- when 17 => ram_data( 8)(15 downto 8) <= flashram_data_o; --- pwm_write_ii <= '1'; --- pwm_addr_ii <= "01000"; --- pwm_data_ii( 15 downto 8) <= flashram_data_o; --- when 18 => ram_data( 9)( 7 downto 0) <= flashram_data_o; --- pwm_write_ii <= '0'; --- pwm_data_ii( 7 downto 0) <= flashram_data_o; --- when 19 => ram_data( 9)(15 downto 8) <= flashram_data_o; --- pwm_write_ii <= '1'; --- pwm_addr_ii <= "01001"; --- pwm_data_ii( 15 downto 8) <= flashram_data_o; --- when 20 => ram_data(10)( 7 downto 0) <= flashram_data_o; --- pwm_write_ii <= '0'; --- pwm_data_ii( 7 downto 0) <= flashram_data_o; --- when 21 => ram_data(10)(15 downto 8) <= flashram_data_o; --- pwm_write_ii <= '1'; --- pwm_addr_ii <= "01010"; --- pwm_data_ii( 15 downto 8) <= flashram_data_o; --- when 22 => ram_data(11)( 7 downto 0) <= flashram_data_o; --- pwm_write_ii <= '0'; --- pwm_data_ii( 7 downto 0) <= flashram_data_o; --- when 23 => ram_data(11)(15 downto 8) <= flashram_data_o; --- pwm_write_ii <= '1'; --- pwm_addr_ii <= "01011"; --- pwm_data_ii( 15 downto 8) <= flashram_data_o; --- when 24 => ram_data(12)( 7 downto 0) <= flashram_data_o; --- pwm_write_ii <= '0'; --- pwm_data_ii( 7 downto 0) <= flashram_data_o; --- when 25 => ram_data(12)(15 downto 8) <= flashram_data_o; --- pwm_write_ii <= '1'; --- pwm_addr_ii <= "01100"; --- pwm_data_ii( 15 downto 8) <= flashram_data_o; --- when 26 => ram_data(13)( 7 downto 0) <= flashram_data_o; --- pwm_write_ii <= '0'; --- pwm_data_ii( 7 downto 0) <= flashram_data_o; --- when 27 => ram_data(13)(15 downto 8) <= flashram_data_o; --- pwm_write_ii <= '1'; --- pwm_addr_ii <= "01101"; --- pwm_data_ii( 15 downto 8) <= flashram_data_o; --- when 28 => ram_data(14)( 7 downto 0) <= flashram_data_o; --- pwm_write_ii <= '0'; --- pwm_data_ii( 7 downto 0) <= flashram_data_o; --- when 29 => ram_data(14)(15 downto 8) <= flashram_data_o; --- pwm_write_ii <= '1'; --- pwm_addr_ii <= "01110"; --- pwm_data_ii(15 downto 8) <= flashram_data_o; --- when 30 => ram_data(15)( 7 downto 0) <= flashram_data_o; --- pwm_write_ii <= '0'; --- pwm_data_ii( 7 downto 0) <= flashram_data_o; --- when 31 => ram_data(15)(15 downto 8) <= flashram_data_o; --- pwm_write_ii <= '1'; --- pwm_addr_ii <= "01111"; --- pwm_data_ii(15 downto 8) <= flashram_data_o; +-- +-- if flash_command = '0' and ufm_bus_ready_out = '1' then +-- -- copy data from UFM to registers +-- ufm_bus_ready_in <= '1'; +-- case to_integer ( ufm_databyte_counter ) is +-- when 0 => ram_temp <= flashram_data_o; +-- when 1 => ram_data(0)(15 downto 0) <= flashram_data_o & ram_temp; +-- when 2 => ram_temp <= flashram_data_o; +-- when 3 => ram_data(1)(15 downto 0) <= flashram_data_o & ram_temp; -- when others => null; -- end case ; -- @@ -345,45 +423,155 @@ OUTPUT <= pwm_i; -- -- save data from registers to UFM -- ufm_bus_ready_in <= '1'; -- case to_integer ( ufm_databyte_counter ) is --- when 0 => flashram_data_i <= ram_data( 0)( 7 downto 0); --- when 1 => flashram_data_i <= ram_data( 0)(15 downto 8); --- when 2 => flashram_data_i <= ram_data( 1)( 7 downto 0); --- when 3 => flashram_data_i <= ram_data( 1)(15 downto 8); --- when 4 => flashram_data_i <= ram_data( 2)( 7 downto 0); --- when 5 => flashram_data_i <= ram_data( 2)(15 downto 8); --- when 6 => flashram_data_i <= ram_data( 3)( 7 downto 0); --- when 7 => flashram_data_i <= ram_data( 3)(15 downto 8); --- when 8 => flashram_data_i <= ram_data( 4)( 7 downto 0); --- when 9 => flashram_data_i <= ram_data( 4)(15 downto 8); --- when 10 => flashram_data_i <= ram_data( 5)( 7 downto 0); --- when 11 => flashram_data_i <= ram_data( 5)(15 downto 8); --- when 12 => flashram_data_i <= ram_data( 6)( 7 downto 0); --- when 13 => flashram_data_i <= ram_data( 6)(15 downto 8); --- when 14 => flashram_data_i <= ram_data( 7)( 7 downto 0); --- when 15 => flashram_data_i <= ram_data( 7)(15 downto 8); --- when 16 => flashram_data_i <= ram_data( 8)( 7 downto 0); --- when 17 => flashram_data_i <= ram_data( 8)(15 downto 8); --- when 18 => flashram_data_i <= ram_data( 9)( 7 downto 0); --- when 19 => flashram_data_i <= ram_data( 9)(15 downto 8); --- when 20 => flashram_data_i <= ram_data(10)( 7 downto 0); --- when 21 => flashram_data_i <= ram_data(10)(15 downto 8); --- when 22 => flashram_data_i <= ram_data(11)( 7 downto 0); --- when 23 => flashram_data_i <= ram_data(11)(15 downto 8); --- when 24 => flashram_data_i <= ram_data(12)( 7 downto 0); --- when 25 => flashram_data_i <= ram_data(12)(15 downto 8); --- when 26 => flashram_data_i <= ram_data(13)( 7 downto 0); --- when 27 => flashram_data_i <= ram_data(13)(15 downto 8); --- when 28 => flashram_data_i <= ram_data(14)( 7 downto 0); --- when 29 => flashram_data_i <= ram_data(14)(15 downto 8); --- when 30 => flashram_data_i <= ram_data(15)( 7 downto 0); --- when 31 => flashram_data_i <= ram_data(15)(15 downto 8); +-- when 0 => flashram_data_i <= ram_data(1)( 7 downto 0); +-- when 1 => flashram_data_i <= ram_data(1)(15 downto 8); +-- --when 2 => flashram_data_i <= ram_data(1)( 7 downto 0); +-- --when 3 => flashram_data_i <= ram_data(1)(15 downto 8); -- when others => null ; -- end case ; -- -- elsif ram_data_f_spi_write = '1' then --- ram_data(to_integer(unsigned(ram_data_f_spi_addr))) <= ram_data_f_spi_data; +-- ram_data(1) <= reg_spi; +-- elsif ram_data_f_spi_read = '1' then +-- reg_spi_o <= ram_data(1); -- end if ; --- end process ; + + + +PROC_REGS_FLASH: process begin +wait until rising_edge( clk_i ); + ufm_bus_ready_in <= '0'; + pwm_write_ii <= '0'; + if flash_command = '0' and ufm_bus_ready_out = '1' then + -- copy data from UFM to registers + ufm_bus_ready_in <= '1'; + case to_integer ( ufm_databyte_counter ) is + when 0 => flash_temp <= flashram_data_o; + when 1 => ram_data( 0) <= flashram_data_o & flash_temp; + pwm_write_ii <= '1'; + pwm_addr_ii <= "00000"; + pwm_data_ii <= flashram_data_o & flash_temp; + when 2 => flash_temp <= flashram_data_o; + when 3 => ram_data( 1) <= flashram_data_o & flash_temp; + pwm_write_ii <= '1'; + pwm_addr_ii <= "00001"; + pwm_data_ii <= flashram_data_o & flash_temp; + when 4 => flash_temp <= flashram_data_o; + when 5 => ram_data( 2) <= flashram_data_o & flash_temp; + pwm_write_ii <= '1'; + pwm_addr_ii <= "00010"; + pwm_data_ii <= flashram_data_o & flash_temp; + when 6 => flash_temp <= flashram_data_o; + when 7 => ram_data( 3) <= flashram_data_o & flash_temp; + pwm_write_ii <= '1'; + pwm_addr_ii <= "00011"; + pwm_data_ii <= flashram_data_o & flash_temp; + when 8 => flash_temp <= flashram_data_o; + when 9 => ram_data( 4) <= flashram_data_o & flash_temp; + pwm_write_ii <= '1'; + pwm_addr_ii <= "00100"; + pwm_data_ii <= flashram_data_o & flash_temp; + when 10 => flash_temp <= flashram_data_o; + when 11 => ram_data( 5) <= flashram_data_o & flash_temp; + pwm_write_ii <= '1'; + pwm_addr_ii <= "00101"; + pwm_data_ii <= flashram_data_o & flash_temp; + when 12 => flash_temp <= flashram_data_o; + when 13 => ram_data( 6) <= flashram_data_o & flash_temp; + pwm_write_ii <= '1'; + pwm_addr_ii <= "00110"; + pwm_data_ii <= flashram_data_o & flash_temp; + when 14 => flash_temp <= flashram_data_o; + when 15 => ram_data( 7) <= flashram_data_o & flash_temp; + pwm_write_ii <= '1'; + pwm_addr_ii <= "00111"; + pwm_data_ii <= flashram_data_o & flash_temp; + when 16 => flash_temp <= flashram_data_o; + when 17 => ram_data( 8) <= flashram_data_o & flash_temp; + pwm_write_ii <= '1'; + pwm_addr_ii <= "01000"; + pwm_data_ii <= flashram_data_o & flash_temp; + when 18 => flash_temp <= flashram_data_o; + when 19 => ram_data( 9) <= flashram_data_o & flash_temp; + pwm_write_ii <= '1'; + pwm_addr_ii <= "01001"; + pwm_data_ii <= flashram_data_o & flash_temp; + when 20 => flash_temp <= flashram_data_o; + when 21 => ram_data(10) <= flashram_data_o & flash_temp; + pwm_write_ii <= '1'; + pwm_addr_ii <= "01010"; + pwm_data_ii <= flashram_data_o & flash_temp; + when 22 => flash_temp <= flashram_data_o; + when 23 => ram_data(11) <= flashram_data_o & flash_temp; + pwm_write_ii <= '1'; + pwm_addr_ii <= "01011"; + pwm_data_ii <= flashram_data_o & flash_temp; + when 24 => flash_temp <= flashram_data_o; + when 25 => ram_data(12) <= flashram_data_o & flash_temp; + pwm_write_ii <= '1'; + pwm_addr_ii <= "01100"; + pwm_data_ii <= flashram_data_o & flash_temp; + when 26 => flash_temp <= flashram_data_o; + when 27 => ram_data(13) <= flashram_data_o & flash_temp; + pwm_write_ii <= '1'; + pwm_addr_ii <= "01101"; + pwm_data_ii <= flashram_data_o & flash_temp; + when 28 => flash_temp <= flashram_data_o; + when 29 => ram_data(14) <= flashram_data_o & flash_temp; + pwm_write_ii <= '1'; + pwm_addr_ii <= "01110"; + pwm_data_ii <= flashram_data_o & flash_temp; + when 30 => flash_temp <= flashram_data_o; + when 31 => ram_data(15) <= flashram_data_o & flash_temp; + pwm_write_ii <= '1'; + pwm_addr_ii <= "01111"; + pwm_data_ii <= flashram_data_o & flash_temp; + when others => null; + end case ; + + elsif flash_command = '1' and ufm_bus_ready_out = '1' then + -- save data from registers to UFM + ufm_bus_ready_in <= '1'; + case to_integer ( ufm_databyte_counter ) is + when 0 => flashram_data_i <= ram_data( 0)( 7 downto 0); + when 1 => flashram_data_i <= ram_data( 0)(15 downto 8); + when 2 => flashram_data_i <= ram_data( 1)( 7 downto 0); + when 3 => flashram_data_i <= ram_data( 1)(15 downto 8); + when 4 => flashram_data_i <= ram_data( 2)( 7 downto 0); + when 5 => flashram_data_i <= ram_data( 2)(15 downto 8); + when 6 => flashram_data_i <= ram_data( 3)( 7 downto 0); + when 7 => flashram_data_i <= ram_data( 3)(15 downto 8); + when 8 => flashram_data_i <= ram_data( 4)( 7 downto 0); + when 9 => flashram_data_i <= ram_data( 4)(15 downto 8); + when 10 => flashram_data_i <= ram_data( 5)( 7 downto 0); + when 11 => flashram_data_i <= ram_data( 5)(15 downto 8); + when 12 => flashram_data_i <= ram_data( 6)( 7 downto 0); + when 13 => flashram_data_i <= ram_data( 6)(15 downto 8); + when 14 => flashram_data_i <= ram_data( 7)( 7 downto 0); + when 15 => flashram_data_i <= ram_data( 7)(15 downto 8); + when 16 => flashram_data_i <= ram_data( 8)( 7 downto 0); + when 17 => flashram_data_i <= ram_data( 8)(15 downto 8); + when 18 => flashram_data_i <= ram_data( 9)( 7 downto 0); + when 19 => flashram_data_i <= ram_data( 9)(15 downto 8); + when 20 => flashram_data_i <= ram_data(10)( 7 downto 0); + when 21 => flashram_data_i <= ram_data(10)(15 downto 8); + when 22 => flashram_data_i <= ram_data(11)( 7 downto 0); + when 23 => flashram_data_i <= ram_data(11)(15 downto 8); + when 24 => flashram_data_i <= ram_data(12)( 7 downto 0); + when 25 => flashram_data_i <= ram_data(12)(15 downto 8); + when 26 => flashram_data_i <= ram_data(13)( 7 downto 0); + when 27 => flashram_data_i <= ram_data(13)(15 downto 8); + when 28 => flashram_data_i <= ram_data(14)( 7 downto 0); + when 29 => flashram_data_i <= ram_data(14)(15 downto 8); + when 30 => flashram_data_i <= ram_data(15)( 7 downto 0); + when 31 => flashram_data_i <= ram_data(15)(15 downto 8); + when others => null ; + end case ; + + elsif ram_spi_write = '1' then + ram_data(to_integer(unsigned(ram_spi_addr))) <= ram_spi_data; + end if ; +end process ;