From: Jan Michel <j.michel@gsi.de>
Date: Fri, 10 Aug 2018 09:51:08 +0000 (+0200)
Subject: Updata 4conn and gpin TDC designs
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=98a75fa0b101057c98c77b5b050a454ee761452c;p=trb3.git

Updata 4conn and gpin TDC designs
---

diff --git a/32PinAddOn/config_compile_frankfurt.pl b/32PinAddOn/config_compile_frankfurt.pl
index 8bf794b..d4460fe 100644
--- a/32PinAddOn/config_compile_frankfurt.pl
+++ b/32PinAddOn/config_compile_frankfurt.pl
@@ -1,12 +1,11 @@
 TOPNAME                      => "trb3_periph_32PinAddOn",
 project_path                 => "32PinAddOn",
-lm_license_file_for_synplify => "1702\@jspc29", #"27000\@lxcad01.gsi.de";
-lm_license_file_for_par      => "1702\@jspc29",
+lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
+lm_license_file_for_par      => "1702\@hadeb05",
 lattice_path                 => '/d/jspc29/lattice/diamond/3.7_x64',
 synplify_path                => '/d/jspc29/lattice/synplify/K-2015.09/',
 # synplify_command             => "/d/jspc29/lattice/diamond/3.6_x64/bin/lin64/synpwrap -fg -options",
 # synplify_command             => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp",
-synplify_command             => "ssh -p 52238 jmichel\@cerberus \"cd /home/jmichel/git/trb3/32PinAddOn/workdir; LM_LICENSE_FILE=27000\@lxcad01.gsi.de /opt/synplicity/K-2015.09/bin/synplify_premier_dp -batch ../trb3_periph_32PinAddOn.prj\" #",
 
 
 nodelist_file                => '../nodes_lxhadeb07.txt',
@@ -19,3 +18,9 @@ include_GBE                  => 0,
 #Report settings
 firefox_open                 => 0,
 twr_number_of_errors         => 20,
+
+
+Familyname  => 'LatticeECP3',
+Devicename  => 'LFE3-150EA',
+Package     => 'FPBGA672',
+Speedgrade  => '8',
diff --git a/ADA_Addon/config.vhd b/ADA_Addon/config.vhd
index 30ec9d7..cd47b33 100644
--- a/ADA_Addon/config.vhd
+++ b/ADA_Addon/config.vhd
@@ -12,9 +12,9 @@ package config is
 --TDC settings
   constant FPGA_TYPE               : integer  := 3;  --3: ECP3, 5: ECP5
   constant NUM_TDC_MODULES         : integer range 1 to 4  := 1;  -- number of tdc modules to implement
-  constant NUM_TDC_CHANNELS        : integer range 1 to 65 := 33;  -- number of tdc channels per module
+  constant NUM_TDC_CHANNELS        : integer range 1 to 65 := 17;  -- number of tdc channels per module
   constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6  := 4;  --the nearest power of two, for convenience reasons 
-  constant DOUBLE_EDGE_TYPE        : integer range 0 to 3  := 1;  --double edge type:  0, 1, 2,  3
+  constant DOUBLE_EDGE_TYPE        : integer range 0 to 3  := 3;  --double edge type:  0, 1, 2,  3
   -- 0: single edge only,
   -- 1: same channel,
   -- 2: alternating channels,
@@ -28,11 +28,11 @@ package config is
   -- 13: Debug - single fine time and the chain for the 0x3ff hits
   -- 14: Debug - single fine time and the ROM addresses for the two transitions
   -- 15: Debug - complete carry chain dump
-  constant USE_PINOUT : integer := 1; --1: normal, 3: every 4th channel (HPTDC)
+  constant USE_PINOUT : integer := 3; --1: normal, 3: every 4th channel (HPTDC)
   
   
   constant EVENT_BUFFER_SIZE       : integer range 9 to 13 := 13; -- size of the event buffer, 2**N
-  constant EVENT_MAX_SIZE          : integer := 4096;             --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2
+  constant EVENT_MAX_SIZE          : integer := 2048;             --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2
 
 --Include SPI on AddOn connector
   constant INCLUDE_UART           : integer  := c_YES;
@@ -113,5 +113,5 @@ end function;
   constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_125_MHZ);
   constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_125_MHZ);
   
-  constant INCLUDED_FEATURES : std_logic_vector := generateIncludedFeatures;  
+  constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures;  
 end package body;
diff --git a/gpin/compile.pl b/gpin/compile.pl
index 4456748..8a19aa6 120000
--- a/gpin/compile.pl
+++ b/gpin/compile.pl
@@ -1 +1 @@
-../scripts/compile.pl
\ No newline at end of file
+../../trb3sc/scripts/compile.pl
\ No newline at end of file
diff --git a/gpin/config.vhd b/gpin/config.vhd
index 7fb4f41..be40ddf 100644
--- a/gpin/config.vhd
+++ b/gpin/config.vhd
@@ -10,10 +10,11 @@ package config is
 ------------------------------------------------------------------------------
 
 --TDC settings
+  constant FPGA_TYPE               : integer  := 3;  --3: ECP3, 5: ECP5
   constant NUM_TDC_MODULES         : integer range 1 to 4  := 1;  -- number of tdc modules to implement
-  constant NUM_TDC_CHANNELS        : integer range 1 to 65 := 5; -- number of tdc channels per module
+  constant NUM_TDC_CHANNELS        : integer range 1 to 65 := 25; -- number of tdc channels per module
   constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6  := 5;  --the nearest power of two, for convenience reasons 
-  constant DOUBLE_EDGE_TYPE        : integer range 0 to 3  := 2;  --double edge type:  0, 1, 2,  3
+  constant DOUBLE_EDGE_TYPE        : integer range 0 to 3  := 3;  --double edge type:  0, 1, 2,  3
   -- 0: single edge only,
   -- 1: same channel,
   -- 2: alternating channels,
@@ -32,28 +33,36 @@ package config is
   constant EVENT_MAX_SIZE          : integer := 4096;             --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2
   
 --Include SPI on AddOn connector
-  constant INCLUDE_SPI : integer := c_NO;  --there is no spi connector on the addon
+  constant INCLUDE_UART           : integer  := c_YES;
+  constant INCLUDE_SPI            : integer  := c_YES;
+  constant INCLUDE_LCD            : integer  := c_NO;
+  constant INCLUDE_DEBUG_INTERFACE: integer  := c_YES;
+  --constant SPI_FOR_PADI : integer := c_NO;  -- YES: PADI SPI    NO: Normal SPI
 
 --Add logic to generate configurable trigger signal from input signals.
   constant INCLUDE_TRIGGER_LOGIC : integer := c_YES;
   constant INCLUDE_STATISTICS    : integer := c_YES;  --Do histos of all inputs
   constant PHYSICAL_INPUTS       : integer := 24;  --number of inputs connected
+  constant TRIG_GEN_OUTPUT_NUM   : integer := 4;
+  constant MONITOR_INPUT_NUM     : integer := PHYSICAL_INPUTS+TRIG_GEN_OUTPUT_NUM;    
+  constant TRIG_GEN_INPUT_NUM    : integer := PHYSICAL_INPUTS;
   constant USE_SINGLE_FIFO       : integer := c_YES;  -- single fifo for statistics
-
+  
 --Run wih 125 MHz instead of 100 MHz, use received clock from serdes or external clock input
-  constant USE_125_MHZ       : integer := c_NO;  --not implemented yet!  
-  constant USE_RXCLOCK       : integer := c_NO;  --not implemented yet!
-  constant USE_EXTERNALCLOCK : integer := c_NO;  --not implemented yet!
+  constant USE_125_MHZ               : integer    := c_NO;  --not implemented yet!  
+  constant USE_RXCLOCK               : integer    := c_NO;  --not implemented yet!
+  constant USE_EXTERNALCLOCK         : integer    := c_NO;  --not implemented yet!
 
 --Address settings
-  constant INIT_ADDRESS           : std_logic_vector := x"F305";
+  constant INIT_ADDRESS           : std_logic_vector := x"F306";
   constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"4a";
 
 ------------------------------------------------------------------------------
 --End of design configuration
 ------------------------------------------------------------------------------
 
-
+  type data_t is array (0 to 1023) of std_logic_vector(7 downto 0);
+  constant LCD_DATA : data_t := (others => (others => '0'));
 
 ------------------------------------------------------------------------------
 --Select settings by configuration 
diff --git a/gpin/config_compile.pl b/gpin/config_compile.pl
index 67b86a0..52cd2ef 120000
--- a/gpin/config_compile.pl
+++ b/gpin/config_compile.pl
@@ -1 +1 @@
-config_compile_gsi.pl
\ No newline at end of file
+config_compile_frankfurt.pl
\ No newline at end of file
diff --git a/gpin/config_compile_frankfurt.pl b/gpin/config_compile_frankfurt.pl
new file mode 100644
index 0000000..ad46ca4
--- /dev/null
+++ b/gpin/config_compile_frankfurt.pl
@@ -0,0 +1,26 @@
+TOPNAME                      => "trb3_periph_gpin",
+project_path                 => "gpin",
+lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
+lm_license_file_for_par      => "1702\@hadeb05.gsi.de",
+lattice_path                 => '/d/jspc29/lattice/diamond/3.9_x64',
+synplify_path                => '/d/jspc29/lattice/synplify/L-2016.09-1/',
+# synplify_command             => "/d/jspc29/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options",
+#synplify_command             => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp",
+
+nodelist_file                => 'nodelist_frankfurt.txt',
+par_options                  => '../../base/trb3_periph.p2t',
+# pinout_file                  => 'trb3_periph_ada',
+
+#Include only necessary lpf files
+#pinout_file                  => '', #name of pin-out file, if not equal TOPNAME
+include_TDC                  => 1,
+include_GBE                  => 0,
+
+#Report settings
+firefox_open                 => 0,
+twr_number_of_errors         => 20,
+
+Familyname  => 'LatticeECP3',
+Devicename  => 'LFE3-150EA',
+Package     => 'FPBGA672',
+Speedgrade  => '8',
diff --git a/gpin/trb3_periph_gpin.p2t b/gpin/par.p2t
similarity index 100%
rename from gpin/trb3_periph_gpin.p2t
rename to gpin/par.p2t
diff --git a/gpin/trb3_periph_gpin.prj b/gpin/trb3_periph_gpin.prj
index a162e46..64aef30 100644
--- a/gpin/trb3_periph_gpin.prj
+++ b/gpin/trb3_periph_gpin.prj
@@ -48,9 +48,7 @@ impl -active "workdir"
 ####################
 
 
-
-#add_file options
-
+#project files
 add_file -vhdl -lib work "workdir/version.vhd"
 add_file -vhdl -lib work "config.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
@@ -86,15 +84,15 @@ add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd"
 
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd"
 add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd"
 add_file -vhdl -lib work "../../trbnet/basics/ram.vhd"
 add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd"
 add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd"
 add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd"
 add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd"
 add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd"
 add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd"
 add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd"
@@ -105,18 +103,22 @@ add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd"
 add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd"
 add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
 add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd"
 add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
 add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd"
 add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
-add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd"
-add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd"
 add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd"
 
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" 
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd"
@@ -129,49 +131,46 @@ add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_9x2k_oreg.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd"
 
 add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd"
 
 add_file -vhdl -lib work "../base/cores/pll_in200_out100.vhd"
-add_file -vhdl -lib work "../base/code/input_to_trigger_logic.vhd"
+add_file -vhdl -lib work "../base/code/input_to_trigger_logic_record.vhd"
 add_file -vhdl -lib work "../base/code/input_statistics.vhd"
 add_file -vhdl -lib work "../base/code/sedcheck.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd"
+add_file -vhdl -lib work "../base/code/trb3_tools.vhd"
 
 
-#add_file -vhdl -lib work "tdc_release/Adder_304.vhd"
 add_file -vhdl -lib work "tdc_release/tdc_components.vhd"
 add_file -vhdl -lib work "tdc_release/bit_sync.vhd"
-#add_file -vhdl -lib work "tdc_release/BusHandler.vhd"
 add_file -vhdl -lib work "tdc_release/BusHandler_record.vhd"
 add_file -vhdl -lib work "tdc_release/Channel.vhd"
 add_file -vhdl -lib work "tdc_release/Channel_200.vhd"
-#add_file -vhdl -lib work "tdc_release/Encoder_304_Bit.vhd"
 add_file -vhdl -lib work "tdc_release/Encoder_288_Bit.vhd"
+add_file -vhdl -lib work "tdc_release/fallingEdgeDetect.vhd"
+add_file -vhdl -lib work "tdc_release/hit_mux.vhd"
 add_file -vhdl -lib work "tdc_release/LogicAnalyser.vhd"
-#add_file -vhdl -lib work "tdc_release/Readout.vhd"
-add_file -vhdl -lib work "tdc_release/Readout_record.vhd"
+add_file -vhdl -lib work "tdc_release/risingEdgeDetect.vhd"
 add_file -vhdl -lib work "tdc_release/ROM_encoder_ecp3.vhd"
 add_file -vhdl -lib work "tdc_release/ShiftRegisterSISO.vhd"
 add_file -vhdl -lib work "tdc_release/Stretcher_A.vhd"
 add_file -vhdl -lib work "tdc_release/Stretcher_B.vhd"
 add_file -vhdl -lib work "tdc_release/Stretcher.vhd"
-#add_file -vhdl -lib work "tdc_release/TDC.vhd"
 add_file -vhdl -lib work "tdc_release/TDC_record.vhd"
-add_file -vhdl -lib work "tdc_release/TriggerHandler.vhd"
 add_file -vhdl -lib work "tdc_release/up_counter.vhd"
-add_file -vhdl -lib work "tdc_release/fallingEdgeDetect.vhd"
-add_file -vhdl -lib work "tdc_release/risingEdgeDetect.vhd"
-add_file -vhdl -lib work "tdc_release/hit_mux.vhd"
-
-add_file -vhdl -lib work "../../tdc/base/cores/ecp3/PLL/pll_in125_out33.vhd"
 add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.vhd"
 add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x128_OutReg.vhd"
 add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x64_OutReg.vhd"
@@ -179,6 +178,16 @@ add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x32_OutReg.vh
 add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x128_OutReg.vhd"
 add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x64_OutReg.vhd"
 add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x32_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/PLL/pll_in125_out33.vhd"
+
+#if {$TDC_DATA_FORMAT == 0 | $TDC_DATA_FORMAT == 1 | $TDC_DATA_FORMAT == 14} {
+add_file -vhdl -lib work "tdc_release/Readout_record.vhd"
+add_file -vhdl -lib work "tdc_release/TriggerHandler.vhd"
+#}
+#if {$TDC_DATA_FORMAT == 13 | $TDC_DATA_FORMAT == 15} {
+#add_file -vhdl -lib work "tdc_release/Readout_record_noDecode.vhd"
+#add_file -vhdl -lib work "tdc_release/TriggerHandler_noDecode.vhd"
+#}
 
 add_file -vhdl -lib work "trb3_periph_gpin.vhd"
 
diff --git a/nxyter/config_compile_frankfurt.pl b/nxyter/config_compile_frankfurt.pl
index 9465dc1..2e834b0 100644
--- a/nxyter/config_compile_frankfurt.pl
+++ b/nxyter/config_compile_frankfurt.pl
@@ -1,4 +1,4 @@
-TOPNAME                      => "trb3_periph_blank",
+TOPNAME                      => "trb3_periph_nxyter",
 lm_license_file_for_synplify => "1702\@jspc29", #"27000\@lxcad01.gsi.de";
 lm_license_file_for_par      => "1702\@jspc29",
 lattice_path                 => '/d/jspc29/lattice/diamond/3.6_x64',
@@ -7,7 +7,7 @@ synplify_command             => "/d/jspc29/lattice/diamond/3.6_x64/bin/lin64/syn
 #synplify_command             => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp",
 
 nodelist_file                => 'nodes_frankfurt.txt',
-pinout_file                  => 'trb3_periph_ada',
+pinout_file                  => 'trb3_periph_nxyter',
 
 #Include only necessary lpf files
 #pinout_file                  => '', #name of pin-out file, if not equal TOPNAME
@@ -21,4 +21,4 @@ twr_number_of_errors         => 20,
 Familyname  => 'LatticeECP3',
 Devicename  => 'LFE3-150EA',
 Package     => 'FPBGA672',
-Speedgrade  => '8',
\ No newline at end of file
+Speedgrade  => '8',
diff --git a/trb3_gbe/config_compile_frankfurt.pl b/trb3_gbe/config_compile_frankfurt.pl
index 511871c..7605bb1 100644
--- a/trb3_gbe/config_compile_frankfurt.pl
+++ b/trb3_gbe/config_compile_frankfurt.pl
@@ -1,7 +1,7 @@
 TOPNAME                      => "trb3_central_gbe",
 lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
 lm_license_file_for_par      => "1702\@hadeb05.gsi.de",
-lattice_path                 => '/d/jspc29/lattice/diamond/3.8_x64',
+lattice_path                 => '/d/jspc29/lattice/diamond/3.9_x64',
 synplify_path                => '/d/jspc29/lattice/synplify/L-2016.09-1/',
 
 #synplify_command             => "/opt/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options",
diff --git a/trb3_gbe/trb3_central_gbe.vhd b/trb3_gbe/trb3_central_gbe.vhd
index dca233e..618a9b4 100644
--- a/trb3_gbe/trb3_central_gbe.vhd
+++ b/trb3_gbe/trb3_central_gbe.vhd
@@ -414,12 +414,12 @@ gen_uplink : if USE_125_MHZ = c_NO generate
       CLK_RX_HALF_OUT    => open,
       CLK_RX_FULL_OUT    => open,
       --SFP Connection
-      SD_RXD_P_IN        => SFP_RX_P(1),
-      SD_RXD_N_IN        => SFP_RX_N(1),
-      SD_TXD_P_OUT       => SFP_TX_P(1),
-      SD_TXD_N_OUT       => SFP_TX_N(1),
-      SD_REFCLK_P_IN     => open,
-      SD_REFCLK_N_IN     => open,
+--       SD_RXD_P_IN        => SFP_RX_P(1),
+--       SD_RXD_N_IN        => SFP_RX_N(1),
+--       SD_TXD_P_OUT       => SFP_TX_P(1),
+--       SD_TXD_N_OUT       => SFP_TX_N(1),
+--       SD_REFCLK_P_IN     => open,
+--       SD_REFCLK_N_IN     => open,
       SD_PRSNT_N_IN      => SFP_MOD0(1),
       SD_LOS_IN          => SFP_LOS(1),
       SD_TXDIS_OUT       => SFP_TXDIS(1),
diff --git a/wasa/compile.pl b/wasa/compile.pl
index 4456748..8a19aa6 120000
--- a/wasa/compile.pl
+++ b/wasa/compile.pl
@@ -1 +1 @@
-../scripts/compile.pl
\ No newline at end of file
+../../trb3sc/scripts/compile.pl
\ No newline at end of file
diff --git a/wasa/config.vhd b/wasa/config.vhd
index d4daa4d..9968ce0 100644
--- a/wasa/config.vhd
+++ b/wasa/config.vhd
@@ -11,15 +11,16 @@ package config is
 ------------------------------------------------------------------------------
 
 --TDC settings
+  constant FPGA_TYPE               : integer  := 3;  --3: ECP3, 5: ECP5
   constant NUM_TDC_MODULES         : integer range 1 to 4  := 1;  -- number of tdc modules to implement
-  constant NUM_TDC_CHANNELS        : integer range 1 to 65 := 5;  -- number of tdc channels per module
-  constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6  := 6;  --the nearest power of two, for convenience reasons 
+  constant NUM_TDC_CHANNELS        : integer range 1 to 65 := 33;  -- number of tdc channels per module
+  constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6  := 5;  --the nearest power of two, for convenience reasons 
   constant DOUBLE_EDGE_TYPE        : integer range 0 to 3  := 3;  --double edge type:  0, 1, 2,  3
   -- 0: single edge only,
   -- 1: same channel,
   -- 2: alternating channels,
   -- 3: same channel with stretcher
-  constant RING_BUFFER_SIZE        : integer range 0 to 7  := 0;  --ring buffer size
+  constant RING_BUFFER_SIZE        : integer range 0 to 7  := 7;  --ring buffer size
   -- mode:  0,  1,  2,   3,   7
   -- size: 32, 64, 96, 128, dyn
   constant TDC_DATA_FORMAT         : integer range 0 to 15 := 0;  --type of data format for the TDC
@@ -29,19 +30,25 @@ package config is
   -- 14: Debug - single fine time and the ROM addresses for the two transitions
   -- 15: Debug - complete carry chain dump
 
-  constant EVENT_BUFFER_SIZE       : integer range 9 to 13 := 11; -- size of the event buffer, 2**N
+  constant EVENT_BUFFER_SIZE       : integer range 9 to 13 := 13; -- size of the event buffer, 2**N
   constant EVENT_MAX_SIZE          : integer := 1024;             --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2
 
 --Use only every second input channel (mask slow channels from padiwa amps)
   constant USE_PADIWA_FAST_ONLY : integer := c_NO;
 
 --Include SPI on AddOn connector
-  constant INCLUDE_SPI : integer := c_YES;
+  constant INCLUDE_UART           : integer  := c_YES;
+  constant INCLUDE_SPI            : integer  := c_YES;
+  constant INCLUDE_LCD            : integer  := c_NO;
+  constant INCLUDE_DEBUG_INTERFACE: integer  := c_YES;
 
 --Add logic to generate configurable trigger signal from input signals.
   constant INCLUDE_TRIGGER_LOGIC : integer := c_YES;
   constant INCLUDE_STATISTICS    : integer := c_YES;  --Do histos of all inputs
-  constant PHYSICAL_INPUTS       : integer := 16;  --number of inputs connected
+  constant PHYSICAL_INPUTS       : integer := 48;  --number of inputs connected
+  constant TRIG_GEN_OUTPUT_NUM   : integer := 4;
+  constant MONITOR_INPUT_NUM     : integer := PHYSICAL_INPUTS+TRIG_GEN_OUTPUT_NUM;    
+  constant TRIG_GEN_INPUT_NUM    : integer := PHYSICAL_INPUTS;
   constant USE_SINGLE_FIFO       : integer := c_YES;  -- single fifo for statistics
 
 --Run wih 125 MHz instead of 100 MHz, use received clock from serdes or external clock input
@@ -57,7 +64,8 @@ package config is
 --End of design configuration
 ------------------------------------------------------------------------------
 
-
+  type data_t is array (0 to 1023) of std_logic_vector(7 downto 0);
+  constant LCD_DATA : data_t := (others => (others => '0'));
 
 ------------------------------------------------------------------------------
 --Select settings by configuration 
diff --git a/wasa/config_compile.pl b/wasa/config_compile.pl
index 67b86a0..52cd2ef 120000
--- a/wasa/config_compile.pl
+++ b/wasa/config_compile.pl
@@ -1 +1 @@
-config_compile_gsi.pl
\ No newline at end of file
+config_compile_frankfurt.pl
\ No newline at end of file
diff --git a/wasa/config_compile_frankfurt.pl b/wasa/config_compile_frankfurt.pl
index 877b174..b2e3121 100644
--- a/wasa/config_compile_frankfurt.pl
+++ b/wasa/config_compile_frankfurt.pl
@@ -1,9 +1,10 @@
-TOPNAME                      => "trb3sc_basic",
-lm_license_file_for_synplify => "1702\@hadeb05.gsi.de", #"27000\@lxcad01.gsi.de";
+TOPNAME                      => "trb3_periph_padiwa",
+project_path                 => "wasa",
+lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
 lm_license_file_for_par      => "1702\@hadeb05.gsi.de",
-lattice_path                 => '/d/jspc29/lattice/diamond/3.5_x64',
-synplify_path                => '/d/jspc29/lattice/synplify/J-2014.09-SP2/',
-synplify_command             => "/d/jspc29/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options",
+lattice_path                 => '/d/jspc29/lattice/diamond/3.9_x64',
+synplify_path                => '/d/jspc29/lattice/synplify/L-2016.09-1/',
+
 #synplify_command             => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp",
 
 nodelist_file                => 'nodelist_frankfurt.txt',
@@ -11,10 +12,15 @@ nodelist_file                => 'nodelist_frankfurt.txt',
 
 #Include only necessary lpf files
 #pinout_file                  => '', #name of pin-out file, if not equal TOPNAME
-include_TDC                  => 0,
+include_TDC                  => 1,
 include_GBE                  => 0,
 
 #Report settings
 firefox_open                 => 0,
 twr_number_of_errors         => 20,
 
+
+Familyname  => 'LatticeECP3',
+Devicename  => 'LFE3-150EA',
+Package     => 'FPBGA672',
+Speedgrade  => '8',
diff --git a/wasa/trb3_periph_padiwa.p2t b/wasa/par.p2t
similarity index 100%
rename from wasa/trb3_periph_padiwa.p2t
rename to wasa/par.p2t
diff --git a/wasa/trb3_periph_padiwa.prj b/wasa/trb3_periph_padiwa.prj
index da1228a..a24e88c 100644
--- a/wasa/trb3_periph_padiwa.prj
+++ b/wasa/trb3_periph_padiwa.prj
@@ -49,10 +49,7 @@ impl -active "workdir"
 
 ####################
 
-
-
-#add_file options
-
+#project files
 add_file -vhdl -lib work "workdir/version.vhd"
 add_file -vhdl -lib work "config.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
@@ -88,15 +85,15 @@ add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd"
 
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd"
 add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd"
 add_file -vhdl -lib work "../../trbnet/basics/ram.vhd"
 add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd"
 add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd"
 add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd"
 add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd"
 add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd"
 add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd"
 add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd"
@@ -107,18 +104,22 @@ add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd"
 add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd"
 add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
 add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd"
 add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
 add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd"
 add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
-add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd"
-add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd"
 add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd"
 
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" 
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd"
@@ -131,22 +132,27 @@ add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_9x2k_oreg.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd"
 
 add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd"
 
 add_file -vhdl -lib work "../base/cores/pll_in200_out100.vhd"
-add_file -vhdl -lib work "../base/code/input_to_trigger_logic.vhd"
+add_file -vhdl -lib work "../base/code/input_to_trigger_logic_record.vhd"
 add_file -vhdl -lib work "../base/code/input_statistics.vhd"
 add_file -vhdl -lib work "../base/code/sedcheck.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd"
+add_file -vhdl -lib work "../base/code/trb3_tools.vhd"
 
 
 add_file -vhdl -lib work "tdc_release/tdc_components.vhd"
@@ -175,6 +181,18 @@ add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x64_OutReg.vhd"
 add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x32_OutReg.vhd"
 add_file -vhdl -lib work "../../tdc/base/cores/ecp3/PLL/pll_in125_out33.vhd"
 
+add_file -vhdl -lib work "../../triggerlogic/trigger_coin.vhd"
+add_file -vhdl -lib work "../../triggerlogic/trigger_delay.vhd"
+add_file -vhdl -lib work "../../triggerlogic/trigger_edgedetect.vhd"
+add_file -vhdl -lib work "../../triggerlogic/trigger_enable.vhd"
+add_file -vhdl -lib work "../../triggerlogic/trigger_inverter.vhd"
+add_file -vhdl -lib work "../../triggerlogic/trigger_logic.vhd"
+add_file -vhdl -lib work "../../triggerlogic/trigger_merge.vhd"
+add_file -vhdl -lib work "../../triggerlogic/trigger_stretch.vhd"
+add_file -vhdl -lib work "../../triggerlogic/cores/delay_shift_reg.vhd"
+
+
+
 if {$TDC_DATA_FORMAT == 0 | $TDC_DATA_FORMAT == 1 | $TDC_DATA_FORMAT == 14} {
 add_file -vhdl -lib work "tdc_release/Readout_record.vhd"
 add_file -vhdl -lib work "tdc_release/TriggerHandler.vhd"