From: Manuel Penschuck <manuel.penschuck@stud.uni-frankfurt.de>
Date: Sun, 10 Aug 2014 19:09:36 +0000 (+0200)
Subject: Readout seems to work with TrbNet test-pattern generator
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=98c78fde5f42059a923b784429af1b798d63b897;p=trb3.git

Readout seems to work with TrbNet test-pattern generator
---

diff --git a/cbmnet/code/cbmnet_interface_pkg.vhd b/cbmnet/code/cbmnet_interface_pkg.vhd
index 6809235..d0aa0bf 100644
--- a/cbmnet/code/cbmnet_interface_pkg.vhd
+++ b/cbmnet/code/cbmnet_interface_pkg.vhd
@@ -468,7 +468,7 @@ package cbmnet_interface_pkg is
          RESET_IN : in std_logic; 
 
          -- fifo 
-         FIFO_DATA_IN   : in std_logic_vector(15 downto 0);
+         FIFO_DATA_IN   : in std_logic_vector(17 downto 0);
          FIFO_DEQUEUE_OUT : out std_logic;
          FIFO_PACKET_COMPLETE_IN : in std_logic;  
          FIFO_PACKET_COMPLETE_ACK_OUT : out std_logic;
diff --git a/cbmnet/code/cbmnet_readout.vhd b/cbmnet/code/cbmnet_readout.vhd
index 1a113e7..4baae75 100644
--- a/cbmnet/code/cbmnet_readout.vhd
+++ b/cbmnet/code/cbmnet_readout.vhd
@@ -75,7 +75,6 @@ architecture cbmnet_readout_arch of CBMNET_READOUT is
    signal fifo_wenqueue_i         : std_logic;
    signal fifo_wpacket_complete_i : std_logic;
    signal fifo_wfull_i            : std_logic;
-   signal debug_fifo_i            : std_logic_vector(31 downto 0);
    
    signal dec_evt_info_i   : std_logic_vector(31 downto 0);
    signal dec_length_i     : std_logic_vector(15 downto 0);
@@ -116,9 +115,11 @@ architecture cbmnet_readout_arch of CBMNET_READOUT is
    signal stat_link_inactive_i      : unsigned(31 downto 0);   
 
 -- debug
-   signal debug_decorder_i : std_logic_vector(31 downto 0);
-   signal debug_packer_i : std_logic_vector(31 downto 0);
-   signal debug_tx_fsm_i : std_logic_vector(31 downto 0);
+   signal debug_decorder_i     : std_logic_vector(31 downto 0);
+   signal debug_packer_i       : std_logic_vector(31 downto 0);
+   signal debug_frame_packer_i : std_logic_vector(31 downto 0);
+   signal debug_fifo_i         : std_logic_vector(31 downto 0);
+   signal debug_obuf_i         : std_logic_vector(31 downto 0);
 
 -- slow control and configuration   
    signal regio_data_status_i : std_logic_vector(31 downto 0);
@@ -229,10 +230,7 @@ begin
    
 
    THE_READOUT_FIFO: CBMNET_READOUT_FIFO 
-   generic map (
-      ADDR_WIDTH => 12, -- 8kb ..
-      WATERMARK  => 8
-   ) port map (
+   port map (
       -- write port
       WCLK_IN   => CLK_IN,   -- in std_logic; -- not faster than rclk_in
       WRESET_IN => reset_combined_i, -- in std_logic;
@@ -266,7 +264,7 @@ begin
       RESET_IN => reset_combined_i, -- in std_logic; 
 
       -- fifo 
-      FIFO_DATA_IN                 => fifo_rdata_i(15 downto 0), -- in std_logic_vector(15 downto 0);
+      FIFO_DATA_IN                 => fifo_rdata_i, -- in std_logic_vector(15 downto 0);
       FIFO_DEQUEUE_OUT             => fifo_rdequeue_i, -- out std_logic;
       FIFO_PACKET_COMPLETE_IN      => fifo_rpacket_complete_i, -- in std_logic;  
       FIFO_PACKET_COMPLETE_ACK_OUT => fifo_rpacket_complete_ack_i, -- out std_logic;
@@ -277,7 +275,7 @@ begin
       CBMNET_END_OUT   => frame_packer_end_i,   -- out std_logic;
       CBMNET_DATA_OUT  => frame_packer_data_i,   -- out std_logic_vector(15 downto 0)
       
-      DEBUG_OUT => debug_tx_fsm_i
+      DEBUG_OUT => debug_frame_packer_i
    );
    
    THE_OBUF: CBMNET_READOUT_OBUF 
@@ -297,7 +295,7 @@ begin
       CBMNET_END_OUT   => CBMNET_DATA2SEND_END_OUT, -- out std_logic;
       CBMNET_DATA_OUT  => CBMNET_DATA2SEND_DATA_OUT, -- out std_logic_vector(15 downto 0);
       
-      DEBUG_OUT => open -- out std_logic_vector(31 downto 0)
+      DEBUG_OUT => debug_obuf_i -- out std_logic_vector(31 downto 0)
    );
    
 ----------------------------------------
@@ -380,13 +378,14 @@ begin
          -- debug only ports
          when 16#09# => regio_data_status_i <= debug_decorder_i;
          when 16#0a# => regio_data_status_i <= debug_packer_i;
-         when 16#0b# => regio_data_status_i <= debug_tx_fsm_i;
+         when 16#0b# => regio_data_status_i <= debug_frame_packer_i;
          when 16#0c# => regio_data_status_i(1 downto 0) <= fifo_wfull_i & fifo_rpacket_complete_i;
          when 16#0d# => regio_data_status_i <= HUB_CTS_INFORMATION_IN & HUB_CTS_CODE_IN & HUB_CTS_NUMBER_IN;
          when 16#0e# => regio_data_status_i <= dec_evt_info_i;
          when 16#0f# => regio_data_status_i <= dec_source_i & dec_length_i;
          
          when 16#10# => regio_data_status_i <= debug_fifo_i;
+         when 16#11# => regio_data_status_i <= debug_obuf_i;
          
          when others => regio_unkown_address_i <= REGIO_READ_ENABLE_IN;
       end case;
diff --git a/cbmnet/code/cbmnet_readout_event_packer.vhd b/cbmnet/code/cbmnet_readout_event_packer.vhd
deleted file mode 100644
index 4b804d4..0000000
--- a/cbmnet/code/cbmnet_readout_event_packer.vhd
+++ /dev/null
@@ -1,168 +0,0 @@
-library ieee;
-   use ieee.std_logic_1164.all;
-   use ieee.numeric_std.all;
-
-entity CBMNET_READOUT_EVENT_PACKER is
-   port (
-   -- TrbNet
-      CLK_IN   : in std_logic;
-      RESET_IN : in std_logic;
-
-      -- connect to hub
-      HUB_CTS_NUMBER_IN              : in  std_logic_vector (15 downto 0);
-      HUB_CTS_CODE_IN                : in  std_logic_vector (7  downto 0);
-      HUB_CTS_INFORMATION_IN         : in  std_logic_vector (7  downto 0);
-      HUB_CTS_READOUT_TYPE_IN        : in  std_logic_vector (3  downto 0);
-      GBE_CTS_STATUS_BITS_IN         : in  std_logic_vector (31 downto 0);
-      
-      
-      -- connect to decoder
-      DEC_EVT_INFO_IN                : in  std_logic_vector(31 downto 0);
-      DEC_LENGTH_IN                  : in  std_logic_vector(15 downto 0);
-      DEC_SOURCE_IN                  : in  std_logic_vector(15 downto 0);
-      DEC_DATA_IN                    : in  std_logic_vector(15 downto 0);
-      DEC_DATA_READY_IN              : in  std_logic;
-      DEC_ACTIVE_IN                  : in  std_logic;
-      DEC_ERROR_IN                   : in  std_logic;
-      
-      DEC_DATA_READ_OUT              : out std_logic;
-      DEC_RESET_OUT                  : out std_logic;
-
-      -- connect to fifo
-      WADDR_STORE_OUT  : out std_logic;
-      WADDR_RESTORE_OUT: out std_logic;
-      WDATA_OUT        : out std_logic_vector(17 downto 0);
-      WENQUEUE_OUT     : out std_logic;
-      WPACKET_COMPLETE_OUT: out std_logic;
-      WFULL_IN         : in  std_logic;
-      
-      DEBUG_OUT                      : out std_logic_vector(31 downto 0)
-   );
-end entity;
-
-architecture cbmnet_readout_event_packer_arch of CBMNET_READOUT_EVENT_PACKER is
-   type FSM_STATES_T is (
-      WAIT_FOR_IDLE, IDLE, 
-      HDR_SIZE_H, HDR_SIZE_L, 
-      HDR_DECODING_H, HDR_DECODING_L,
-      HDR_ID_H, HDR_ID_L,
-      HDR_NUMBER_H, HDR_NUMBER_L,
-      PAYLOAD,
-      TRL_TRAILER_H, TRL_TRAILER_L,
-      TRL_STATUS_H, TRL_STATUS_L
-   );
-   
-   signal fsm_i : FSM_STATES_T;
-   signal header_data_i : std_logic_vector(15 downto 0);
-   signal header_enqueue_i : std_logic;
-   signal copy_payload_i : std_logic;
-   
-   signal data_read_i, data_read_delayed_i : std_logic;
-begin
-   THE_PACKER: process is
-   begin
-      wait until rising_edge(CLK_IN);
-      
-      WADDR_STORE_OUT <= '0';
-      WADDR_RESTORE_OUT <= '0';
-      DEC_RESET_OUT <= '0';    
-      copy_payload_i <= '0';
-      header_data_i <= (others => '-');
-      header_enqueue_i <= '0';
-      WPACKET_COMPLETE_OUT <= '0';
-      
-      if RESET_IN='1' then
-         fsm_i <= WAIT_FOR_IDLE;
-       
-      elsif fsm_i /= IDLE and (DEC_ERROR_IN = '1' or WFULL_IN = '1') then
-         WADDR_RESTORE_OUT <= '1';
-         DEC_RESET_OUT <= '1';
-         fsm_i <= WAIT_FOR_IDLE;
-         
-      else
-         case(fsm_i) is
-            when WAIT_FOR_IDLE =>
-               if DEC_ACTIVE_IN='0' then
-                  fsm_i <= IDLE;
-               end if;
-         
-            when IDLE =>
-               if DEC_ACTIVE_IN='1' then
-                  WADDR_STORE_OUT <= '1';
-                  fsm_i <= HDR_SIZE_H;
-               end if;
-               
-            when HDR_SIZE_H =>
-               header_data_i <= x"0000";
-               header_enqueue_i <= '1';
-               fsm_i <= HDR_SIZE_L;
-            when HDR_SIZE_L =>
-               header_data_i <= STD_LOGIC_VECTOR(UNSIGNED(DEC_LENGTH_IN) + TO_UNSIGNED(16+8, 16)); -- 8 words of SE-Hdr and 4 words for SE-trailer 
-               header_enqueue_i <= '1';
-               fsm_i <= HDR_DECODING_H;
-
-            when HDR_DECODING_H =>
-               header_data_i <= x"0003";
-               header_enqueue_i <= '1';
-               fsm_i <= HDR_DECODING_L;
-            when HDR_DECODING_L =>
-               header_data_i <= x"000" & HUB_CTS_READOUT_TYPE_IN;
-               header_enqueue_i <= '1';
-               fsm_i <= HDR_ID_H;
-
-            when HDR_ID_H =>
-               header_data_i <= x"0000";
-               header_enqueue_i <= '1';
-               fsm_i <= HDR_ID_L;
-            when HDR_ID_L =>
-               header_data_i <= x"beaf";
-               header_enqueue_i <= '1';
-               fsm_i <= HDR_NUMBER_H;
-
-            when HDR_NUMBER_H =>
-               header_data_i <= x"00" & HUB_CTS_NUMBER_IN(15 downto 8);
-               header_enqueue_i <= '1';
-               fsm_i <= HDR_NUMBER_L;
-            when HDR_NUMBER_L =>
-               header_data_i <= HUB_CTS_NUMBER_IN(7 downto 0) & HUB_CTS_CODE_IN;
-               header_enqueue_i <= '1';
-               fsm_i <= PAYLOAD;
-
-            when PAYLOAD =>
-               if DEC_ACTIVE_IN = '0' then
-                  fsm_i <= TRL_TRAILER_H;
-               else
-                  copy_payload_i <= '1';
-               end if;
-               
-            when TRL_TRAILER_H =>
-               header_data_i <= x"0001";
-               header_enqueue_i <= '1';
-               fsm_i <= TRL_TRAILER_L;
-            when TRL_TRAILER_L =>
-               header_data_i <= x"5555";
-               header_enqueue_i <= '1';
-               fsm_i <= TRL_STATUS_H;            
-
-            when TRL_STATUS_H =>
-               header_data_i <= GBE_CTS_STATUS_BITS_IN(31 downto 16);
-               header_enqueue_i <= '1';
-               fsm_i <= TRL_STATUS_L;
-            when TRL_STATUS_L =>
-               header_data_i <= GBE_CTS_STATUS_BITS_IN(15 downto  0);
-               header_enqueue_i <= '1';
-               WPACKET_COMPLETE_OUT <= '1';
-               fsm_i <= IDLE;                         
-               
-         end case;
-      end if;
-   end process;
-   
-   WDATA_OUT(15 downto 0) <= DEC_DATA_IN when copy_payload_i='1' else header_data_i;
-   WDATA_OUT(17 downto 16) <= "00";
-   WENQUEUE_OUT <= header_enqueue_i or data_read_i;
-   
-   data_read_i <= copy_payload_i and DEC_DATA_READY_IN;
-   DEC_DATA_READ_OUT <= data_read_i;
-   data_read_delayed_i <= data_read_i when rising_edge(CLK_IN);
-end architecture;
\ No newline at end of file
diff --git a/cbmnet/code/cbmnet_readout_fifo_ecp3.vhd b/cbmnet/code/cbmnet_readout_fifo_ecp3.vhd
new file mode 100644
index 0000000..857f7b8
--- /dev/null
+++ b/cbmnet/code/cbmnet_readout_fifo_ecp3.vhd
@@ -0,0 +1,281 @@
+library ieee;
+   use ieee.std_logic_1164.all;
+   use ieee.numeric_std.all;
+
+
+entity CBMNET_READOUT_FIFO is
+   generic (
+      ADDR_WIDTH : positive := 10;
+      WATERMARK  : positive := 4
+   );
+
+   port (
+      -- write port
+      WCLK_IN   : in std_logic; -- not faster than rclk_in
+      WRESET_IN : in std_logic;
+      
+      WADDR_STORE_IN   : in std_logic;
+      WADDR_RESTORE_IN : in std_logic;
+      
+      WDATA_IN    : in std_logic_vector(17 downto 0);
+      WENQUEUE_IN : in std_logic;
+      WPACKET_COMPLETE_IN : in std_logic;
+      
+      WALMOST_FULL_OUT : out std_logic;
+      WFULL_OUT        : out std_logic;
+      
+      -- read port
+      RCLK_IN   : in std_logic;
+      RRESET_IN : in std_logic;  -- has to active at least two clocks AFTER (or while) write port was (is being) initialised
+      
+      RDATA_OUT   : out std_logic_vector(17 downto 0);
+      RDEQUEUE_IN : in std_logic;
+      
+      RPACKET_COMPLETE_OUT : out std_logic;   -- atleast one packet is completed in fifo
+      RPACKET_COMPLETE_ACK_IN : in std_logic; -- mark one event as dealt with (effectively decrease number of completed packets by one)
+      
+      DEBUG_OUT : out std_logic_vector(31 downto 0)
+   );
+end CBMNET_READOUT_FIFO;
+
+architecture cbmnet_readout_fifo_arch of CBMNET_READOUT_FIFO is
+   constant FIFO_NUM_C : positive := 2;
+   
+   component cbmnet_fifo_18x2k_dp is
+      port (
+         Data: in  std_logic_vector(17 downto 0); 
+         WrClock: in  std_logic; 
+         RdClock: in  std_logic; 
+         WrEn: in  std_logic; 
+         RdEn: in  std_logic; 
+         Reset: in  std_logic; 
+         RPReset: in  std_logic; 
+         Q: out  std_logic_vector(17 downto 0); 
+         WCNT: out  std_logic_vector(11 downto 0); 
+         Empty: out  std_logic; 
+         Full: out  std_logic; 
+         AlmostFull: out  std_logic
+      );
+   end component;
+   
+   signal rread_fifo_i, wread_fifo_i, rwrite_fifo_i, wwrite_fifo_i : integer range 0 to FIFO_NUM_C-1;
+   
+   signal fifo_enqueue_i     : std_logic_vector(FIFO_NUM_C-1 downto 0);
+   signal fifo_dequeue_i     : std_logic_vector(FIFO_NUM_C-1 downto 0);
+   signal fifo_empty_i       : std_logic_vector(FIFO_NUM_C-1 downto 0);
+   signal fifo_full_i        : std_logic_vector(FIFO_NUM_C-1 downto 0);
+   signal fifo_almost_full_i : std_logic_vector(FIFO_NUM_C-1 downto 0);
+   
+   signal fifo_data_i   : std_logic_vector(FIFO_NUM_C*18 - 1 downto 0);
+   signal fifo_wcount_i : std_logic_vector(FIFO_NUM_C*12 - 1 downto 0);
+
+   signal fifo_reset_i  : std_logic_vector(FIFO_NUM_C - 1 downto 0);
+   signal fifo_rreset_i : std_logic_vector(FIFO_NUM_C - 1 downto 0);
+   signal fifo_wreset_i : std_logic_vector(FIFO_NUM_C - 1 downto 0);
+   
+   signal wfifo_complete_i, rfifo_complete_i  : std_logic_vector(FIFO_NUM_C-1 downto 0);
+   
+   signal complete_ack_buf_i : std_logic_vector(1 downto 0);
+   
+   type RFSM_T is (WAIT_FOR_COMPLETED_FIFO, READ_FIRST_WORD, WAIT_FOR_ACK, WAIT_UNTIL_RESET);
+   type RFSM_ENC_T is array(RFSM_T) of std_logic_vector(3 downto 0);
+   signal rfsm_i : RFSM_T;
+   constant rfsm_enc_i : RFSM_ENC_T := (WAIT_FOR_COMPLETED_FIFO => x"1", READ_FIRST_WORD => x"2", WAIT_FOR_ACK => x"3", WAIT_UNTIL_RESET => x"4");
+   
+   type WFSM_T is (WAIT_FOR_FREE_FIFO, WAIT_FOR_RESET, WAIT_FOR_COMPLETE, COMPLETED);
+   type WFSM_ENC_T is array(WFSM_T) of std_logic_vector(3 downto 0);
+   signal wfsm_i : WFSM_T;
+   constant wfsm_enc_i : WFSM_ENC_T := (WAIT_FOR_FREE_FIFO => x"1", WAIT_FOR_RESET => x"2", WAIT_FOR_COMPLETE => x"3", COMPLETED => x"4");
+begin
+-- Complete and Reset flags
+   RPROC_COMP: process is
+   begin
+      wait until rising_edge(RCLK_IN);
+      
+      complete_ack_buf_i <= "0" & complete_ack_buf_i(complete_ack_buf_i'high downto 1);
+      
+      if RRESET_IN='1' then
+         complete_ack_buf_i <= (others => '0');
+      
+      elsif RPACKET_COMPLETE_ACK_IN='1' or rfsm_i = WAIT_UNTIL_RESET then
+         complete_ack_buf_i <= (others => '1');
+         
+      end if;
+   end process;
+
+   WPROC_COMP: process is
+      variable last_v : std_logic;
+   begin
+      wait until rising_edge(WCLK_IN);
+      
+      fifo_reset_i <= (others => '0');
+      if complete_ack_buf_i(0) = '1' then
+         fifo_reset_i(wread_fifo_i) <= '1';
+      end if;
+      last_v := complete_ack_buf_i(0);
+      
+      if WADDR_RESTORE_IN='1' and wfsm_i = WAIT_FOR_COMPLETE then
+         fifo_reset_i(wwrite_fifo_i) <= '1';
+      end if;
+   end process;
+   
+   WPROC_RESET: process is
+   begin
+      wait until rising_edge(WCLK_IN);
+      
+      if WRESET_IN='1' then
+         fifo_wreset_i <= (others => '1');
+         wfifo_complete_i <= (others => '0');
+      else
+         fifo_wreset_i <= fifo_reset_i;
+         wfifo_complete_i <= wfifo_complete_i and (not fifo_reset_i);
+      end if;
+      
+      if WPACKET_COMPLETE_IN='1' then
+         wfifo_complete_i(wwrite_fifo_i) <= '1';
+      end if;
+   end process;
+   
+   RPROC_RESET: process is
+   begin
+      wait until rising_edge(RCLK_IN);
+      if RRESET_IN='1' then
+         fifo_rreset_i <= (others => '1');
+      else
+         fifo_rreset_i <= fifo_reset_i;
+      end if;
+   end process;
+   
+   RFIFO_SELECTION: process is
+   begin
+      wait until rising_edge(RCLK_IN);
+      RPACKET_COMPLETE_OUT <= '0';
+      
+      if RRESET_IN='1' then
+         rfsm_i <= WAIT_FOR_COMPLETED_FIFO;
+         
+      else
+         case(rfsm_i) is
+            when WAIT_FOR_COMPLETED_FIFO =>
+               for i in 0 to FIFO_NUM_C-1 loop
+                  if rfifo_complete_i(i)='1' then
+                     rread_fifo_i <= i;
+                     rfsm_i <= READ_FIRST_WORD;
+                  end if;
+               end loop;
+            
+            when READ_FIRST_WORD =>
+               rfsm_i <= WAIT_FOR_ACK;
+               
+            when WAIT_FOR_ACK =>
+               RPACKET_COMPLETE_OUT <= '1';
+               if RPACKET_COMPLETE_ACK_IN='1' then
+                  RPACKET_COMPLETE_OUT <= '0';
+                  rfsm_i <= WAIT_UNTIL_RESET;
+               end if;
+               
+            when WAIT_UNTIL_RESET =>
+               if rfifo_complete_i(rread_fifo_i)='0' then
+                  rfsm_i <= WAIT_FOR_COMPLETED_FIFO;
+               end if;
+         end case;
+      end if;
+   end process;
+   
+   
+   WFIFO_SELECTION: process is
+   begin
+      wait until rising_edge(WCLK_IN);
+      
+      if WRESET_IN='1' then
+         wfsm_i <= WAIT_FOR_FREE_FIFO;
+      else
+         case(wfsm_i) is
+            when WAIT_FOR_FREE_FIFO =>
+               for i in 0 to FIFO_NUM_C-1 loop
+                  if wfifo_complete_i(i)='0' then
+                     wwrite_fifo_i <= i;
+                     wfsm_i <= WAIT_FOR_RESET;
+                  end if;
+               end loop;
+            
+            when WAIT_FOR_RESET =>
+               if fifo_rreset_i(wwrite_fifo_i) = '0' and fifo_wreset_i(wwrite_fifo_i) = '0' then
+                  wfsm_i <= WAIT_FOR_COMPLETE;
+               end if;
+            
+            when WAIT_FOR_COMPLETE =>
+               if WPACKET_COMPLETE_IN='1' then
+                  wfsm_i <= COMPLETED;
+               end if;
+               
+            when COMPLETED =>
+               wfsm_i <= WAIT_FOR_FREE_FIFO;
+            
+         end case;
+      end if;
+   end process;
+   
+   assert(not (wfsm_i = WAIT_FOR_COMPLETE and rfsm_i = WAIT_FOR_ACK and rread_fifo_i = wwrite_fifo_i));
+   
+   
+   wread_fifo_i <= rread_fifo_i when rising_edge(WCLK_IN);
+   rwrite_fifo_i <= wwrite_fifo_i when rising_edge(RCLK_IN);
+   rfifo_complete_i <= wfifo_complete_i when rising_edge(RCLK_IN);
+   
+
+-- READ PORT mux and decoder   
+   RDATA_OUT <= fifo_data_i(17+ 18*rread_fifo_i downto 18*rread_fifo_i); -- when rising_edge(RCLK_IN);
+   PROC_DEQUEUE: process(rread_fifo_i, RDEQUEUE_IN, rfsm_i) is
+   begin
+      fifo_dequeue_i <= (others => '0');
+      if RDEQUEUE_IN='1' or rfsm_i = READ_FIRST_WORD then
+         fifo_dequeue_i(rread_fifo_i) <= '1';
+      end if;
+   end process;
+
+-- WRITE PORT   
+   PROC_WPORT: process(wwrite_fifo_i, wfsm_i, WENQUEUE_IN, fifo_full_i, fifo_almost_full_i) is
+   begin
+      fifo_enqueue_i <= (others => '0');
+      fifo_enqueue_i(wwrite_fifo_i) <= WENQUEUE_IN;
+      
+      WFULL_OUT <= '0';
+      if (wfsm_i /= WAIT_FOR_COMPLETE) or fifo_full_i(wwrite_fifo_i)='1' then
+         WFULL_OUT <= '1';
+      end if;
+      
+      WALMOST_FULL_OUT <= '0';
+      if (wfsm_i /= WAIT_FOR_COMPLETE) or fifo_almost_full_i(wwrite_fifo_i)='1' then
+         WALMOST_FULL_OUT <= '1';
+      end if;
+   end process;
+
+
+   GEN_FIFOS: for i in 0 to FIFO_NUM_C-1 generate
+      THE_FIFO: cbmnet_fifo_18x2k_dp
+      port map (
+         Data    => WDATA_IN, -- in  std_logic_vector(17 downto 0); 
+         WrClock => WCLK_IN, -- in  std_logic; 
+         RdClock => RCLK_IN, -- in  std_logic; 
+         WrEn    => fifo_enqueue_i(i), -- in  std_logic; 
+         RdEn    => fifo_dequeue_i(i), -- in  std_logic; 
+         Reset   => fifo_wreset_i(i), -- in  std_logic; 
+         RPReset => fifo_rreset_i(i), -- in  std_logic; 
+         Q       => fifo_data_i(17 + 18*i downto 18*i), -- out  std_logic_vector(17 downto 0); 
+         WCNT    => open, -- out  std_logic_vector(11 downto 0); 
+         Empty   => fifo_empty_i(i), -- out  std_logic; 
+         Full    => fifo_full_i(i), -- out  std_logic; 
+         AlmostFull => fifo_almost_full_i(i) -- out  std_logic
+      );
+   end generate;
+   
+   DEBUG_OUT( 3 downto  0) <= STD_LOGIC_VECTOR(TO_UNSIGNED(wwrite_fifo_i, 4));
+   DEBUG_OUT( 7 downto  4) <= STD_LOGIC_VECTOR(TO_UNSIGNED(wread_fifo_i, 4));
+   DEBUG_OUT(11 downto  8) <= wfsm_enc_i(wfsm_i);
+   DEBUG_OUT(15 downto 12) <= rfsm_enc_i(rfsm_i);
+   DEBUG_OUT(19 downto 16) <= "0" & fifo_full_i(0) & fifo_almost_full_i(0) & fifo_empty_i(0);
+   DEBUG_OUT(23 downto 20) <= "0" & fifo_full_i(0) & fifo_almost_full_i(0) & fifo_empty_i(0);   
+   DEBUG_OUT(27 downto 24) <= "00" & wfifo_complete_i;
+   DEBUG_OUT(31 downto 28) <= "00" & fifo_wreset_i;
+end architecture;
\ No newline at end of file
diff --git a/cbmnet/code/cbmnet_readout_fifo.vhd b/cbmnet/code/cbmnet_readout_fifo_generic.vhd
similarity index 75%
rename from cbmnet/code/cbmnet_readout_fifo.vhd
rename to cbmnet/code/cbmnet_readout_fifo_generic.vhd
index 381d8a5..0cceca5 100644
--- a/cbmnet/code/cbmnet_readout_fifo.vhd
+++ b/cbmnet/code/cbmnet_readout_fifo_generic.vhd
@@ -41,13 +41,16 @@ end CBMNET_READOUT_FIFO;
 architecture cbmnet_readout_fifo_arch of CBMNET_READOUT_FIFO is
    signal waddr_i, waddr_stored_i, wread_pointer_i, wwords_remaining_i : unsigned(ADDR_WIDTH-1 downto 0) := (others => '0');
    signal wfull_i, walmost_full_i : std_logic;
-   signal wpacket_complete_xchange_i : std_logic := '0';
+   signal wpacket_complete_xchange_i : std_logic_vector(2 downto 0) := (others => '0');
    
    signal raddr_i, raddr_stored_i, rwrite_pointer_i, rpacket_counter_i : unsigned(ADDR_WIDTH-1 downto 0) := (others => '0');
    signal rpacket_complete_xchange_i : std_logic := '0'; 
    
-   type FIFO_MEM_T is array(0 to 2**ADDR_WIDTH-1) of std_logic_vector(17 downto 0);
+   type FIFO_MEM_T is array(0 to 2**ADDR_WIDTH-1) of std_logic_vector(15 downto 0);
    signal mem_i : FIFO_MEM_T;
+   
+   attribute syn_ramstyle : string;
+   attribute syn_ramstyle of mem_i : signal is "block_ram";
 begin
 -- Memory
    MEM_WRITE_PORT: process is
@@ -55,7 +58,7 @@ begin
    begin
       wait until rising_edge(WCLK_IN);
       if (wfull_i = '0' ) and WENQUEUE_IN = '1' then
-         mem_i(to_integer(waddr_i)) <= WDATA_IN;
+         mem_i(to_integer(waddr_i)) <= WDATA_IN(15 downto 0);
       end if;
       
       if WENQUEUE_IN='1' then
@@ -68,31 +71,39 @@ begin
    rwrite_pointer_i <= waddr_i when rising_edge(RCLK_IN);
    
    RPROC_COMPLETE_COUNTER: process is
-      variable delta_v : unsigned(1 downto 0);
+      variable delta_v    : integer range -1 to 1;
+      variable deadtime_v : integer range 0 to 7;
    begin
       wait until rising_edge(RCLK_IN);
-      delta_v := TO_UNSIGNED(1, delta_v'length);
-      rpacket_complete_xchange_i <= wpacket_complete_xchange_i;
+      delta_v := 0;
+      rpacket_complete_xchange_i <= wpacket_complete_xchange_i(0);
       RPACKET_COMPLETE_OUT <= '0';
       
       if RRESET_IN = '1' then
          rpacket_counter_i <= (others => '0');
+         deadtime_v := 0;
       else
          if RPACKET_COMPLETE_ACK_IN = '1' then
-            delta_v := TO_UNSIGNED(0, delta_v'length);
+            delta_v := 1;
          end if;
       
-         if rpacket_complete_xchange_i /= wpacket_complete_xchange_i then
-            delta_v := delta_v + TO_UNSIGNED(1, delta_v'length);
+         if deadtime_v = 0 and rpacket_complete_xchange_i = '1' then
+            delta_v := delta_v - 1;
+            deadtime_v := 7;
          end if;
          
+         
          if rpacket_counter_i /= 0 or delta_v /= 0 then
-            rpacket_counter_i <= rpacket_counter_i + delta_v -  TO_UNSIGNED(1, 1);
+            rpacket_counter_i <= rpacket_counter_i + TO_UNSIGNED(delta_v, rpacket_counter_i'length);
          end if;
          
-         if (rpacket_counter_i /= 0 or delta_v = 2) then
+         if (rpacket_counter_i /= 0) then
             RPACKET_COMPLETE_OUT <= '1';
          end if;
+
+         if deadtime_v /= 0 then
+            deadtime_v := deadtime_v - 1;
+         end if;
       end if;
    end process;
    
@@ -113,7 +124,7 @@ begin
       
       raddr_i <= next_addr_v;
    end process;
-   RDATA_OUT <= mem_i(to_integer(raddr_i)) when rising_edge(RCLK_IN);
+   RDATA_OUT(15 downto 0) <= mem_i(to_integer(raddr_i)) when rising_edge(RCLK_IN);
 
 -- Write Port
    wread_pointer_i <= raddr_i when rising_edge(WCLK_IN);
@@ -156,13 +167,15 @@ begin
    end process;
    
    WPROC_PACKET_COMPLETE: process is
-      variable last_v : std_logic;
    begin
       wait until rising_edge(WCLK_IN);
-      if WPACKET_COMPLETE_IN = '1' and last_v = '0' then
-         wpacket_complete_xchange_i <= not wpacket_complete_xchange_i;
+      if WRESET_IN = '1' then
+         wpacket_complete_xchange_i <= (others => '0');
+      elsif WPACKET_COMPLETE_IN = '1' then
+         wpacket_complete_xchange_i <= (others => '1');
+      else
+         wpacket_complete_xchange_i <= "0" & wpacket_complete_xchange_i(wpacket_complete_xchange_i'high downto 1);
       end if;
-      last_v := WPACKET_COMPLETE_IN;
    end process;
    
    WALMOST_FULL_OUT <= walmost_full_i;
@@ -171,8 +184,8 @@ begin
    WPROC_DEBUG: process is
    begin
       wait until rising_edge(WCLK_IN);
-      DEBUG_OUT <= (others => '0');
-      DEBUG_OUT(wwords_remaining_i'range) <= STD_LOGIC_VECTOR(wwords_remaining_i);
-      DEBUG_OUT(16+rpacket_counter_i'high downto 16) <= STD_LOGIC_VECTOR(rpacket_counter_i);
+      DEBUG_OUT(11 downto  0) <= waddr_i;
+      DEBUG_OUT(23 downto 12) <= raddr_i;
+      DEBUG_OUT(31 downto 24) <= rpacket_counter_i(7 downto 0);
    end process;
 end architecture;
\ No newline at end of file
diff --git a/cbmnet/code/cbmnet_readout_frame_packer.vhd b/cbmnet/code/cbmnet_readout_frame_packer.vhd
index 5301781..fa59526 100644
--- a/cbmnet/code/cbmnet_readout_frame_packer.vhd
+++ b/cbmnet/code/cbmnet_readout_frame_packer.vhd
@@ -9,7 +9,7 @@ entity CBMNET_READOUT_FRAME_PACKER is
       RESET_IN : in std_logic; 
 
       -- fifo 
-      FIFO_DATA_IN   : in std_logic_vector(15 downto 0);
+      FIFO_DATA_IN   : in std_logic_vector(17 downto 0);
       FIFO_DEQUEUE_OUT : out std_logic;
       FIFO_PACKET_COMPLETE_IN : in std_logic;  
       FIFO_PACKET_COMPLETE_ACK_OUT : out std_logic;
@@ -58,7 +58,13 @@ architecture cbmnet_readout_frame_packer_arch of CBMNET_READOUT_FRAME_PACKER is
    
    signal buf_length_h_i : std_logic_vector(15 downto 0);
    
+   signal fifo_data_i : std_logic_vector(15 downto 0);
+   signal fifo_token_i : std_logic_vector(1 downto 0);
+   
 begin
+   fifo_data_i <= FIFO_DATA_IN(15 downto 0);
+   fifo_token_i <= FIFO_DATA_IN(17 downto 16);
+
 
    PROC_TX_CNTL: process is 
       variable dequeue_forced_v : std_logic;
@@ -68,7 +74,7 @@ begin
       
       CBMNET_START_OUT <= '0';
       CBMNET_END_OUT <= '0';
-      CBMNET_DATA_OUT <= FIFO_DATA_IN;
+      CBMNET_DATA_OUT <= fifo_data_i;
       
       dequeue_if_allowed_v := '0';
       dequeue_forced_v := '0';
@@ -96,17 +102,19 @@ begin
                fsm_i <= SETUP_TRANSACTION_FETCH_LENGTH_H;
             
             when SETUP_TRANSACTION_FETCH_LENGTH_H =>
-               buf_length_h_i <= FIFO_DATA_IN;
-               assert(FIFO_DATA_IN = x"0000");
+               buf_length_h_i <= fifo_data_i;
+               assert(fifo_token_i = "01") report "Invalid LENGHT_H token" severity failure;
+               assert(fifo_data_i = x"0000") report "TrbNet length high-byte /= 0 and hence to long. This is not supported by this module" severity failure;
                fsm_i <= SETUP_TRANSACTION_FETCH_LENGTH_L;
             
             when SETUP_TRANSACTION_FETCH_LENGTH_L =>
                remaining_words_in_transaction_i <= (others =>'0');
-               remaining_words_in_transaction_i(14 downto 0) <= UNSIGNED(FIFO_DATA_IN(15 downto 1));
+               remaining_words_in_transaction_i(14 downto 0) <= UNSIGNED(fifo_data_i(15 downto 1));
                remaining_words_to_dequeue_i <= (others =>'0');
-               remaining_words_to_dequeue_i(14 downto 0) <= UNSIGNED(FIFO_DATA_IN(15 downto 1)) - TO_UNSIGNED(1, 15);
-               assert(to_integer(UNSIGNED(FIFO_DATA_IN)) >= 24) report "TrbNet packet too short. Expect minimal length of 24 bytes.";
-               assert(to_integer(UNSIGNED(FIFO_DATA_IN)) < 4096) report "TrbNet packet too long. This module should support sending of transactions with upto 32kb data, but only 4kb transactions have been specified and tested";
+               remaining_words_to_dequeue_i(14 downto 0) <= UNSIGNED(fifo_data_i(15 downto 1)) - TO_UNSIGNED(1, 15);
+               assert(fifo_token_i = "10") report "Invalid LENGTH_L token"  severity failure;
+               assert(to_integer(UNSIGNED(fifo_data_i)) >= 24) report "TrbNet packet too short. Expect minimal length of 24 bytes." severity failure;
+               assert(to_integer(UNSIGNED(fifo_data_i)) < 4096) report "TrbNet packet too long. This module should support sending of transactions with upto 32kb data, but only 4kb transactions have been specified and tested" severity failure;
                fsm_i <= FIRST_FRAME_SEND_HDR;
             
             when FIRST_FRAME_SEND_HDR =>
@@ -189,6 +197,8 @@ begin
                if remaining_words_in_frame_i = 2 then
                   fsm_i <= SEND_STOP_WORD;
                end if;
+               
+               assert(fifo_token_i = "00" or fifo_token_i = "10" or (fifo_token_i = "11" and remaining_words_in_transaction_i < 2)) report "Invalid LENGHT_L / DATA / END token";
                   
             when SEND_STOP_WORD =>
                if remaining_words_in_transaction_i = 0 then
@@ -203,8 +213,10 @@ begin
                if remaining_words_in_transaction_i = 1 or remaining_words_in_transaction_i = 0 then
                   fsm_i <= COMPLETE_TRANSACTION;
                   FIFO_PACKET_COMPLETE_ACK_OUT <= '1';
+                  assert(fifo_token_i = "11") report "Invalid data token";
                else
                   fsm_i <= BEGIN_FRAME_PRE_WAIT0;
+                  assert(fifo_token_i = "00") report "Invalid data token";
                end if;
             
             
diff --git a/cbmnet/code/cbmnet_readout_obuf.vhd b/cbmnet/code/cbmnet_readout_obuf.vhd
index 134216d..c014885 100644
--- a/cbmnet/code/cbmnet_readout_obuf.vhd
+++ b/cbmnet/code/cbmnet_readout_obuf.vhd
@@ -23,7 +23,7 @@ entity CBMNET_READOUT_OBUF is
       CBMNET_END_OUT   : out std_logic;
       CBMNET_DATA_OUT  : out std_logic_vector(15 downto 0);
       
-      DEBUG_OUT : out std_logic_vector(31 downto 0)
+      DEBUG_OUT : out std_logic_vector(31 downto 0) := (others => '0')
    );
 end entity;
 
@@ -41,12 +41,16 @@ architecture cbmnet_readout_obuf_arch of CBMNET_READOUT_OBUF is
    signal fifo_write_data_i : std_logic_vector(15 downto 0);
    
    signal fifo_deq_i : std_logic;
-
+   
    type WFSM_T is (OBTAIN_FREE_BUFFER, WAIT_FOR_START, WAIT_FOR_END, COMPLETE);
+   type WFSM_DEC_T is array(WFSM_T) of std_logic_vector(3 downto 0);
    signal wfsm_i : WFSM_T;
+   constant wfsm_dec_c : WFSM_DEC_T := (OBTAIN_FREE_BUFFER => x"1", WAIT_FOR_START => x"2", WAIT_FOR_END => x"3", COMPLETE => x"4");
    
    type RFSM_T is (OBTAIN_FULL_BUFFER, WAIT_WHILE_STOP, COPY, COMPLETE);
+   type RFSM_DEC_T is array(RFSM_T) of std_logic_vector(3 downto 0);
    signal rfsm_i, rfsm_next_i : RFSM_T;
+   constant rfsm_dec_c : RFSM_DEC_T := (OBTAIN_FULL_BUFFER => x"1", WAIT_WHILE_STOP => x"2", COPY => x"3", COMPLETE => x"4");
 begin
    WPROC: process is
    begin
@@ -187,4 +191,12 @@ begin
    );
    
    fifo_write_data_i <= PACKER_DATA_IN when rising_edge(CLK_IN);
+   
+   DEBUG_OUT( 3 downto  0) <= STD_LOGIC_VECTOR(TO_UNSIGNED(write_fifo_i, 4));
+   DEBUG_OUT( 7 downto  4) <= STD_LOGIC_VECTOR(TO_UNSIGNED(read_fifo_i,  4));
+   DEBUG_OUT(11 downto  8) <= wfsm_dec_c(wfsm_i);
+   DEBUG_OUT(15 downto 12) <= rfsm_dec_c(rfsm_i);
+   DEBUG_OUT(19 downto 16) <= fifo_get_filled_i(0) & fifo_last_i(0) & fifo_enqueue_i(0) & fifo_dequeue_i(0);
+   DEBUG_OUT(23 downto 20) <= fifo_get_filled_i(1) & fifo_last_i(1) & fifo_enqueue_i(1) & fifo_dequeue_i(1);
+
 end architecture;
\ No newline at end of file
diff --git a/cbmnet/code/cbmnet_readout_trbnet_decoder.vhd b/cbmnet/code/cbmnet_readout_trbnet_decoder.vhd
index cf24f06..25fecef 100644
--- a/cbmnet/code/cbmnet_readout_trbnet_decoder.vhd
+++ b/cbmnet/code/cbmnet_readout_trbnet_decoder.vhd
@@ -42,6 +42,8 @@ architecture cbmnet_readout_trbnet_decoder_arch of CBMNET_READOUT_TRBNET_DECODER
    type FIFO_MEM_T is array(0 to 2**FIFO_LENGTH_C-1) of std_logic_vector(15 downto 0);
    signal fifo_mem_i : FIFO_MEM_T;
 
+   attribute syn_ramstyle : string;
+   attribute syn_ramstyle of fifo_mem_i : signal is "block_ram";
 
    type FSM_STATES_T is (WAIT_FOR_IDLE, IDLE, RECV_EVT_INFO_H, RECV_EVT_INFO_L, RECV_EVT_LENGTH, RECV_EVT_SOURCE, RECV_PAYLOAD, LAST_WORD, ERROR_COND);
    signal fsm_i : FSM_STATES_T;
diff --git a/cbmnet/code/tb_cbmnet_readout2.vhd b/cbmnet/code/tb_cbmnet_readout2.vhd
index 6374253..19f8478 100644
--- a/cbmnet/code/tb_cbmnet_readout2.vhd
+++ b/cbmnet/code/tb_cbmnet_readout2.vhd
@@ -236,7 +236,7 @@ begin
                --end if;
                
                uniform(seed1, seed2, rand);
-               int_rand := 4+integer(trunc(rand*500.0));
+               int_rand := 2+integer(trunc(rand*990.0));
                --int_rand := 2;
                send_length_i(9 downto 0) <= TO_UNSIGNED(int_rand, 10);
                
diff --git a/cbmnet/cores/cbmnet_fifo_18x2k_dp.ipx b/cbmnet/cores/cbmnet_fifo_18x2k_dp.ipx
new file mode 100644
index 0000000..4ad1418
--- /dev/null
+++ b/cbmnet/cores/cbmnet_fifo_18x2k_dp.ipx
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="cbmnet_fifo_18x2k_dp" module="FIFO_DC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 08 08 14:35:44.077" version="5.7" type="Module" synthesis="synplify" source_format="VHDL">
+  <Package>
+		<File name="cbmnet_fifo_18x2k_dp.lpc" type="lpc" modified="2014 08 08 14:35:22.000"/>
+		<File name="cbmnet_fifo_18x2k_dp.vhd" type="top_level_vhdl" modified="2014 08 08 14:35:22.000"/>
+		<File name="cbmnet_fifo_18x2k_dp_tmpl.vhd" type="template_vhdl" modified="2014 08 08 14:35:22.000"/>
+		<File name="tb_cbmnet_fifo_18x2k_dp_tmpl.vhd" type="testbench_vhdl" modified="2014 08 08 14:35:23.000"/>
+  </Package>
+</DiamondModule>
diff --git a/cbmnet/cores/cbmnet_fifo_18x2k_dp.vhd b/cbmnet/cores/cbmnet_fifo_18x2k_dp.vhd
new file mode 100644
index 0000000..1a0e021
--- /dev/null
+++ b/cbmnet/cores/cbmnet_fifo_18x2k_dp.vhd
@@ -0,0 +1,1934 @@
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.2.0.134
+-- Module  Version: 5.7
+--/d/jspc29/lattice/diamond/3.2_x64/ispfpga/bin/lin64/scuba -w -n cbmnet_fifo_18x2k_dp -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 2048 -width 18 -depth 2048 -rdata_width 18 -regout -no_enable -pe -1 -pf 2040 -pf2 2038 -fill 
+
+-- Fri Aug  8 14:35:22 2014
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity cbmnet_fifo_18x2k_dp is
+    port (
+        Data: in  std_logic_vector(17 downto 0); 
+        WrClock: in  std_logic; 
+        RdClock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        RPReset: in  std_logic; 
+        Q: out  std_logic_vector(17 downto 0); 
+        WCNT: out  std_logic_vector(11 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic; 
+        AlmostFull: out  std_logic);
+end cbmnet_fifo_18x2k_dp;
+
+architecture Structure of cbmnet_fifo_18x2k_dp is
+
+    -- internal signal declarations
+    signal invout_1: std_logic;
+    signal invout_0: std_logic;
+    signal w_g2b_xor_cluster_2_1: std_logic;
+    signal w_g2b_xor_cluster_2: std_logic;
+    signal w_g2b_xor_cluster_1: std_logic;
+    signal r_g2b_xor_cluster_2_1: std_logic;
+    signal r_g2b_xor_cluster_2: std_logic;
+    signal r_g2b_xor_cluster_1: std_logic;
+    signal w_gdata_0: std_logic;
+    signal w_gdata_1: std_logic;
+    signal w_gdata_2: std_logic;
+    signal w_gdata_3: std_logic;
+    signal w_gdata_4: std_logic;
+    signal w_gdata_5: std_logic;
+    signal w_gdata_6: std_logic;
+    signal w_gdata_7: std_logic;
+    signal w_gdata_8: std_logic;
+    signal w_gdata_9: std_logic;
+    signal w_gdata_10: std_logic;
+    signal wptr_11: std_logic;
+    signal r_gdata_0: std_logic;
+    signal r_gdata_1: std_logic;
+    signal r_gdata_2: std_logic;
+    signal r_gdata_3: std_logic;
+    signal r_gdata_4: std_logic;
+    signal r_gdata_5: std_logic;
+    signal r_gdata_6: std_logic;
+    signal r_gdata_7: std_logic;
+    signal r_gdata_8: std_logic;
+    signal r_gdata_9: std_logic;
+    signal r_gdata_10: std_logic;
+    signal rptr_0: std_logic;
+    signal rptr_1: std_logic;
+    signal rptr_2: std_logic;
+    signal rptr_3: std_logic;
+    signal rptr_4: std_logic;
+    signal rptr_5: std_logic;
+    signal rptr_6: std_logic;
+    signal rptr_7: std_logic;
+    signal rptr_8: std_logic;
+    signal rptr_9: std_logic;
+    signal rptr_10: std_logic;
+    signal rptr_11: std_logic;
+    signal w_gcount_0: std_logic;
+    signal w_gcount_1: std_logic;
+    signal w_gcount_2: std_logic;
+    signal w_gcount_3: std_logic;
+    signal w_gcount_4: std_logic;
+    signal w_gcount_5: std_logic;
+    signal w_gcount_6: std_logic;
+    signal w_gcount_7: std_logic;
+    signal w_gcount_8: std_logic;
+    signal w_gcount_9: std_logic;
+    signal w_gcount_10: std_logic;
+    signal w_gcount_11: std_logic;
+    signal r_gcount_0: std_logic;
+    signal r_gcount_1: std_logic;
+    signal r_gcount_2: std_logic;
+    signal r_gcount_3: std_logic;
+    signal r_gcount_4: std_logic;
+    signal r_gcount_5: std_logic;
+    signal r_gcount_6: std_logic;
+    signal r_gcount_7: std_logic;
+    signal r_gcount_8: std_logic;
+    signal r_gcount_9: std_logic;
+    signal r_gcount_10: std_logic;
+    signal r_gcount_11: std_logic;
+    signal w_gcount_r20: std_logic;
+    signal w_gcount_r0: std_logic;
+    signal w_gcount_r21: std_logic;
+    signal w_gcount_r1: std_logic;
+    signal w_gcount_r22: std_logic;
+    signal w_gcount_r2: std_logic;
+    signal w_gcount_r23: std_logic;
+    signal w_gcount_r3: std_logic;
+    signal w_gcount_r24: std_logic;
+    signal w_gcount_r4: std_logic;
+    signal w_gcount_r25: std_logic;
+    signal w_gcount_r5: std_logic;
+    signal w_gcount_r26: std_logic;
+    signal w_gcount_r6: std_logic;
+    signal w_gcount_r27: std_logic;
+    signal w_gcount_r7: std_logic;
+    signal w_gcount_r28: std_logic;
+    signal w_gcount_r8: std_logic;
+    signal w_gcount_r29: std_logic;
+    signal w_gcount_r9: std_logic;
+    signal w_gcount_r210: std_logic;
+    signal w_gcount_r10: std_logic;
+    signal w_gcount_r211: std_logic;
+    signal w_gcount_r11: std_logic;
+    signal r_gcount_w20: std_logic;
+    signal r_gcount_w0: std_logic;
+    signal r_gcount_w21: std_logic;
+    signal r_gcount_w1: std_logic;
+    signal r_gcount_w22: std_logic;
+    signal r_gcount_w2: std_logic;
+    signal r_gcount_w23: std_logic;
+    signal r_gcount_w3: std_logic;
+    signal r_gcount_w24: std_logic;
+    signal r_gcount_w4: std_logic;
+    signal r_gcount_w25: std_logic;
+    signal r_gcount_w5: std_logic;
+    signal r_gcount_w26: std_logic;
+    signal r_gcount_w6: std_logic;
+    signal r_gcount_w27: std_logic;
+    signal r_gcount_w7: std_logic;
+    signal r_gcount_w28: std_logic;
+    signal r_gcount_w8: std_logic;
+    signal r_gcount_w29: std_logic;
+    signal r_gcount_w9: std_logic;
+    signal r_gcount_w210: std_logic;
+    signal r_gcount_w10: std_logic;
+    signal r_gcount_w211: std_logic;
+    signal r_gcount_w11: std_logic;
+    signal empty_i: std_logic;
+    signal rRst: std_logic;
+    signal full_i: std_logic;
+    signal af: std_logic;
+    signal af_d: std_logic;
+    signal iwcount_0: std_logic;
+    signal iwcount_1: std_logic;
+    signal w_gctr_ci: std_logic;
+    signal iwcount_2: std_logic;
+    signal iwcount_3: std_logic;
+    signal co0: std_logic;
+    signal iwcount_4: std_logic;
+    signal iwcount_5: std_logic;
+    signal co1: std_logic;
+    signal iwcount_6: std_logic;
+    signal iwcount_7: std_logic;
+    signal co2: std_logic;
+    signal iwcount_8: std_logic;
+    signal iwcount_9: std_logic;
+    signal co3: std_logic;
+    signal iwcount_10: std_logic;
+    signal iwcount_11: std_logic;
+    signal co5: std_logic;
+    signal co4: std_logic;
+    signal wcount_11: std_logic;
+    signal ircount_0: std_logic;
+    signal ircount_1: std_logic;
+    signal r_gctr_ci: std_logic;
+    signal ircount_2: std_logic;
+    signal ircount_3: std_logic;
+    signal co0_1: std_logic;
+    signal ircount_4: std_logic;
+    signal ircount_5: std_logic;
+    signal co1_1: std_logic;
+    signal ircount_6: std_logic;
+    signal ircount_7: std_logic;
+    signal co2_1: std_logic;
+    signal ircount_8: std_logic;
+    signal ircount_9: std_logic;
+    signal co3_1: std_logic;
+    signal ircount_10: std_logic;
+    signal ircount_11: std_logic;
+    signal co5_1: std_logic;
+    signal co4_1: std_logic;
+    signal rcount_11: std_logic;
+    signal wfill_sub_0: std_logic;
+    signal precin: std_logic;
+    signal wptr_0: std_logic;
+    signal wfill_sub_1: std_logic;
+    signal wfill_sub_2: std_logic;
+    signal co0_2: std_logic;
+    signal wptr_1: std_logic;
+    signal wptr_2: std_logic;
+    signal wfill_sub_3: std_logic;
+    signal wfill_sub_4: std_logic;
+    signal co1_2: std_logic;
+    signal wptr_3: std_logic;
+    signal wptr_4: std_logic;
+    signal wfill_sub_5: std_logic;
+    signal wfill_sub_6: std_logic;
+    signal co2_2: std_logic;
+    signal wptr_5: std_logic;
+    signal wptr_6: std_logic;
+    signal wfill_sub_7: std_logic;
+    signal wfill_sub_8: std_logic;
+    signal co3_2: std_logic;
+    signal wptr_7: std_logic;
+    signal wptr_8: std_logic;
+    signal wfill_sub_9: std_logic;
+    signal wfill_sub_10: std_logic;
+    signal co4_2: std_logic;
+    signal wptr_9: std_logic;
+    signal wptr_10: std_logic;
+    signal wfill_sub_11: std_logic;
+    signal co5_2: std_logic;
+    signal wfill_sub_msb: std_logic;
+    signal rden_i: std_logic;
+    signal cmp_ci: std_logic;
+    signal wcount_r0: std_logic;
+    signal wcount_r1: std_logic;
+    signal rcount_0: std_logic;
+    signal rcount_1: std_logic;
+    signal co0_3: std_logic;
+    signal wcount_r2: std_logic;
+    signal wcount_r3: std_logic;
+    signal rcount_2: std_logic;
+    signal rcount_3: std_logic;
+    signal co1_3: std_logic;
+    signal wcount_r4: std_logic;
+    signal wcount_r5: std_logic;
+    signal rcount_4: std_logic;
+    signal rcount_5: std_logic;
+    signal co2_3: std_logic;
+    signal wcount_r6: std_logic;
+    signal wcount_r7: std_logic;
+    signal rcount_6: std_logic;
+    signal rcount_7: std_logic;
+    signal co3_3: std_logic;
+    signal w_g2b_xor_cluster_0: std_logic;
+    signal wcount_r9: std_logic;
+    signal rcount_8: std_logic;
+    signal rcount_9: std_logic;
+    signal co4_3: std_logic;
+    signal wcount_r10: std_logic;
+    signal empty_cmp_clr: std_logic;
+    signal rcount_10: std_logic;
+    signal empty_cmp_set: std_logic;
+    signal empty_d: std_logic;
+    signal empty_d_c: std_logic;
+    signal cmp_ci_1: std_logic;
+    signal wcount_0: std_logic;
+    signal wcount_1: std_logic;
+    signal co0_4: std_logic;
+    signal wcount_2: std_logic;
+    signal wcount_3: std_logic;
+    signal co1_4: std_logic;
+    signal wcount_4: std_logic;
+    signal wcount_5: std_logic;
+    signal co2_4: std_logic;
+    signal wcount_6: std_logic;
+    signal wcount_7: std_logic;
+    signal co3_4: std_logic;
+    signal wcount_8: std_logic;
+    signal wcount_9: std_logic;
+    signal co4_4: std_logic;
+    signal full_cmp_clr: std_logic;
+    signal wcount_10: std_logic;
+    signal full_cmp_set: std_logic;
+    signal full_d: std_logic;
+    signal full_d_c: std_logic;
+    signal iaf_setcount_0: std_logic;
+    signal iaf_setcount_1: std_logic;
+    signal af_set_ctr_ci: std_logic;
+    signal iaf_setcount_2: std_logic;
+    signal iaf_setcount_3: std_logic;
+    signal co0_5: std_logic;
+    signal iaf_setcount_4: std_logic;
+    signal iaf_setcount_5: std_logic;
+    signal co1_5: std_logic;
+    signal iaf_setcount_6: std_logic;
+    signal iaf_setcount_7: std_logic;
+    signal co2_5: std_logic;
+    signal iaf_setcount_8: std_logic;
+    signal iaf_setcount_9: std_logic;
+    signal co3_5: std_logic;
+    signal iaf_setcount_10: std_logic;
+    signal iaf_setcount_11: std_logic;
+    signal co5_3: std_logic;
+    signal co4_5: std_logic;
+    signal af_setcount_11: std_logic;
+    signal cmp_ci_2: std_logic;
+    signal af_setcount_0: std_logic;
+    signal af_setcount_1: std_logic;
+    signal co0_6: std_logic;
+    signal af_setcount_2: std_logic;
+    signal af_setcount_3: std_logic;
+    signal co1_6: std_logic;
+    signal af_setcount_4: std_logic;
+    signal af_setcount_5: std_logic;
+    signal co2_6: std_logic;
+    signal af_setcount_6: std_logic;
+    signal af_setcount_7: std_logic;
+    signal co3_6: std_logic;
+    signal af_setcount_8: std_logic;
+    signal af_setcount_9: std_logic;
+    signal co4_6: std_logic;
+    signal af_set_cmp_clr: std_logic;
+    signal af_setcount_10: std_logic;
+    signal af_set_cmp_set: std_logic;
+    signal af_set: std_logic;
+    signal af_set_c: std_logic;
+    signal scuba_vhi: std_logic;
+    signal iaf_clrcount_0: std_logic;
+    signal iaf_clrcount_1: std_logic;
+    signal af_clr_ctr_ci: std_logic;
+    signal iaf_clrcount_2: std_logic;
+    signal iaf_clrcount_3: std_logic;
+    signal co0_7: std_logic;
+    signal iaf_clrcount_4: std_logic;
+    signal iaf_clrcount_5: std_logic;
+    signal co1_7: std_logic;
+    signal iaf_clrcount_6: std_logic;
+    signal iaf_clrcount_7: std_logic;
+    signal co2_7: std_logic;
+    signal iaf_clrcount_8: std_logic;
+    signal iaf_clrcount_9: std_logic;
+    signal co3_7: std_logic;
+    signal iaf_clrcount_10: std_logic;
+    signal iaf_clrcount_11: std_logic;
+    signal co5_4: std_logic;
+    signal co4_7: std_logic;
+    signal af_clrcount_11: std_logic;
+    signal wren_i: std_logic;
+    signal cmp_ci_3: std_logic;
+    signal rcount_w0: std_logic;
+    signal rcount_w1: std_logic;
+    signal af_clrcount_0: std_logic;
+    signal af_clrcount_1: std_logic;
+    signal co0_8: std_logic;
+    signal rcount_w2: std_logic;
+    signal rcount_w3: std_logic;
+    signal af_clrcount_2: std_logic;
+    signal af_clrcount_3: std_logic;
+    signal co1_8: std_logic;
+    signal rcount_w4: std_logic;
+    signal rcount_w5: std_logic;
+    signal af_clrcount_4: std_logic;
+    signal af_clrcount_5: std_logic;
+    signal co2_8: std_logic;
+    signal rcount_w6: std_logic;
+    signal rcount_w7: std_logic;
+    signal af_clrcount_6: std_logic;
+    signal af_clrcount_7: std_logic;
+    signal co3_8: std_logic;
+    signal r_g2b_xor_cluster_0: std_logic;
+    signal rcount_w9: std_logic;
+    signal af_clrcount_8: std_logic;
+    signal af_clrcount_9: std_logic;
+    signal co4_8: std_logic;
+    signal rcount_w10: std_logic;
+    signal af_clr_cmp_clr: std_logic;
+    signal af_clrcount_10: std_logic;
+    signal af_clr_cmp_set: std_logic;
+    signal af_clr: std_logic;
+    signal af_clr_c: std_logic;
+    signal scuba_vlo: std_logic;
+
+    -- local component declarations
+    component AGEB2
+        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
+            B1: in  std_logic; CI: in  std_logic; GE: out  std_logic);
+    end component;
+    component AND2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component CU2
+        port (CI: in  std_logic; PC0: in  std_logic; PC1: in  std_logic; 
+            CO: out  std_logic; NC0: out  std_logic; NC1: out  std_logic);
+    end component;
+    component FADD2B
+        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
+            B1: in  std_logic; CI: in  std_logic; COUT: out  std_logic; 
+            S0: out  std_logic; S1: out  std_logic);
+    end component;
+    component FSUB2B
+        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
+            B1: in  std_logic; BI: in  std_logic; BOUT: out  std_logic; 
+            S0: out  std_logic; S1: out  std_logic);
+    end component;
+    component FD1P3BX
+        port (D: in  std_logic; SP: in  std_logic; CK: in  std_logic; 
+            PD: in  std_logic; Q: out  std_logic);
+    end component;
+    component FD1P3DX
+        port (D: in  std_logic; SP: in  std_logic; CK: in  std_logic; 
+            CD: in  std_logic; Q: out  std_logic);
+    end component;
+    component FD1S3BX
+        port (D: in  std_logic; CK: in  std_logic; PD: in  std_logic; 
+            Q: out  std_logic);
+    end component;
+    component FD1S3DX
+        port (D: in  std_logic; CK: in  std_logic; CD: in  std_logic; 
+            Q: out  std_logic);
+    end component;
+    component INV
+        port (A: in  std_logic; Z: out  std_logic);
+    end component;
+    component OR2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component ROM16X1A
+        generic (INITVAL : in std_logic_vector(15 downto 0));
+        port (AD3: in  std_logic; AD2: in  std_logic; AD1: in  std_logic; 
+            AD0: in  std_logic; DO0: out  std_logic);
+    end component;
+    component VHI
+        port (Z: out  std_logic);
+    end component;
+    component VLO
+        port (Z: out  std_logic);
+    end component;
+    component XOR2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component DP16KC
+        generic (GSR : in String; WRITEMODE_B : in String; 
+                WRITEMODE_A : in String; CSDECODE_B : in String; 
+                CSDECODE_A : in String; REGMODE_B : in String; 
+                REGMODE_A : in String; DATA_WIDTH_B : in Integer; 
+                DATA_WIDTH_A : in Integer);
+        port (DIA0: in  std_logic; DIA1: in  std_logic; 
+            DIA2: in  std_logic; DIA3: in  std_logic; 
+            DIA4: in  std_logic; DIA5: in  std_logic; 
+            DIA6: in  std_logic; DIA7: in  std_logic; 
+            DIA8: in  std_logic; DIA9: in  std_logic; 
+            DIA10: in  std_logic; DIA11: in  std_logic; 
+            DIA12: in  std_logic; DIA13: in  std_logic; 
+            DIA14: in  std_logic; DIA15: in  std_logic; 
+            DIA16: in  std_logic; DIA17: in  std_logic; 
+            ADA0: in  std_logic; ADA1: in  std_logic; 
+            ADA2: in  std_logic; ADA3: in  std_logic; 
+            ADA4: in  std_logic; ADA5: in  std_logic; 
+            ADA6: in  std_logic; ADA7: in  std_logic; 
+            ADA8: in  std_logic; ADA9: in  std_logic; 
+            ADA10: in  std_logic; ADA11: in  std_logic; 
+            ADA12: in  std_logic; ADA13: in  std_logic; 
+            CEA: in  std_logic; CLKA: in  std_logic; OCEA: in  std_logic; 
+            WEA: in  std_logic; CSA0: in  std_logic; CSA1: in  std_logic; 
+            CSA2: in  std_logic; RSTA: in  std_logic; 
+            DIB0: in  std_logic; DIB1: in  std_logic; 
+            DIB2: in  std_logic; DIB3: in  std_logic; 
+            DIB4: in  std_logic; DIB5: in  std_logic; 
+            DIB6: in  std_logic; DIB7: in  std_logic; 
+            DIB8: in  std_logic; DIB9: in  std_logic; 
+            DIB10: in  std_logic; DIB11: in  std_logic; 
+            DIB12: in  std_logic; DIB13: in  std_logic; 
+            DIB14: in  std_logic; DIB15: in  std_logic; 
+            DIB16: in  std_logic; DIB17: in  std_logic; 
+            ADB0: in  std_logic; ADB1: in  std_logic; 
+            ADB2: in  std_logic; ADB3: in  std_logic; 
+            ADB4: in  std_logic; ADB5: in  std_logic; 
+            ADB6: in  std_logic; ADB7: in  std_logic; 
+            ADB8: in  std_logic; ADB9: in  std_logic; 
+            ADB10: in  std_logic; ADB11: in  std_logic; 
+            ADB12: in  std_logic; ADB13: in  std_logic; 
+            CEB: in  std_logic; CLKB: in  std_logic; OCEB: in  std_logic; 
+            WEB: in  std_logic; CSB0: in  std_logic; CSB1: in  std_logic; 
+            CSB2: in  std_logic; RSTB: in  std_logic; 
+            DOA0: out  std_logic; DOA1: out  std_logic; 
+            DOA2: out  std_logic; DOA3: out  std_logic; 
+            DOA4: out  std_logic; DOA5: out  std_logic; 
+            DOA6: out  std_logic; DOA7: out  std_logic; 
+            DOA8: out  std_logic; DOA9: out  std_logic; 
+            DOA10: out  std_logic; DOA11: out  std_logic; 
+            DOA12: out  std_logic; DOA13: out  std_logic; 
+            DOA14: out  std_logic; DOA15: out  std_logic; 
+            DOA16: out  std_logic; DOA17: out  std_logic; 
+            DOB0: out  std_logic; DOB1: out  std_logic; 
+            DOB2: out  std_logic; DOB3: out  std_logic; 
+            DOB4: out  std_logic; DOB5: out  std_logic; 
+            DOB6: out  std_logic; DOB7: out  std_logic; 
+            DOB8: out  std_logic; DOB9: out  std_logic; 
+            DOB10: out  std_logic; DOB11: out  std_logic; 
+            DOB12: out  std_logic; DOB13: out  std_logic; 
+            DOB14: out  std_logic; DOB15: out  std_logic; 
+            DOB16: out  std_logic; DOB17: out  std_logic);
+    end component;
+    attribute MEM_LPC_FILE : string; 
+    attribute MEM_INIT_FILE : string; 
+    attribute RESETMODE : string; 
+    attribute GSR : string; 
+    attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "cbmnet_fifo_18x2k_dp.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is "";
+    attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "cbmnet_fifo_18x2k_dp.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is "";
+    attribute RESETMODE of pdp_ram_0_1_0 : label is "SYNC";
+    attribute GSR of FF_158 : label is "ENABLED";
+    attribute GSR of FF_157 : label is "ENABLED";
+    attribute GSR of FF_156 : label is "ENABLED";
+    attribute GSR of FF_155 : label is "ENABLED";
+    attribute GSR of FF_154 : label is "ENABLED";
+    attribute GSR of FF_153 : label is "ENABLED";
+    attribute GSR of FF_152 : label is "ENABLED";
+    attribute GSR of FF_151 : label is "ENABLED";
+    attribute GSR of FF_150 : label is "ENABLED";
+    attribute GSR of FF_149 : label is "ENABLED";
+    attribute GSR of FF_148 : label is "ENABLED";
+    attribute GSR of FF_147 : label is "ENABLED";
+    attribute GSR of FF_146 : label is "ENABLED";
+    attribute GSR of FF_145 : label is "ENABLED";
+    attribute GSR of FF_144 : label is "ENABLED";
+    attribute GSR of FF_143 : label is "ENABLED";
+    attribute GSR of FF_142 : label is "ENABLED";
+    attribute GSR of FF_141 : label is "ENABLED";
+    attribute GSR of FF_140 : label is "ENABLED";
+    attribute GSR of FF_139 : label is "ENABLED";
+    attribute GSR of FF_138 : label is "ENABLED";
+    attribute GSR of FF_137 : label is "ENABLED";
+    attribute GSR of FF_136 : label is "ENABLED";
+    attribute GSR of FF_135 : label is "ENABLED";
+    attribute GSR of FF_134 : label is "ENABLED";
+    attribute GSR of FF_133 : label is "ENABLED";
+    attribute GSR of FF_132 : label is "ENABLED";
+    attribute GSR of FF_131 : label is "ENABLED";
+    attribute GSR of FF_130 : label is "ENABLED";
+    attribute GSR of FF_129 : label is "ENABLED";
+    attribute GSR of FF_128 : label is "ENABLED";
+    attribute GSR of FF_127 : label is "ENABLED";
+    attribute GSR of FF_126 : label is "ENABLED";
+    attribute GSR of FF_125 : label is "ENABLED";
+    attribute GSR of FF_124 : label is "ENABLED";
+    attribute GSR of FF_123 : label is "ENABLED";
+    attribute GSR of FF_122 : label is "ENABLED";
+    attribute GSR of FF_121 : label is "ENABLED";
+    attribute GSR of FF_120 : label is "ENABLED";
+    attribute GSR of FF_119 : label is "ENABLED";
+    attribute GSR of FF_118 : label is "ENABLED";
+    attribute GSR of FF_117 : label is "ENABLED";
+    attribute GSR of FF_116 : label is "ENABLED";
+    attribute GSR of FF_115 : label is "ENABLED";
+    attribute GSR of FF_114 : label is "ENABLED";
+    attribute GSR of FF_113 : label is "ENABLED";
+    attribute GSR of FF_112 : label is "ENABLED";
+    attribute GSR of FF_111 : label is "ENABLED";
+    attribute GSR of FF_110 : label is "ENABLED";
+    attribute GSR of FF_109 : label is "ENABLED";
+    attribute GSR of FF_108 : label is "ENABLED";
+    attribute GSR of FF_107 : label is "ENABLED";
+    attribute GSR of FF_106 : label is "ENABLED";
+    attribute GSR of FF_105 : label is "ENABLED";
+    attribute GSR of FF_104 : label is "ENABLED";
+    attribute GSR of FF_103 : label is "ENABLED";
+    attribute GSR of FF_102 : label is "ENABLED";
+    attribute GSR of FF_101 : label is "ENABLED";
+    attribute GSR of FF_100 : label is "ENABLED";
+    attribute GSR of FF_99 : label is "ENABLED";
+    attribute GSR of FF_98 : label is "ENABLED";
+    attribute GSR of FF_97 : label is "ENABLED";
+    attribute GSR of FF_96 : label is "ENABLED";
+    attribute GSR of FF_95 : label is "ENABLED";
+    attribute GSR of FF_94 : label is "ENABLED";
+    attribute GSR of FF_93 : label is "ENABLED";
+    attribute GSR of FF_92 : label is "ENABLED";
+    attribute GSR of FF_91 : label is "ENABLED";
+    attribute GSR of FF_90 : label is "ENABLED";
+    attribute GSR of FF_89 : label is "ENABLED";
+    attribute GSR of FF_88 : label is "ENABLED";
+    attribute GSR of FF_87 : label is "ENABLED";
+    attribute GSR of FF_86 : label is "ENABLED";
+    attribute GSR of FF_85 : label is "ENABLED";
+    attribute GSR of FF_84 : label is "ENABLED";
+    attribute GSR of FF_83 : label is "ENABLED";
+    attribute GSR of FF_82 : label is "ENABLED";
+    attribute GSR of FF_81 : label is "ENABLED";
+    attribute GSR of FF_80 : label is "ENABLED";
+    attribute GSR of FF_79 : label is "ENABLED";
+    attribute GSR of FF_78 : label is "ENABLED";
+    attribute GSR of FF_77 : label is "ENABLED";
+    attribute GSR of FF_76 : label is "ENABLED";
+    attribute GSR of FF_75 : label is "ENABLED";
+    attribute GSR of FF_74 : label is "ENABLED";
+    attribute GSR of FF_73 : label is "ENABLED";
+    attribute GSR of FF_72 : label is "ENABLED";
+    attribute GSR of FF_71 : label is "ENABLED";
+    attribute GSR of FF_70 : label is "ENABLED";
+    attribute GSR of FF_69 : label is "ENABLED";
+    attribute GSR of FF_68 : label is "ENABLED";
+    attribute GSR of FF_67 : label is "ENABLED";
+    attribute GSR of FF_66 : label is "ENABLED";
+    attribute GSR of FF_65 : label is "ENABLED";
+    attribute GSR of FF_64 : label is "ENABLED";
+    attribute GSR of FF_63 : label is "ENABLED";
+    attribute GSR of FF_62 : label is "ENABLED";
+    attribute GSR of FF_61 : label is "ENABLED";
+    attribute GSR of FF_60 : label is "ENABLED";
+    attribute GSR of FF_59 : label is "ENABLED";
+    attribute GSR of FF_58 : label is "ENABLED";
+    attribute GSR of FF_57 : label is "ENABLED";
+    attribute GSR of FF_56 : label is "ENABLED";
+    attribute GSR of FF_55 : label is "ENABLED";
+    attribute GSR of FF_54 : label is "ENABLED";
+    attribute GSR of FF_53 : label is "ENABLED";
+    attribute GSR of FF_52 : label is "ENABLED";
+    attribute GSR of FF_51 : label is "ENABLED";
+    attribute GSR of FF_50 : label is "ENABLED";
+    attribute GSR of FF_49 : label is "ENABLED";
+    attribute GSR of FF_48 : label is "ENABLED";
+    attribute GSR of FF_47 : label is "ENABLED";
+    attribute GSR of FF_46 : label is "ENABLED";
+    attribute GSR of FF_45 : label is "ENABLED";
+    attribute GSR of FF_44 : label is "ENABLED";
+    attribute GSR of FF_43 : label is "ENABLED";
+    attribute GSR of FF_42 : label is "ENABLED";
+    attribute GSR of FF_41 : label is "ENABLED";
+    attribute GSR of FF_40 : label is "ENABLED";
+    attribute GSR of FF_39 : label is "ENABLED";
+    attribute GSR of FF_38 : label is "ENABLED";
+    attribute GSR of FF_37 : label is "ENABLED";
+    attribute GSR of FF_36 : label is "ENABLED";
+    attribute GSR of FF_35 : label is "ENABLED";
+    attribute GSR of FF_34 : label is "ENABLED";
+    attribute GSR of FF_33 : label is "ENABLED";
+    attribute GSR of FF_32 : label is "ENABLED";
+    attribute GSR of FF_31 : label is "ENABLED";
+    attribute GSR of FF_30 : label is "ENABLED";
+    attribute GSR of FF_29 : label is "ENABLED";
+    attribute GSR of FF_28 : label is "ENABLED";
+    attribute GSR of FF_27 : label is "ENABLED";
+    attribute GSR of FF_26 : label is "ENABLED";
+    attribute GSR of FF_25 : label is "ENABLED";
+    attribute GSR of FF_24 : label is "ENABLED";
+    attribute GSR of FF_23 : label is "ENABLED";
+    attribute GSR of FF_22 : label is "ENABLED";
+    attribute GSR of FF_21 : label is "ENABLED";
+    attribute GSR of FF_20 : label is "ENABLED";
+    attribute GSR of FF_19 : label is "ENABLED";
+    attribute GSR of FF_18 : label is "ENABLED";
+    attribute GSR of FF_17 : label is "ENABLED";
+    attribute GSR of FF_16 : label is "ENABLED";
+    attribute GSR of FF_15 : label is "ENABLED";
+    attribute GSR of FF_14 : label is "ENABLED";
+    attribute GSR of FF_13 : label is "ENABLED";
+    attribute GSR of FF_12 : label is "ENABLED";
+    attribute GSR of FF_11 : label is "ENABLED";
+    attribute GSR of FF_10 : label is "ENABLED";
+    attribute GSR of FF_9 : label is "ENABLED";
+    attribute GSR of FF_8 : label is "ENABLED";
+    attribute GSR of FF_7 : label is "ENABLED";
+    attribute GSR of FF_6 : label is "ENABLED";
+    attribute GSR of FF_5 : label is "ENABLED";
+    attribute GSR of FF_4 : label is "ENABLED";
+    attribute GSR of FF_3 : label is "ENABLED";
+    attribute GSR of FF_2 : label is "ENABLED";
+    attribute GSR of FF_1 : label is "ENABLED";
+    attribute GSR of FF_0 : label is "ENABLED";
+    attribute syn_keep : boolean;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    AND2_t25: AND2
+        port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+    INV_1: INV
+        port map (A=>full_i, Z=>invout_1);
+
+    AND2_t24: AND2
+        port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+    INV_0: INV
+        port map (A=>empty_i, Z=>invout_0);
+
+    OR2_t23: OR2
+        port map (A=>Reset, B=>RPReset, Z=>rRst);
+
+    XOR2_t22: XOR2
+        port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
+
+    XOR2_t21: XOR2
+        port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
+
+    XOR2_t20: XOR2
+        port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
+
+    XOR2_t19: XOR2
+        port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
+
+    XOR2_t18: XOR2
+        port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
+
+    XOR2_t17: XOR2
+        port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
+
+    XOR2_t16: XOR2
+        port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
+
+    XOR2_t15: XOR2
+        port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
+
+    XOR2_t14: XOR2
+        port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
+
+    XOR2_t13: XOR2
+        port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
+
+    XOR2_t12: XOR2
+        port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);
+
+    XOR2_t11: XOR2
+        port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
+
+    XOR2_t10: XOR2
+        port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
+
+    XOR2_t9: XOR2
+        port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
+
+    XOR2_t8: XOR2
+        port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
+
+    XOR2_t7: XOR2
+        port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
+
+    XOR2_t6: XOR2
+        port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
+
+    XOR2_t5: XOR2
+        port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
+
+    XOR2_t4: XOR2
+        port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
+
+    XOR2_t3: XOR2
+        port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
+
+    XOR2_t2: XOR2
+        port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);
+
+    XOR2_t1: XOR2
+        port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10);
+
+    LUT4_36: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, 
+            AD1=>w_gcount_r210, AD0=>w_gcount_r211, 
+            DO0=>w_g2b_xor_cluster_0);
+
+    LUT4_35: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, 
+            AD1=>w_gcount_r26, AD0=>w_gcount_r27, 
+            DO0=>w_g2b_xor_cluster_1);
+
+    LUT4_34: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, 
+            AD1=>w_gcount_r22, AD0=>w_gcount_r23, 
+            DO0=>w_g2b_xor_cluster_2);
+
+    LUT4_33: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, AD1=>scuba_vlo, 
+            AD0=>scuba_vlo, DO0=>wcount_r10);
+
+    LUT4_32: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, 
+            AD1=>w_gcount_r211, AD0=>scuba_vlo, DO0=>wcount_r9);
+
+    LUT4_31: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, 
+            AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7);
+
+    LUT4_30: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, 
+            AD1=>w_gcount_r28, AD0=>wcount_r9, DO0=>wcount_r6);
+
+    LUT4_29: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, 
+            AD1=>w_gcount_r27, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r5);
+
+    LUT4_28: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
+            AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r4);
+
+    LUT4_27: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
+            AD1=>w_gcount_r23, AD0=>scuba_vlo, DO0=>wcount_r3);
+
+    LUT4_26: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
+            AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>wcount_r2);
+
+    LUT4_25: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, 
+            AD1=>w_gcount_r23, AD0=>scuba_vlo, 
+            DO0=>w_g2b_xor_cluster_2_1);
+
+    LUT4_24: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
+            AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r1);
+
+    LUT4_23: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
+            AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r0);
+
+    LUT4_22: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, 
+            AD1=>r_gcount_w210, AD0=>r_gcount_w211, 
+            DO0=>r_g2b_xor_cluster_0);
+
+    LUT4_21: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, 
+            AD1=>r_gcount_w26, AD0=>r_gcount_w27, 
+            DO0=>r_g2b_xor_cluster_1);
+
+    LUT4_20: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, 
+            AD1=>r_gcount_w22, AD0=>r_gcount_w23, 
+            DO0=>r_g2b_xor_cluster_2);
+
+    LUT4_19: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, AD1=>scuba_vlo, 
+            AD0=>scuba_vlo, DO0=>rcount_w10);
+
+    LUT4_18: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, 
+            AD1=>r_gcount_w211, AD0=>scuba_vlo, DO0=>rcount_w9);
+
+    LUT4_17: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, 
+            AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7);
+
+    LUT4_16: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, 
+            AD1=>r_gcount_w28, AD0=>rcount_w9, DO0=>rcount_w6);
+
+    LUT4_15: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, 
+            AD1=>r_gcount_w27, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w5);
+
+    LUT4_14: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
+            AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w4);
+
+    LUT4_13: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
+            AD1=>r_gcount_w23, AD0=>scuba_vlo, DO0=>rcount_w3);
+
+    LUT4_12: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
+            AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>rcount_w2);
+
+    LUT4_11: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, 
+            AD1=>r_gcount_w23, AD0=>scuba_vlo, 
+            DO0=>r_g2b_xor_cluster_2_1);
+
+    LUT4_10: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
+            AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w1);
+
+    LUT4_9: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
+            AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w0);
+
+    XOR2_t0: XOR2
+        port map (A=>wptr_11, B=>r_gcount_w211, Z=>wfill_sub_msb);
+
+    LUT4_8: ROM16X1A
+        generic map (initval=> X"0410")
+        port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r211, 
+            AD0=>scuba_vlo, DO0=>empty_cmp_set);
+
+    LUT4_7: ROM16X1A
+        generic map (initval=> X"1004")
+        port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r211, 
+            AD0=>scuba_vlo, DO0=>empty_cmp_clr);
+
+    LUT4_6: ROM16X1A
+        generic map (initval=> X"0140")
+        port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w211, 
+            AD0=>scuba_vlo, DO0=>full_cmp_set);
+
+    LUT4_5: ROM16X1A
+        generic map (initval=> X"4001")
+        port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w211, 
+            AD0=>scuba_vlo, DO0=>full_cmp_clr);
+
+    LUT4_4: ROM16X1A
+        generic map (initval=> X"4c32")
+        port map (AD3=>af_setcount_11, AD2=>wcount_11, 
+            AD1=>r_gcount_w211, AD0=>wptr_11, DO0=>af_set_cmp_set);
+
+    LUT4_3: ROM16X1A
+        generic map (initval=> X"8001")
+        port map (AD3=>af_setcount_11, AD2=>wcount_11, 
+            AD1=>r_gcount_w211, AD0=>wptr_11, DO0=>af_set_cmp_clr);
+
+    LUT4_2: ROM16X1A
+        generic map (initval=> X"4c32")
+        port map (AD3=>af_clrcount_11, AD2=>wcount_11, 
+            AD1=>r_gcount_w211, AD0=>wptr_11, DO0=>af_clr_cmp_set);
+
+    LUT4_1: ROM16X1A
+        generic map (initval=> X"8001")
+        port map (AD3=>af_clrcount_11, AD2=>wcount_11, 
+            AD1=>r_gcount_w211, AD0=>wptr_11, DO0=>af_clr_cmp_clr);
+
+    LUT4_0: ROM16X1A
+        generic map (initval=> X"4450")
+        port map (AD3=>af, AD2=>af_set, AD1=>af_clr, AD0=>scuba_vlo, 
+            DO0=>af_d);
+
+    pdp_ram_0_0_1: DP16KC
+        generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), 
+            DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), 
+            DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, 
+            DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, 
+            ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, 
+            ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, 
+            ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, 
+            WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, 
+            CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, 
+            ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, 
+            ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, 
+            ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>scuba_vhi, 
+            WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo, 
+            CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, 
+            DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, 
+            DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, 
+            DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, 
+            DOA16=>open, DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>Q(2), 
+            DOB3=>Q(3), DOB4=>Q(4), DOB5=>Q(5), DOB6=>Q(6), DOB7=>Q(7), 
+            DOB8=>Q(8), DOB9=>open, DOB10=>open, DOB11=>open, 
+            DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
+            DOB16=>open, DOB17=>open);
+
+    pdp_ram_0_1_0: DP16KC
+        generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11), 
+            DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14), 
+            DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, 
+            DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, 
+            ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, 
+            ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, 
+            ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, 
+            ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, 
+            CLKB=>RdClock, OCEB=>scuba_vhi, WEB=>scuba_vlo, 
+            CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, 
+            RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, 
+            DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, 
+            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, 
+            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, 
+            DOA17=>open, DOB0=>Q(9), DOB1=>Q(10), DOB2=>Q(11), 
+            DOB3=>Q(12), DOB4=>Q(13), DOB5=>Q(14), DOB6=>Q(15), 
+            DOB7=>Q(16), DOB8=>Q(17), DOB9=>open, DOB10=>open, 
+            DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, 
+            DOB15=>open, DOB16=>open, DOB17=>open);
+
+    FF_158: FD1P3BX
+        port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, 
+            Q=>wcount_0);
+
+    FF_157: FD1P3DX
+        port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_1);
+
+    FF_156: FD1P3DX
+        port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_2);
+
+    FF_155: FD1P3DX
+        port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_3);
+
+    FF_154: FD1P3DX
+        port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_4);
+
+    FF_153: FD1P3DX
+        port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_5);
+
+    FF_152: FD1P3DX
+        port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_6);
+
+    FF_151: FD1P3DX
+        port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_7);
+
+    FF_150: FD1P3DX
+        port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_8);
+
+    FF_149: FD1P3DX
+        port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_9);
+
+    FF_148: FD1P3DX
+        port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_10);
+
+    FF_147: FD1P3DX
+        port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_11);
+
+    FF_146: FD1P3DX
+        port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_0);
+
+    FF_145: FD1P3DX
+        port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_1);
+
+    FF_144: FD1P3DX
+        port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_2);
+
+    FF_143: FD1P3DX
+        port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_3);
+
+    FF_142: FD1P3DX
+        port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_4);
+
+    FF_141: FD1P3DX
+        port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_5);
+
+    FF_140: FD1P3DX
+        port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_6);
+
+    FF_139: FD1P3DX
+        port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_7);
+
+    FF_138: FD1P3DX
+        port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_8);
+
+    FF_137: FD1P3DX
+        port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_9);
+
+    FF_136: FD1P3DX
+        port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_10);
+
+    FF_135: FD1P3DX
+        port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_11);
+
+    FF_134: FD1P3DX
+        port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_0);
+
+    FF_133: FD1P3DX
+        port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_1);
+
+    FF_132: FD1P3DX
+        port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_2);
+
+    FF_131: FD1P3DX
+        port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_3);
+
+    FF_130: FD1P3DX
+        port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_4);
+
+    FF_129: FD1P3DX
+        port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_5);
+
+    FF_128: FD1P3DX
+        port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_6);
+
+    FF_127: FD1P3DX
+        port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_7);
+
+    FF_126: FD1P3DX
+        port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_8);
+
+    FF_125: FD1P3DX
+        port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_9);
+
+    FF_124: FD1P3DX
+        port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_10);
+
+    FF_123: FD1P3DX
+        port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_11);
+
+    FF_122: FD1P3BX
+        port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, 
+            Q=>rcount_0);
+
+    FF_121: FD1P3DX
+        port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_1);
+
+    FF_120: FD1P3DX
+        port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_2);
+
+    FF_119: FD1P3DX
+        port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_3);
+
+    FF_118: FD1P3DX
+        port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_4);
+
+    FF_117: FD1P3DX
+        port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_5);
+
+    FF_116: FD1P3DX
+        port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_6);
+
+    FF_115: FD1P3DX
+        port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_7);
+
+    FF_114: FD1P3DX
+        port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_8);
+
+    FF_113: FD1P3DX
+        port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_9);
+
+    FF_112: FD1P3DX
+        port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_10);
+
+    FF_111: FD1P3DX
+        port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_11);
+
+    FF_110: FD1P3DX
+        port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_0);
+
+    FF_109: FD1P3DX
+        port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_1);
+
+    FF_108: FD1P3DX
+        port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_2);
+
+    FF_107: FD1P3DX
+        port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_3);
+
+    FF_106: FD1P3DX
+        port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_4);
+
+    FF_105: FD1P3DX
+        port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_5);
+
+    FF_104: FD1P3DX
+        port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_6);
+
+    FF_103: FD1P3DX
+        port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_7);
+
+    FF_102: FD1P3DX
+        port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_8);
+
+    FF_101: FD1P3DX
+        port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_9);
+
+    FF_100: FD1P3DX
+        port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_10);
+
+    FF_99: FD1P3DX
+        port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_11);
+
+    FF_98: FD1P3DX
+        port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_0);
+
+    FF_97: FD1P3DX
+        port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_1);
+
+    FF_96: FD1P3DX
+        port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_2);
+
+    FF_95: FD1P3DX
+        port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_3);
+
+    FF_94: FD1P3DX
+        port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_4);
+
+    FF_93: FD1P3DX
+        port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_5);
+
+    FF_92: FD1P3DX
+        port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_6);
+
+    FF_91: FD1P3DX
+        port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_7);
+
+    FF_90: FD1P3DX
+        port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_8);
+
+    FF_89: FD1P3DX
+        port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_9);
+
+    FF_88: FD1P3DX
+        port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_10);
+
+    FF_87: FD1P3DX
+        port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_11);
+
+    FF_86: FD1S3DX
+        port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
+
+    FF_85: FD1S3DX
+        port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
+
+    FF_84: FD1S3DX
+        port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
+
+    FF_83: FD1S3DX
+        port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
+
+    FF_82: FD1S3DX
+        port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
+
+    FF_81: FD1S3DX
+        port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
+
+    FF_80: FD1S3DX
+        port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
+
+    FF_79: FD1S3DX
+        port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
+
+    FF_78: FD1S3DX
+        port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
+
+    FF_77: FD1S3DX
+        port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
+
+    FF_76: FD1S3DX
+        port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r10);
+
+    FF_75: FD1S3DX
+        port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r11);
+
+    FF_74: FD1S3DX
+        port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
+
+    FF_73: FD1S3DX
+        port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
+
+    FF_72: FD1S3DX
+        port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
+
+    FF_71: FD1S3DX
+        port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
+
+    FF_70: FD1S3DX
+        port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
+
+    FF_69: FD1S3DX
+        port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
+
+    FF_68: FD1S3DX
+        port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
+
+    FF_67: FD1S3DX
+        port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
+
+    FF_66: FD1S3DX
+        port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
+
+    FF_65: FD1S3DX
+        port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
+
+    FF_64: FD1S3DX
+        port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);
+
+    FF_63: FD1S3DX
+        port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11);
+
+    FF_62: FD1S3DX
+        port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r20);
+
+    FF_61: FD1S3DX
+        port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r21);
+
+    FF_60: FD1S3DX
+        port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r22);
+
+    FF_59: FD1S3DX
+        port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r23);
+
+    FF_58: FD1S3DX
+        port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r24);
+
+    FF_57: FD1S3DX
+        port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r25);
+
+    FF_56: FD1S3DX
+        port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r26);
+
+    FF_55: FD1S3DX
+        port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r27);
+
+    FF_54: FD1S3DX
+        port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r28);
+
+    FF_53: FD1S3DX
+        port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r29);
+
+    FF_52: FD1S3DX
+        port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r210);
+
+    FF_51: FD1S3DX
+        port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r211);
+
+    FF_50: FD1S3DX
+        port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
+
+    FF_49: FD1S3DX
+        port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
+
+    FF_48: FD1S3DX
+        port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
+
+    FF_47: FD1S3DX
+        port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
+
+    FF_46: FD1S3DX
+        port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
+
+    FF_45: FD1S3DX
+        port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
+
+    FF_44: FD1S3DX
+        port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
+
+    FF_43: FD1S3DX
+        port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
+
+    FF_42: FD1S3DX
+        port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
+
+    FF_41: FD1S3DX
+        port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
+
+    FF_40: FD1S3DX
+        port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, 
+            Q=>r_gcount_w210);
+
+    FF_39: FD1S3DX
+        port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, 
+            Q=>r_gcount_w211);
+
+    FF_38: FD1S3DX
+        port map (D=>wfill_sub_0, CK=>WrClock, CD=>Reset, Q=>WCNT(0));
+
+    FF_37: FD1S3DX
+        port map (D=>wfill_sub_1, CK=>WrClock, CD=>Reset, Q=>WCNT(1));
+
+    FF_36: FD1S3DX
+        port map (D=>wfill_sub_2, CK=>WrClock, CD=>Reset, Q=>WCNT(2));
+
+    FF_35: FD1S3DX
+        port map (D=>wfill_sub_3, CK=>WrClock, CD=>Reset, Q=>WCNT(3));
+
+    FF_34: FD1S3DX
+        port map (D=>wfill_sub_4, CK=>WrClock, CD=>Reset, Q=>WCNT(4));
+
+    FF_33: FD1S3DX
+        port map (D=>wfill_sub_5, CK=>WrClock, CD=>Reset, Q=>WCNT(5));
+
+    FF_32: FD1S3DX
+        port map (D=>wfill_sub_6, CK=>WrClock, CD=>Reset, Q=>WCNT(6));
+
+    FF_31: FD1S3DX
+        port map (D=>wfill_sub_7, CK=>WrClock, CD=>Reset, Q=>WCNT(7));
+
+    FF_30: FD1S3DX
+        port map (D=>wfill_sub_8, CK=>WrClock, CD=>Reset, Q=>WCNT(8));
+
+    FF_29: FD1S3DX
+        port map (D=>wfill_sub_9, CK=>WrClock, CD=>Reset, Q=>WCNT(9));
+
+    FF_28: FD1S3DX
+        port map (D=>wfill_sub_10, CK=>WrClock, CD=>Reset, Q=>WCNT(10));
+
+    FF_27: FD1S3DX
+        port map (D=>wfill_sub_11, CK=>WrClock, CD=>Reset, Q=>WCNT(11));
+
+    FF_26: FD1S3BX
+        port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
+
+    FF_25: FD1S3DX
+        port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
+
+    FF_24: FD1P3BX
+        port map (D=>iaf_setcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, 
+            Q=>af_setcount_0);
+
+    FF_23: FD1P3DX
+        port map (D=>iaf_setcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>af_setcount_1);
+
+    FF_22: FD1P3DX
+        port map (D=>iaf_setcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>af_setcount_2);
+
+    FF_21: FD1P3BX
+        port map (D=>iaf_setcount_3, SP=>wren_i, CK=>WrClock, PD=>Reset, 
+            Q=>af_setcount_3);
+
+    FF_20: FD1P3DX
+        port map (D=>iaf_setcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>af_setcount_4);
+
+    FF_19: FD1P3DX
+        port map (D=>iaf_setcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>af_setcount_5);
+
+    FF_18: FD1P3DX
+        port map (D=>iaf_setcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>af_setcount_6);
+
+    FF_17: FD1P3DX
+        port map (D=>iaf_setcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>af_setcount_7);
+
+    FF_16: FD1P3DX
+        port map (D=>iaf_setcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>af_setcount_8);
+
+    FF_15: FD1P3DX
+        port map (D=>iaf_setcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>af_setcount_9);
+
+    FF_14: FD1P3DX
+        port map (D=>iaf_setcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>af_setcount_10);
+
+    FF_13: FD1P3DX
+        port map (D=>iaf_setcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>af_setcount_11);
+
+    FF_12: FD1P3BX
+        port map (D=>iaf_clrcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, 
+            Q=>af_clrcount_0);
+
+    FF_11: FD1P3BX
+        port map (D=>iaf_clrcount_1, SP=>wren_i, CK=>WrClock, PD=>Reset, 
+            Q=>af_clrcount_1);
+
+    FF_10: FD1P3DX
+        port map (D=>iaf_clrcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>af_clrcount_2);
+
+    FF_9: FD1P3BX
+        port map (D=>iaf_clrcount_3, SP=>wren_i, CK=>WrClock, PD=>Reset, 
+            Q=>af_clrcount_3);
+
+    FF_8: FD1P3DX
+        port map (D=>iaf_clrcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>af_clrcount_4);
+
+    FF_7: FD1P3DX
+        port map (D=>iaf_clrcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>af_clrcount_5);
+
+    FF_6: FD1P3DX
+        port map (D=>iaf_clrcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>af_clrcount_6);
+
+    FF_5: FD1P3DX
+        port map (D=>iaf_clrcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>af_clrcount_7);
+
+    FF_4: FD1P3DX
+        port map (D=>iaf_clrcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>af_clrcount_8);
+
+    FF_3: FD1P3DX
+        port map (D=>iaf_clrcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>af_clrcount_9);
+
+    FF_2: FD1P3DX
+        port map (D=>iaf_clrcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>af_clrcount_10);
+
+    FF_1: FD1P3DX
+        port map (D=>iaf_clrcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>af_clrcount_11);
+
+    FF_0: FD1S3DX
+        port map (D=>af_d, CK=>WrClock, CD=>Reset, Q=>af);
+
+    w_gctr_cia: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, 
+            S1=>open);
+
+    w_gctr_0: CU2
+        port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, 
+            NC0=>iwcount_0, NC1=>iwcount_1);
+
+    w_gctr_1: CU2
+        port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, 
+            NC0=>iwcount_2, NC1=>iwcount_3);
+
+    w_gctr_2: CU2
+        port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, 
+            NC0=>iwcount_4, NC1=>iwcount_5);
+
+    w_gctr_3: CU2
+        port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, 
+            NC0=>iwcount_6, NC1=>iwcount_7);
+
+    w_gctr_4: CU2
+        port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, 
+            NC0=>iwcount_8, NC1=>iwcount_9);
+
+    w_gctr_5: CU2
+        port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, 
+            NC0=>iwcount_10, NC1=>iwcount_11);
+
+    r_gctr_cia: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, 
+            S1=>open);
+
+    r_gctr_0: CU2
+        port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, 
+            NC0=>ircount_0, NC1=>ircount_1);
+
+    r_gctr_1: CU2
+        port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, 
+            NC0=>ircount_2, NC1=>ircount_3);
+
+    r_gctr_2: CU2
+        port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, 
+            NC0=>ircount_4, NC1=>ircount_5);
+
+    r_gctr_3: CU2
+        port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, 
+            NC0=>ircount_6, NC1=>ircount_7);
+
+    r_gctr_4: CU2
+        port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, 
+            NC0=>ircount_8, NC1=>ircount_9);
+
+    r_gctr_5: CU2
+        port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, 
+            NC0=>ircount_10, NC1=>ircount_11);
+
+    precin_inst311: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>scuba_vlo, COUT=>precin, S0=>open, 
+            S1=>open);
+
+    wfill_0: FSUB2B
+        port map (A0=>scuba_vhi, A1=>wptr_0, B0=>scuba_vlo, 
+            B1=>rcount_w0, BI=>precin, BOUT=>co0_2, S0=>open, 
+            S1=>wfill_sub_0);
+
+    wfill_1: FSUB2B
+        port map (A0=>wptr_1, A1=>wptr_2, B0=>rcount_w1, B1=>rcount_w2, 
+            BI=>co0_2, BOUT=>co1_2, S0=>wfill_sub_1, S1=>wfill_sub_2);
+
+    wfill_2: FSUB2B
+        port map (A0=>wptr_3, A1=>wptr_4, B0=>rcount_w3, B1=>rcount_w4, 
+            BI=>co1_2, BOUT=>co2_2, S0=>wfill_sub_3, S1=>wfill_sub_4);
+
+    wfill_3: FSUB2B
+        port map (A0=>wptr_5, A1=>wptr_6, B0=>rcount_w5, B1=>rcount_w6, 
+            BI=>co2_2, BOUT=>co3_2, S0=>wfill_sub_5, S1=>wfill_sub_6);
+
+    wfill_4: FSUB2B
+        port map (A0=>wptr_7, A1=>wptr_8, B0=>rcount_w7, 
+            B1=>r_g2b_xor_cluster_0, BI=>co3_2, BOUT=>co4_2, 
+            S0=>wfill_sub_7, S1=>wfill_sub_8);
+
+    wfill_5: FSUB2B
+        port map (A0=>wptr_9, A1=>wptr_10, B0=>rcount_w9, B1=>rcount_w10, 
+            BI=>co4_2, BOUT=>co5_2, S0=>wfill_sub_9, S1=>wfill_sub_10);
+
+    wfill_6: FSUB2B
+        port map (A0=>wfill_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, BI=>co5_2, BOUT=>open, S0=>wfill_sub_11, 
+            S1=>open);
+
+    empty_cmp_ci_a: FADD2B
+        port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, 
+            CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
+
+    empty_cmp_0: AGEB2
+        port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, 
+            B1=>wcount_r1, CI=>cmp_ci, GE=>co0_3);
+
+    empty_cmp_1: AGEB2
+        port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, 
+            B1=>wcount_r3, CI=>co0_3, GE=>co1_3);
+
+    empty_cmp_2: AGEB2
+        port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, 
+            B1=>wcount_r5, CI=>co1_3, GE=>co2_3);
+
+    empty_cmp_3: AGEB2
+        port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, 
+            B1=>wcount_r7, CI=>co2_3, GE=>co3_3);
+
+    empty_cmp_4: AGEB2
+        port map (A0=>rcount_8, A1=>rcount_9, B0=>w_g2b_xor_cluster_0, 
+            B1=>wcount_r9, CI=>co3_3, GE=>co4_3);
+
+    empty_cmp_5: AGEB2
+        port map (A0=>rcount_10, A1=>empty_cmp_set, B0=>wcount_r10, 
+            B1=>empty_cmp_clr, CI=>co4_3, GE=>empty_d_c);
+
+    a0: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, 
+            S1=>open);
+
+    full_cmp_ci_a: FADD2B
+        port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, 
+            CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
+
+    full_cmp_0: AGEB2
+        port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, 
+            B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_4);
+
+    full_cmp_1: AGEB2
+        port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, 
+            B1=>rcount_w3, CI=>co0_4, GE=>co1_4);
+
+    full_cmp_2: AGEB2
+        port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, 
+            B1=>rcount_w5, CI=>co1_4, GE=>co2_4);
+
+    full_cmp_3: AGEB2
+        port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, 
+            B1=>rcount_w7, CI=>co2_4, GE=>co3_4);
+
+    full_cmp_4: AGEB2
+        port map (A0=>wcount_8, A1=>wcount_9, B0=>r_g2b_xor_cluster_0, 
+            B1=>rcount_w9, CI=>co3_4, GE=>co4_4);
+
+    full_cmp_5: AGEB2
+        port map (A0=>wcount_10, A1=>full_cmp_set, B0=>rcount_w10, 
+            B1=>full_cmp_clr, CI=>co4_4, GE=>full_d_c);
+
+    a1: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, 
+            S1=>open);
+
+    af_set_ctr_cia: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>af_set_ctr_ci, S0=>open, 
+            S1=>open);
+
+    af_set_ctr_0: CU2
+        port map (CI=>af_set_ctr_ci, PC0=>af_setcount_0, 
+            PC1=>af_setcount_1, CO=>co0_5, NC0=>iaf_setcount_0, 
+            NC1=>iaf_setcount_1);
+
+    af_set_ctr_1: CU2
+        port map (CI=>co0_5, PC0=>af_setcount_2, PC1=>af_setcount_3, 
+            CO=>co1_5, NC0=>iaf_setcount_2, NC1=>iaf_setcount_3);
+
+    af_set_ctr_2: CU2
+        port map (CI=>co1_5, PC0=>af_setcount_4, PC1=>af_setcount_5, 
+            CO=>co2_5, NC0=>iaf_setcount_4, NC1=>iaf_setcount_5);
+
+    af_set_ctr_3: CU2
+        port map (CI=>co2_5, PC0=>af_setcount_6, PC1=>af_setcount_7, 
+            CO=>co3_5, NC0=>iaf_setcount_6, NC1=>iaf_setcount_7);
+
+    af_set_ctr_4: CU2
+        port map (CI=>co3_5, PC0=>af_setcount_8, PC1=>af_setcount_9, 
+            CO=>co4_5, NC0=>iaf_setcount_8, NC1=>iaf_setcount_9);
+
+    af_set_ctr_5: CU2
+        port map (CI=>co4_5, PC0=>af_setcount_10, PC1=>af_setcount_11, 
+            CO=>co5_3, NC0=>iaf_setcount_10, NC1=>iaf_setcount_11);
+
+    af_set_cmp_ci_a: FADD2B
+        port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, 
+            CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open);
+
+    af_set_cmp_0: AGEB2
+        port map (A0=>af_setcount_0, A1=>af_setcount_1, B0=>rcount_w0, 
+            B1=>rcount_w1, CI=>cmp_ci_2, GE=>co0_6);
+
+    af_set_cmp_1: AGEB2
+        port map (A0=>af_setcount_2, A1=>af_setcount_3, B0=>rcount_w2, 
+            B1=>rcount_w3, CI=>co0_6, GE=>co1_6);
+
+    af_set_cmp_2: AGEB2
+        port map (A0=>af_setcount_4, A1=>af_setcount_5, B0=>rcount_w4, 
+            B1=>rcount_w5, CI=>co1_6, GE=>co2_6);
+
+    af_set_cmp_3: AGEB2
+        port map (A0=>af_setcount_6, A1=>af_setcount_7, B0=>rcount_w6, 
+            B1=>rcount_w7, CI=>co2_6, GE=>co3_6);
+
+    af_set_cmp_4: AGEB2
+        port map (A0=>af_setcount_8, A1=>af_setcount_9, 
+            B0=>r_g2b_xor_cluster_0, B1=>rcount_w9, CI=>co3_6, GE=>co4_6);
+
+    af_set_cmp_5: AGEB2
+        port map (A0=>af_setcount_10, A1=>af_set_cmp_set, B0=>rcount_w10, 
+            B1=>af_set_cmp_clr, CI=>co4_6, GE=>af_set_c);
+
+    a2: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>af_set_c, COUT=>open, S0=>af_set, 
+            S1=>open);
+
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    af_clr_ctr_cia: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>af_clr_ctr_ci, S0=>open, 
+            S1=>open);
+
+    af_clr_ctr_0: CU2
+        port map (CI=>af_clr_ctr_ci, PC0=>af_clrcount_0, 
+            PC1=>af_clrcount_1, CO=>co0_7, NC0=>iaf_clrcount_0, 
+            NC1=>iaf_clrcount_1);
+
+    af_clr_ctr_1: CU2
+        port map (CI=>co0_7, PC0=>af_clrcount_2, PC1=>af_clrcount_3, 
+            CO=>co1_7, NC0=>iaf_clrcount_2, NC1=>iaf_clrcount_3);
+
+    af_clr_ctr_2: CU2
+        port map (CI=>co1_7, PC0=>af_clrcount_4, PC1=>af_clrcount_5, 
+            CO=>co2_7, NC0=>iaf_clrcount_4, NC1=>iaf_clrcount_5);
+
+    af_clr_ctr_3: CU2
+        port map (CI=>co2_7, PC0=>af_clrcount_6, PC1=>af_clrcount_7, 
+            CO=>co3_7, NC0=>iaf_clrcount_6, NC1=>iaf_clrcount_7);
+
+    af_clr_ctr_4: CU2
+        port map (CI=>co3_7, PC0=>af_clrcount_8, PC1=>af_clrcount_9, 
+            CO=>co4_7, NC0=>iaf_clrcount_8, NC1=>iaf_clrcount_9);
+
+    af_clr_ctr_5: CU2
+        port map (CI=>co4_7, PC0=>af_clrcount_10, PC1=>af_clrcount_11, 
+            CO=>co5_4, NC0=>iaf_clrcount_10, NC1=>iaf_clrcount_11);
+
+    af_clr_cmp_ci_a: FADD2B
+        port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, 
+            CI=>scuba_vlo, COUT=>cmp_ci_3, S0=>open, S1=>open);
+
+    af_clr_cmp_0: AGEB2
+        port map (A0=>af_clrcount_0, A1=>af_clrcount_1, B0=>rcount_w0, 
+            B1=>rcount_w1, CI=>cmp_ci_3, GE=>co0_8);
+
+    af_clr_cmp_1: AGEB2
+        port map (A0=>af_clrcount_2, A1=>af_clrcount_3, B0=>rcount_w2, 
+            B1=>rcount_w3, CI=>co0_8, GE=>co1_8);
+
+    af_clr_cmp_2: AGEB2
+        port map (A0=>af_clrcount_4, A1=>af_clrcount_5, B0=>rcount_w4, 
+            B1=>rcount_w5, CI=>co1_8, GE=>co2_8);
+
+    af_clr_cmp_3: AGEB2
+        port map (A0=>af_clrcount_6, A1=>af_clrcount_7, B0=>rcount_w6, 
+            B1=>rcount_w7, CI=>co2_8, GE=>co3_8);
+
+    af_clr_cmp_4: AGEB2
+        port map (A0=>af_clrcount_8, A1=>af_clrcount_9, 
+            B0=>r_g2b_xor_cluster_0, B1=>rcount_w9, CI=>co3_8, GE=>co4_8);
+
+    af_clr_cmp_5: AGEB2
+        port map (A0=>af_clrcount_10, A1=>af_clr_cmp_set, B0=>rcount_w10, 
+            B1=>af_clr_cmp_clr, CI=>co4_8, GE=>af_clr_c);
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    a3: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>af_clr_c, COUT=>open, S0=>af_clr, 
+            S1=>open);
+
+    Empty <= empty_i;
+    Full <= full_i;
+    AlmostFull <= af;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of cbmnet_fifo_18x2k_dp is
+    for Structure
+        for all:AGEB2 use entity ecp3.AGEB2(V); end for;
+        for all:AND2 use entity ecp3.AND2(V); end for;
+        for all:CU2 use entity ecp3.CU2(V); end for;
+        for all:FADD2B use entity ecp3.FADD2B(V); end for;
+        for all:FSUB2B use entity ecp3.FSUB2B(V); end for;
+        for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
+        for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
+        for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
+        for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
+        for all:INV use entity ecp3.INV(V); end for;
+        for all:OR2 use entity ecp3.OR2(V); end for;
+        for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
+        for all:VHI use entity ecp3.VHI(V); end for;
+        for all:VLO use entity ecp3.VLO(V); end for;
+        for all:XOR2 use entity ecp3.XOR2(V); end for;
+        for all:DP16KC use entity ecp3.DP16KC(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on
diff --git a/cbmnet/test/dlm_cnt.pl b/cbmnet/test/dlm_cnt.pl
new file mode 100755
index 0000000..bb2fb8d
--- /dev/null
+++ b/cbmnet/test/dlm_cnt.pl
@@ -0,0 +1,90 @@
+#!/usr/bin/perl
+use warnings;
+use strict;
+use POSIX;
+use Time::HiRes qw(usleep gettimeofday tv_interval);
+
+$ENV{'SIMPATH'}='/d/salt/fairsoft/fairsoft_dec13/';
+
+sub getTrb3Status {
+   my $info = `./info.pl s`;
+   my $count = '-';
+   my $dlmRecv = '-';
+   
+   $count = hex($1) if $info =~ /stat_dlm_counter_i\(15 downto 0\)\s*\|\s*0x(....)/;
+   $dlmRecv = $1 if $info =~ /rx_data_sp_i0\(17 downto 0\)\s*\|\s*.+: DLM(\d+)/;
+   
+ #  print "$count $dlmRecv\n";
+   
+   return ($count, $dlmRecv);
+}
+
+my $dlm_cmd = 'ssh jspc58 "/u/mpenschuck/Documents/flesnet/build/dlm %DLM%"';
+#$dlm_cmd = 'ssh root@jspc58 "/u/mpenschuck/Downloads/dlm_nocp %DLM%"';
+if ($ARGV[0]) {
+   $dlm_cmd = '../../../flesnet/ctrl/control/cliclient/cliclient jspc58:9750 dlm 0x1 %DLM%';
+}
+
+#print $dlm_cmd;
+
+my $interval = 0 * 1e6;
+
+my @starttime = gettimeofday;
+
+my $cnt = 0;
+my $iteration = 1;
+
+my ($startCount, $dlmRecv) = getTrb3Status();
+
+printf "% 10s % 10s % 10s % 10s % 10s % 10s\n", "Time", "Iter", "Trb3Cnt", "CntDiff", "DLM sent", "DLM recv";
+
+printf "Start count: %d\n", $startCount;
+
+my $lastCount = 0;
+
+my $dlmMatches = 0;
+my $dlmMatchesOff = 0;
+my $lastDlmSend = 0;
+my %deltaHist = (-1,0, 0,0, 1,0, 2,0, 3,0, 4,0);
+
+while($iteration < 10000) {
+   my $dlm = $lastDlmSend;
+   while($dlm == $lastDlmSend || $dlm < 2) {$dlm = int(rand(16));}
+
+   my $cmd = $dlm_cmd;
+   $cmd =~ s/%DLM%/$dlm/;
+   `$cmd`;
+   
+   usleep($interval);
+   
+   my ($count, $dlmRecv) = getTrb3Status();
+   
+   my $timeEla = tv_interval([@starttime]);
+   
+   my $counts = ($count eq '-') ? '-' : (($count - $startCount) & 0xffff);
+   my $countDif = $counts - $lastCount;
+   
+   $deltaHist{$countDif}++ if (exists $deltaHist{$countDif});
+   $dlmMatches++ if ($dlmRecv == $dlm);
+   $dlmMatchesOff++ if ($dlmRecv == $lastDlmSend);
+	 
+   my $prob = '';
+   $prob = "!!!!!!" unless ($dlmRecv == $dlm);   
+
+   printf "% 10s % 10s % 10s % 10s % 10s % 10s % 10s\n", $timeEla, $iteration, $counts, $countDif, $dlm, $dlmRecv, $prob;
+
+#exit() if $countDif == 2 and $ARGV[1] or not ($dlmRecv == $dlm);;
+   
+   $lastCount = $counts;
+   $lastDlmSend = $dlm;
+   $iteration++;
+}
+
+my $totIter = $iteration-1;
+
+printf "Correct DLM recv: %d (% 3.2f %%)\n", $dlmMatches, 100 * $dlmMatches / $totIter;
+printf "Correct DLM recv (assuming 1 off): %d (% 3.2f %%)\n", $dlmMatchesOff, 100 * $dlmMatchesOff / ($totIter-1);
+print "Iterations with CntDiff:\n";
+for my $key (sort keys %deltaHist) {
+   printf "% 5s: % 5d (% 3.2f %%)\n", $key, $deltaHist{$key}, 100 * $deltaHist{$key} / $totIter;
+}
diff --git a/cbmnet/test/info.pl b/cbmnet/test/info.pl
index 640cdac..ab2db4d 100755
--- a/cbmnet/test/info.pl
+++ b/cbmnet/test/info.pl
@@ -9,6 +9,7 @@ use POSIX qw/ceil/;
 use Term::ANSIColor;
 use bigint;
 
+my $singleRun = ($ARGV[0] =~ m/s/);
 
 sub readFile {
    open FILE, "<", shift;
@@ -60,7 +61,7 @@ sub interpretLine {
 sub readRegs {
    my $endpoint = shift;
    my $length = shift;
-   my $firstReg = 0xa020;
+   my $firstReg = shift;
    my $res = `trbcmd rm $endpoint $firstReg $length 0`;
    
    my $reg = 0;
@@ -162,11 +163,15 @@ sub cbmnet_definitions {
 
 my @old_results;
 my $first_one = 1;
+my @endpoints = (
+[0x8001, 0xa020]
+#[0xf3c0, 0xa8a0]
+);
 while (1) {
    my @results = ();
 
-   for my $i (1 .. 1) {
-      my $reg = readRegs 0x8000 + $i, 0x10;
+   for my $i (0 .. $#endpoints) {
+      my $reg = readRegs $endpoints[$i]->[0], 0x10, $endpoints[$i]->[1];
       my @slices = ();
       for my $def (@defs) {
          my $idx = $def->[1];
@@ -201,7 +206,10 @@ while (1) {
    
    @old_results = @results;
 
-print `trbcmd rm 0x8001 0xa010 7 0`;   
+print `trbcmd rm 0x8001 0xa00f 8 0`;
+#print `trbcmd rm 0x9001 0xa00f 8 0`;    
+
+last if $singleRun;
 sleep 1;
 print $first_one ? `clear` : chr(27) . "[1;1H";
 $first_one = 0;
diff --git a/cbmnet/trb3_periph_cbmnet.prj b/cbmnet/trb3_periph_cbmnet.prj
index cbf6a4c..583a9b6 100755
--- a/cbmnet/trb3_periph_cbmnet.prj
+++ b/cbmnet/trb3_periph_cbmnet.prj
@@ -170,12 +170,18 @@ add_file -vhdl -lib work "./code/cbmnet_phy_ecp3.vhd"
 add_file -vhdl -lib work "./trb3_periph_cbmnet.vhd"
 
 
+add_file -vhdl -lib work "./cores/cbmnet_fifo_18x2k_dp.vhd"
 add_file -vhdl -lib work "./code/cbmnet_readout_trbnet_decoder.vhd"
 add_file -vhdl -lib work "./code/cbmnet_readout_event_packer.vhd"
-add_file -vhdl -lib work "./code/cbmnet_readout_fifo.vhd"
-add_file -vhdl -lib work "./code/cbmnet_readout_tx_fsm.vhd"
+add_file -vhdl -lib work "./code/cbmnet_readout_fifo_ecp3.vhd"
+add_file -vhdl -lib work "./code/cbmnet_readout_frame_packer.vhd"
+add_file -vhdl -lib work "./code/cbmnet_readout_tx_fifo.vhd"
+add_file -vhdl -lib work "./code/cbmnet_readout_obuf.vhd"
 add_file -vhdl -lib work "./code/cbmnet_readout.vhd"
 
+add_file -fpga_constraint "./project/trb3_periph_cbmnet_syn.fdc"
+
+
 #implementation: "workdir"
 impl -add workdir -type fpga
 
diff --git a/cbmnet/trb3_periph_cbmnet.vhd b/cbmnet/trb3_periph_cbmnet.vhd
index 4d025ac..06739bd 100755
--- a/cbmnet/trb3_periph_cbmnet.vhd
+++ b/cbmnet/trb3_periph_cbmnet.vhd
@@ -253,6 +253,15 @@ architecture trb3_periph_arch of trb3_periph_cbmnet is
    signal cbm_data2send_end     :  std_logic_vector(NUM_LANES-1 downto 0) := (others => '0');
    signal cbm_data2send         :  std_logic_vector((16*NUM_LANES)-1 downto 0) := (others => '0');
 
+   signal cbm_data2send_start1   :  std_logic_vector(NUM_LANES-1 downto 0) := (others => '0');
+   signal cbm_data2send_end1     :  std_logic_vector(NUM_LANES-1 downto 0) := (others => '0');
+   signal cbm_data2send1         :  std_logic_vector((16*NUM_LANES)-1 downto 0) := (others => '0');
+
+   signal cbm_data2send_start2   :  std_logic_vector(NUM_LANES-1 downto 0) := (others => '0');
+   signal cbm_data2send_end2     :  std_logic_vector(NUM_LANES-1 downto 0) := (others => '0');
+   signal cbm_data2send2         :  std_logic_vector((16*NUM_LANES)-1 downto 0) := (others => '0');
+
+   
    signal cbm_dlm2send_va       :  std_logic := '0';                      -- send dlm interface
    signal cbm_dlm2send          :  std_logic_vector(3 downto 0) := (others => '0');
 
@@ -283,6 +292,7 @@ architecture trb3_periph_arch of trb3_periph_cbmnet is
    signal phy_debug_i : std_logic_vector (511 downto 0) := (others => '0');
    signal phy_debug_i_buf : std_logic_vector (511 downto 0);
    
+   signal tp_mux_i : std_logic;
 
 -- Link Tester
    signal link_tester_ctrl_en   :std_logic;
@@ -308,7 +318,8 @@ architecture trb3_periph_arch of trb3_periph_cbmnet is
    signal send_num_pack_counter_i : unsigned(15 downto 0); 
    signal send_enabled_i : std_logic := '0';
    
-   signal send_wait_counter_i : unsigned(31 downto 0);
+   signal send_wait_counter_i1 : unsigned(31 downto 0);
+   signal send_wait_counter_i2 : unsigned(31 downto 0);
    signal send_wait_threshold_i : unsigned(31 downto 0);
    signal send_burst_threshold_i : unsigned(31 downto 0);
    signal send_burst_counter_i : unsigned(31 downto 0);   
@@ -402,11 +413,29 @@ architecture trb3_periph_arch of trb3_periph_cbmnet is
   signal cbm_rdo_regio_write_ack_i    : std_logic;
   signal cbm_rdo_regio_unknown_addr_i : std_logic;  
   
-  signal event_id : unsigned(15 downto 0);
-  signal send_length_i : unsigned(15 downto 0);
+  signal event_id : unsigned(31 downto 0);
+  signal send_length_i1 : unsigned(15 downto 0);
+  signal send_length_i2 : unsigned(15 downto 0);
   signal send_counter_i : unsigned(15 downto 0);
   
-  type TRB_FSM_T is (IDLE, START_READOUT, START_READOUT_WAIT1, START_READOUT_WAIT2, START_READOUT_WAIT3, FEE_BUSY, FEE_BUSY_WAIT1, FEE_BUSY_WAIT2, FEE_BUSY_WAIT3, SEND_EINF_H, SEND_EINF_L, SEND_LENGTH, SEND_SOURCE, SEND_SOURCE_WAIT, SEND_PAYLOAD_H, SEND_PAYLOAD_L, COMPL_WAIT1, COMPL_WAIT2, COMPL_WAIT3, COMPL_WAIT4, COMPL_NOT_BUSY_WAIT1, COMPL_NOT_BUSY_WAIT2, COMPL_NOT_BUSY_WAIT3, COMPL_NOT_BUSY_WAIT4, EVT_WAIT);
+  
+  signal send_length_min_i  : unsigned(15 downto 0);
+  signal send_length_max_i  : unsigned(15 downto 0);
+  signal send_length_step_i : unsigned(15 downto 0);
+  signal send_length_cnt_i  : unsigned(15 downto 0);
+
+  signal send_real_time_i : unsigned(31 downto 0);
+  signal send_real_time_buf_i : unsigned(31 downto 0);
+  
+  signal send_real_time125_i : unsigned(31 downto 0);
+  signal send_real_time125_xfer_i : unsigned(31 downto 0);
+  signal send_real_time125_buf_i : unsigned(31 downto 0);
+
+  signal event_gap_i : unsigned(31 downto 0);
+  signal event_gap_cnt_i : unsigned(31 downto 0);
+  
+  
+  type TRB_FSM_T is (IDLE, START_READOUT, START_READOUT_WAIT, FEE_BUSY, SEND_EINF_H, SEND_EINF_L, SEND_LENGTH, SEND_SOURCE, SEND_SOURCE_WAIT, SEND_PAYLOAD_H, SEND_PAYLOAD_L, SEND_PAYLOAD_RT_H, SEND_PAYLOAD_RT_L, COMPL_WAIT, COMPL_NOT_BUSY_WAIT, EVT_WAIT);
   signal trb_fsm_i : TRB_FSM_T;
    
 begin
@@ -462,7 +491,23 @@ begin
 
 --   TEST_LINE(7 downto 0) <= cbm_data2send_stop & cbm_data2send_start & cbm_data2send_end & cbm_dlm_rec_va & cbm_dlm_rec_type;
 --   TEST_LINE(15 downto 8) <= phy_stat_debug(7 downto 0);
+  
+   PROC_TESTLINE: process is
+      variable pattern_v : std_logic_vector(15 downto 0) := x"0001";
+   begin
+      wait until rising_edge(rclk_125_i);
       
+      pattern_v := pattern_v(14 downto 0) & pattern_v(15);
+      
+      if send_enabled_i = '0' then
+         TEST_LINE <= pattern_v;
+      else
+         pattern_v := x"0001";
+         TEST_LINE(15 downto 11) <= cbm_data2send_stop & cbm_data2send_start & cbm_data2send_end  & cbm_data2send(15 downto 14);
+         TEST_LINE(10 downto 0) <= cbm_data2send(10 downto 0);
+      end if;
+   end process;
+  
    
    SFP_RATESEL   <= (others => '0');
    
@@ -647,139 +692,195 @@ begin
       CBMNET_LINK_ACTIVE_IN => cbm_link_active, -- in std_logic;
 
       CBMNET_DATA2SEND_STOP_IN   => cbm_data2send_stop(0), -- in std_logic;
-      CBMNET_DATA2SEND_START_OUT => cbm_data2send_start(0), -- out std_logic;
-      CBMNET_DATA2SEND_END_OUT   => cbm_data2send_end(0), -- out std_logic;
-      CBMNET_DATA2SEND_DATA_OUT  => cbm_data2send -- out std_logic_vector(15 downto 0)   
+      CBMNET_DATA2SEND_START_OUT => cbm_data2send_start1(0), -- out std_logic;
+      CBMNET_DATA2SEND_END_OUT   => cbm_data2send_end1(0), -- out std_logic;
+      CBMNET_DATA2SEND_DATA_OUT  => cbm_data2send1 -- out std_logic_vector(15 downto 0)   
    );
    
    gbe_fee_read <= '1';
    gbe_cts_status_bits <= x"beafc0de";
    
    process is
+      variable wait_cnt_v : integer range 0 to 15 := 0;
    begin
       wait until rising_edge(clk_100_i);
       
       hub_cts_start_readout <= '1';
-      hub_fee_busy <= '1';
-      hub_fee_dataready <= '0';
+      HUB_FEE_BUSY <= '1';
+      HUB_FEE_DATAREADY <= '0';
       
-      if reset_i = '1' then
+      if reset_i='1' then
          trb_fsm_i <= IDLE;
-         event_id <= 0;
-         
-         hub_cts_start_readout <= '0';
-         hub_fee_busy <= '0';
-         hub_fee_dataready <= '0';
-         
       else
          case(trb_fsm_i) is
             when IDLE =>
                hub_cts_start_readout <= '0';
-               hub_fee_busy <= '0';
+               HUB_FEE_BUSY <= '0';
                if send_enabled_i = '1' then
                   trb_fsm_i <= START_READOUT;
                end if;
                
+               if send_length_cnt_i < send_length_min_i then
+                  send_length_cnt_i <= send_length_min_i;
+               else
+                  send_length_cnt_i <= send_length_cnt_i + 1;
+               end if;
+               
             when START_READOUT => 
-               trb_fsm_i <= START_READOUT_WAIT1;
-               hub_fee_busy <= '0';
+               if send_length_cnt_i < send_length_min_i or send_length_cnt_i > send_length_max_i then
+                  send_length_cnt_i <= send_length_min_i;
+               end if;
+
+               trb_fsm_i <= START_READOUT_WAIT;
+               wait_cnt_v := 10;
+               HUB_FEE_BUSY <= '0';
                event_id <= event_id + 1;
+               send_real_time_buf_i <= send_real_time_i;
+               
+            when START_READOUT_WAIT => 
+               if wait_cnt_v = 0 then
+                  trb_fsm_i <= FEE_BUSY;
+                  wait_cnt_v := 5;
+               else
+                  wait_cnt_v := wait_cnt_v - 1;
+               end if;
                
-            when START_READOUT_WAIT1 => 
-               trb_fsm_i <= START_READOUT_WAIT2;
-               hub_fee_busy <= '0';
-            when START_READOUT_WAIT2 => 
-               trb_fsm_i <= START_READOUT_WAIT3;
-               hub_fee_busy <= '0';
-            when START_READOUT_WAIT3 => 
-               trb_fsm_i <= FEE_BUSY;
-               hub_fee_busy <= '0';
+               HUB_FEE_BUSY <= '0';
             
             when FEE_BUSY =>
-               trb_fsm_i <= FEE_BUSY_WAIT1;
-            when FEE_BUSY_WAIT1 =>
-               trb_fsm_i <= FEE_BUSY_WAIT2;
-            when FEE_BUSY_WAIT2 =>
-               trb_fsm_i <= FEE_BUSY_WAIT3;
-            when FEE_BUSY_WAIT3 =>
-               trb_fsm_i <= SEND_EINF_H;
+               if wait_cnt_v = 0 then
+                  trb_fsm_i <= SEND_EINF_H;
+               else
+                  wait_cnt_v := wait_cnt_v - 1;
+               end if;
+               
+               HUB_FEE_BUSY <= '1';
                
             when SEND_EINF_H =>
-               hub_fee_data <= x"8765";
-               hub_fee_dataready <= '1';
+               HUB_FEE_DATA <= x"0e" & STD_LOGIC_VECTOR(event_id(23 downto 16));
+               HUB_FEE_DATAREADY <= '1';
                trb_fsm_i <= SEND_EINF_L;
             when SEND_EINF_L =>
-               hub_fee_data <= event_id;
-               hub_fee_dataready <= '1';
+               HUB_FEE_DATA <= std_logic_vector(event_id(15 downto 0));
+               HUB_FEE_DATAREADY <= '1';
                trb_fsm_i <= SEND_LENGTH;
                
             when SEND_LENGTH =>
-               hub_fee_data <= send_length_i;
-               send_counter_i <= send_length_i;
-               hub_fee_dataready <= '1';
+               HUB_FEE_DATA <= std_logic_vector(send_length_cnt_i);
+               send_counter_i <= send_length_cnt_i;
+               HUB_FEE_DATAREADY <= '1';
                trb_fsm_i <= SEND_SOURCE;
             when SEND_SOURCE =>
-               hub_fee_data <= x"affe";
-               hub_fee_dataready <= '1';
+               HUB_FEE_DATA <= x"affe";
+               HUB_FEE_DATAREADY <= '1';
                trb_fsm_i <= SEND_SOURCE_WAIT;
 
             when SEND_SOURCE_WAIT =>
                trb_fsm_i <= SEND_PAYLOAD_H;
+
+            when SEND_PAYLOAD_RT_H =>
+               HUB_FEE_DATA <= std_logic_vector(send_real_time_buf_i(31 downto 16));
+               HUB_FEE_DATAREADY <= '1';
+               trb_fsm_i <= SEND_PAYLOAD_RT_L;
+               
+            when SEND_PAYLOAD_RT_L =>
+               HUB_FEE_DATA <= std_logic_vector(send_real_time_buf_i(15 downto 0));
+               HUB_FEE_DATAREADY <= '1';
+               trb_fsm_i <= SEND_PAYLOAD_H;
+               send_counter_i <= send_counter_i - 1;
+               
+               if send_counter_i = 1 then
+                  trb_fsm_i <= COMPL_WAIT;
+                  wait_cnt_v := 5;
+               end if;
                
             when SEND_PAYLOAD_H =>
-               hub_fee_data <= x"bb" & std_logic_vector(event_id(7 downto 0));
-               hub_fee_dataready <= '1';
+               HUB_FEE_DATA <= x"bb" & std_logic_vector(event_id(7 downto 0));
+               HUB_FEE_DATAREADY <= '1';
                trb_fsm_i <= SEND_PAYLOAD_L;
                
             when SEND_PAYLOAD_L =>
-               hub_fee_data <= x"c" & std_logic_vector(send_counter_i(11 downto 0));
-               hub_fee_dataready <= '1';
+               HUB_FEE_DATA <= x"c" & std_logic_vector(send_counter_i(11 downto 0));
+               HUB_FEE_DATAREADY <= '1';
                trb_fsm_i <= SEND_PAYLOAD_H;
                send_counter_i <= send_counter_i - 1;
                
                if send_counter_i = 1 then
-                  trb_fsm_i <= COMPL_WAIT1;
+                  trb_fsm_i <= COMPL_WAIT;
+                  wait_cnt_v := 5;
+               end if;
+               
+            when COMPL_WAIT =>
+               if wait_cnt_v = 0 then
+                  wait_cnt_v := 5;
+                  trb_fsm_i <= COMPL_NOT_BUSY_WAIT;
+               else
+                  wait_cnt_v := wait_cnt_v - 1;
                end if;
                
-            when COMPL_WAIT1 => trb_fsm_i <= COMPL_WAIT2;
-            when COMPL_WAIT2 => trb_fsm_i <= COMPL_WAIT3;
-            when COMPL_WAIT3 => trb_fsm_i <= COMPL_WAIT4;
-            when COMPL_WAIT4 => trb_fsm_i <= COMPL_NOT_BUSY_WAIT1;
+               HUB_FEE_BUSY <= '1';
+
             
-            when COMPL_NOT_BUSY_WAIT1 => trb_fsm_i <= COMPL_NOT_BUSY_WAIT2; hub_fee_busy <= '0';
-            when COMPL_NOT_BUSY_WAIT2 => trb_fsm_i <= COMPL_NOT_BUSY_WAIT3; hub_fee_busy <= '0';
-            when COMPL_NOT_BUSY_WAIT3 => trb_fsm_i <= COMPL_NOT_BUSY_WAIT4; hub_fee_busy <= '0';
-            when COMPL_NOT_BUSY_WAIT4 => 
-               trb_fsm_i <= EVT_WAIT;
-               hub_fee_busy <= '0';
+            when COMPL_NOT_BUSY_WAIT => 
                hub_cts_start_readout <= '0';
-               send_wait_counter_i <= 0;
+               if wait_cnt_v = 0 then
+                  trb_fsm_i <= EVT_WAIT;
+                  wait_cnt_v := 5;
+               else
+                  wait_cnt_v := wait_cnt_v - 1;
+               end if;
+               
+               HUB_FEE_BUSY <= '0';
+               event_gap_cnt_i <= (others => '0');
                
                
             when EVT_WAIT =>
                hub_cts_start_readout <= '0';
-               hub_fee_busy <= '0';
-
-               send_wait_counter_i <= send_wait_counter_i + 1;
-               if send_wait_counter_i >= UNSIGNED(send_wait_threshold_i) then
+               HUB_FEE_BUSY <= '0';
+               
+               event_gap_cnt_i <= event_gap_cnt_i + 1;
+               
+               if event_gap_cnt_i >= UNSIGNED(event_gap_i) then
                   trb_fsm_i <= IDLE;
                end if;
                
          end case;
-      
       end if;
+   end process;
    
+   proc_real_time: process is
+   begin
+      wait until rising_edge(clk_100_i);
+      
+      if reset_i='1' then
+         send_real_time_i <= (others => '0');
+      else
+         send_real_time_i <= send_real_time_i + 1;
+      end if;
    end process;
+  
+   proc_real_time125: process is
+   begin
+      wait until rising_edge(rclk_125_i);
       
-   
-   
+      if rreset_i='1' then
+         send_real_time125_i <= (others => '0');
+      else
+         send_real_time125_i <= send_real_time125_i +1;
+      end if;
+   end process;
+   send_real_time125_xfer_i <= send_real_time125_i when rising_edge(clk_100_i);
+  
+   cbm_data2send <= cbm_data2send1; -- when tp_mux_i = '0' else cbm_data2send2;
+   cbm_data2send_start <= cbm_data2send_start1; -- when tp_mux_i = '0' else cbm_data2send_start2;
+   cbm_data2send_end <= cbm_data2send_end1; -- when tp_mux_i = '0' else cbm_data2send_end2;   
    
 --    proc_data_send: process begin
 --       wait until rising_edge(rclk_125_i);
 --       
---       cbm_data2send <= (others => '0');
---       cbm_data2send_start <= "0";
---       cbm_data2send_end <= "0";
+--       cbm_data2send2 <= (others => '0');
+--       cbm_data2send_start2 <= "0";
+--       cbm_data2send_end2 <= "0";
 -- 
 --       if reset_i = '1' or send_enabled_i = '0' then
 --          send_fsm_i <= start;
@@ -791,7 +892,7 @@ begin
 --                if cbm_link_active='1' and cbm_data2send_stop = "0" then
 --                   send_fsm_i <= send_header;
 --                   send_num_pack_counter_i <= send_num_pack_counter_i + 1;
---                   send_length_i(4 downto 0) <= unsigned("0" & send_num_pack_counter_i(3 downto 0)) + 1;
+--                   send_length_i2(4 downto 0) <= unsigned("0" & send_num_pack_counter_i(3 downto 0)) + 1;
 --                   
 --                   if send_burst_counter_i = to_unsigned(0, send_burst_counter_i'length) then
 --                      send_burst_counter_i <= send_burst_threshold_i;
@@ -801,37 +902,37 @@ begin
 --                end if;
 --             
 --             when send_header =>
---                cbm_data2send <= x"f123";
---                cbm_data2send_start <= "1";
+--                cbm_data2send2 <= x"f123";
+--                cbm_data2send_start2 <= "1";
 --                send_fsm_i <= send_pack_num;
 --                
 --             when send_pack_num =>
---                cbm_data2send <= send_num_pack_counter_i;
+--                cbm_data2send2 <= send_num_pack_counter_i;
 --                send_fsm_i <= send_length;
 --             
 --             when send_length =>
---                cbm_data2send(send_length_i'range) <= send_length_i;
+--                cbm_data2send2(send_length_i2'range) <= send_length_i2;
 --                send_fsm_i <= send_data;
 --                
 --             when send_data =>
---                send_length_i <= send_length_i - 1;
---                cbm_data2send(15 downto 8) <= "0" & std_logic_vector(send_length_i(2 downto 0)) & std_logic_vector(send_length_i(3 downto 0));
---                cbm_data2send(send_length_i'high + 0 downto 0) <= send_length_i;
+--                send_length_i2 <= send_length_i2 - 1;
+--                cbm_data2send2(15 downto 8) <= "0" & std_logic_vector(send_length_i2(2 downto 0)) & std_logic_vector(send_length_i2(3 downto 0));
+--                cbm_data2send2(send_length_i2'high + 0 downto 0) <= send_length_i2;
 --                
---                if send_length_i = to_unsigned(1, send_length_i'length) then
+--                if send_length_i2 = to_unsigned(1, send_length_i2'length) then
 --                   send_fsm_i <= send_footer;
 --                end if;
 --                
 --             when send_footer =>
---                cbm_data2send <= x"f321";
---                cbm_data2send_end <= "1";
+--                cbm_data2send2 <= x"f321";
+--                cbm_data2send_end2 <= "1";
 --                
---                send_wait_counter_i <= (others => '0');
+--                send_wait_counter_i2 <= (others => '0');
 --                send_fsm_i <= after_send_wait;
 -- 
 --             when after_send_wait =>
---                send_wait_counter_i <= std_logic_vector( unsigned(send_wait_counter_i) + 1 );
---                if send_wait_counter_i(4 downto 0) >= send_wait_threshold_i or send_burst_counter_i /= to_unsigned(0, send_burst_counter_i'length) then
+--                send_wait_counter_i2 <= std_logic_vector( unsigned(send_wait_counter_i2) + 1 );
+--                if send_wait_counter_i2(4 downto 0) >= send_wait_threshold_i or send_burst_counter_i /= to_unsigned(0, send_burst_counter_i'length) then
 --                   send_fsm_i <= start;
 --                end if;
 --                
@@ -883,6 +984,27 @@ begin
          when 16#5# => debug_data_out <= phy_ctrl_debug(63 downto 32);
          when 16#6# => debug_data_out <= STD_LOGIC_VECTOR(TO_UNSIGNED(CBM_FEE_MODE, 32));
          
+         when 16#0f# => debug_data_out(15 downto 0) <= send_length_i1;
+         when 16#10# => debug_data_out <= event_gap_i;
+         when 16#11# => debug_data_out <= event_id;
+         
+         when 16#12# => debug_data_out <= STD_LOGIC_VECTOR(dlm_counter_i);
+         when 16#13# => debug_data_out <= STD_LOGIC_VECTOR(dlm_glob_counter_i);
+         when 16#14# =>
+			debug_data_out(21 downto 20) <= cbm_debug_overrides_i;
+            debug_data_out(19 downto 16) <= tp_mux_i & send_enabled_i & cbm_data2send_stop & cbm_link_active;
+            debug_data_out(15 downto 0) <= STD_LOGIC_VECTOR(send_num_pack_counter_i);
+            
+            
+         when 16#15# => debug_data_out(15 downto 0) <= cbm_crc_error_cntr_0;
+         when 16#16# => debug_data_out <= cbm_retrans_error_cntr_0 & cbm_retrans_cntr_0;
+         when 16#17# => debug_data_out(15 downto 0) <= cbm_crc_error_cntr_1;
+         when 16#18# => debug_data_out <= cbm_retrans_error_cntr_1 & cbm_retrans_cntr_1;
+         when 16#19# => debug_data_out(15 downto 0) <= cbm_crc_error_cntr_2;
+         when 16#1a# => debug_data_out <= cbm_retrans_error_cntr_2 & cbm_retrans_cntr_2;
+         when 16#1b# => debug_data_out(15 downto 0) <= cbm_crc_error_cntr_3;
+         when 16#1c# => debug_data_out <= cbm_retrans_error_cntr_3 & cbm_retrans_cntr_3;
+
          when 16#20# => debug_data_out <= phy_debug_i_buf(31+32*0 downto 32*0);
          when 16#21# => debug_data_out <= phy_debug_i_buf(31+32*1 downto 32*1);
          when 16#22# => debug_data_out <= phy_debug_i_buf(31+32*2 downto 32*2);
@@ -900,27 +1022,12 @@ begin
          when 16#2e# => debug_data_out <= phy_debug_i_buf(31+32*14 downto 32*14);
          when 16#2f# => debug_data_out <= phy_debug_i_buf(31+32*15 downto 32*15);  
          
-         
-         when 16#0f# => debug_data_out(15 downto 0) <= send_length_i;
-         when 16#10# => debug_data_out <= send_wait_threshold_i;
-         when 16#11# => null;---debug_data_out(20 downto 0) <= "000" & cbm_data_from_link;
-         
-         when 16#12# => debug_data_out <= STD_LOGIC_VECTOR(dlm_counter_i);
-         when 16#13# => debug_data_out <= STD_LOGIC_VECTOR(dlm_glob_counter_i);
-         when 16#14# =>
-			debug_data_out(21 downto 20) <= cbm_debug_overrides_i;
-            debug_data_out(19 downto 16) <= "0" & send_enabled_i & cbm_data2send_stop & cbm_link_active;
-            debug_data_out(15 downto 0) <= STD_LOGIC_VECTOR(send_num_pack_counter_i);
-            
-            
-         when 16#15# => debug_data_out(15 downto 0) <= cbm_crc_error_cntr_0;
-         when 16#16# => debug_data_out <= cbm_retrans_error_cntr_0 & cbm_retrans_cntr_0;
-         when 16#17# => debug_data_out(15 downto 0) <= cbm_crc_error_cntr_1;
-         when 16#18# => debug_data_out <= cbm_retrans_error_cntr_1 & cbm_retrans_cntr_1;
-         when 16#19# => debug_data_out(15 downto 0) <= cbm_crc_error_cntr_2;
-         when 16#1a# => debug_data_out <= cbm_retrans_error_cntr_2 & cbm_retrans_cntr_2;
-         when 16#1b# => debug_data_out(15 downto 0) <= cbm_crc_error_cntr_3;
-         when 16#1c# => debug_data_out <= cbm_retrans_error_cntr_3 & cbm_retrans_cntr_3;
+         when 16#30# => debug_data_out <= x"0000" & STD_LOGIC_VECTOR( send_length_min_i );
+         when 16#31# => debug_data_out <= x"0000" & STD_LOGIC_VECTOR(send_length_max_i );
+         when 16#32# => debug_data_out <= x"0000" & STD_LOGIC_VECTOR(send_length_step_i );
+         when 16#33# => debug_data_out <= send_real_time_i;
+                        send_real_time125_buf_i <= send_real_time125_xfer_i;
+         when 16#34# => debug_data_out <= send_real_time125_buf_i;
          
          when others => debug_ack <= '0';
       end case;
@@ -930,21 +1037,35 @@ begin
             when 16#01# => phy_ctrl_op <= debug_data_in(15 downto 0);
             when 16#04# => phy_ctrl_debug(31 downto  0) <= debug_data_in;
             when 16#05# => phy_ctrl_debug(63 downto 32) <= debug_data_in;
-            when 16#0f# => --send_burst_threshold_i <= debug_data_in; 
-                  send_length_i <= debug_data_in(15 downto 0);
-            when 16#10# => send_wait_threshold_i <= debug_data_in;
+            when 16#0f# => 
+                  send_burst_threshold_i <= debug_data_in; 
+                  send_length_i1 <= debug_data_in(15 downto 0);
+            when 16#10# => event_gap_i <= debug_data_in;
             when 16#14# => 
 				send_enabled_i <= debug_data_in(18);
+				tp_mux_i <= debug_data_in(19);
 				--cbm_debug_overrides_i <= debug_data_in(21 downto 20);
             
+            when 16#30# => 
+               if UNSIGNED(debug_data_in(15 downto 0)) /= 0 then
+                  send_length_min_i <= UNSIGNED(debug_data_in(15 downto 0));
+               end if;
+            when 16#31# =>
+               if UNSIGNED(debug_data_in(15 downto 0)) < 1019 then
+                  send_length_max_i <= UNSIGNED(debug_data_in(15 downto 0));
+               end if;
+               
+            when 16#32# => 
+               send_length_step_i <= UNSIGNED(debug_data_in(15 downto 0));
 
             when others => debug_ack <= '0';
          end case;
       end if;
       
-      if cbm_res_n = '0' then
-         send_burst_threshold_i<= x"00000010";
-         send_wait_threshold_i <= x"00010000";
+      if reset_i='1' then
+         send_length_step_i <= TO_UNSIGNED(  1, 16);
+         send_length_min_i  <= TO_UNSIGNED(  1, 16);
+         send_length_max_i  <= TO_UNSIGNED(200, 16);
       end if;
    end process;
    
diff --git a/cts/compile_new_central_frankfurt.pl b/cts/compile_new_central_frankfurt.pl
new file mode 100755
index 0000000..72e1c7a
--- /dev/null
+++ b/cts/compile_new_central_frankfurt.pl
@@ -0,0 +1,150 @@
+#!/usr/bin/perl
+use Data::Dumper;
+use warnings;
+use strict;
+use Term::ANSIColor;
+use File::stat;
+use POSIX;
+
+
+###################################################################################
+#Settings for this project
+my $TOPNAME                      = "trb3_central";  #Name of top-level entity
+my $BasePath                     = "../base/";     #path to "base" directory
+my $CbmNetPath                   = "../../cbmnet";
+my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de";
+my $lm_license_file_for_par      = "1702\@hadeb05.gsi.de";
+
+my $lattice_path                 = '/d/jspc29/lattice/diamond/3.2_x64';
+my $synplify_path                = '/d/jspc29/lattice/synplify/I-2013.09-SP1/';
+###################################################################################
+
+system("./compile_constraints.pl");
+
+symlink($CbmNetPath, '../cbmnet/cbmnet') unless (-e '../cbmnet/cbmnet');
+
+use FileHandle;
+
+$ENV{'SYNPLIFY'}=$synplify_path;
+$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1;
+$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify;
+
+
+my $FAMILYNAME="LatticeECP3";
+my $DEVICENAME="LFE3-150EA";
+my $PACKAGE="FPBGA1156";
+my $SPEEDGRADE="8";
+
+#create full lpf file
+
+#set -e
+#set -o errexit
+
+#generate timestamp
+my $t=time;
+my $fh = new FileHandle(">version.vhd");
+die "could not open file" if (! defined $fh);
+print $fh <<EOF;
+
+--## attention, automatically generated. Don't change by hand.
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+use ieee.numeric_std.all;
+
+package version is
+
+    constant VERSION_NUMBER_TIME  : integer   := $t;
+    
+end package version;
+EOF
+$fh->close;
+
+system("env| grep LM_");
+my $r = "";
+
+my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj";
+$r=execute($c, "do_not_exit" );
+
+chdir "workdir";
+
+$fh = new FileHandle("<$TOPNAME".".srr");
+my @a = <$fh>;
+$fh -> close;
+
+
+
+foreach (@a)
+{
+    if(/\@E:/)
+    {
+	print "\n";
+	$c="cat $TOPNAME.srr | grep \"\@E\"";
+	system($c);
+        print "\n\n";
+	exit 129;
+    }
+}
+
+
+$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par;
+
+$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd  -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate   -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|;
+execute($c);
+
+$c=qq'$lattice_path/ispfpga/bin/lin/ngdbuild  -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd" | grep -v -e "^WARNING.*has no load"';
+execute($c);
+
+my $tpmap = $TOPNAME . "_map" ;
+
+$c=qq|$lattice_path/ispfpga/bin/lin/map  -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -o "$tpmap.ncd"  -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|;
+execute($c);
+
+system("rm $TOPNAME.ncd");
+
+$c=qq|mpartrce -p "../$TOPNAME.p2t" -f "../$TOPNAME.p3t" -tf "$TOPNAME.pt" "|.$TOPNAME.qq|_map.ncd" "$TOPNAME.ncd"|;
+execute($c);
+
+# IOR IO Timing Report
+$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+# TWR Timing Report
+$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold"  "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/bitgen  -w "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+chdir "..";
+
+
+sub execute {
+    my ($c, $op) = @_;
+    #print "option: $op \n";
+    $op = "" if(!$op);
+    print color 'blue bold';
+    print "\n\ncommand to execute: $c \n";
+    print color 'reset';
+    $r=system($c);
+    if($r) {
+  print "$!";
+  if($op ne "do_not_exit") {
+      wait;
+  }
+    }
+
+    return $r;
+
+}
+