From: hadeshyp Date: Thu, 17 Jan 2008 14:56:17 +0000 (+0000) Subject: added startup logic to med_tlk, Jan X-Git-Tag: oldGBE~620 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=9983b9fe1c50b2fb24c33a188bc4f9374702c32c;p=trbnet.git added startup logic to med_tlk, Jan --- diff --git a/trb_net16_med_tlk.vhd b/trb_net16_med_tlk.vhd index e3a6b14..e45bb5c 100644 --- a/trb_net16_med_tlk.vhd +++ b/trb_net16_med_tlk.vhd @@ -41,7 +41,10 @@ end trb_net16_med_tlk; architecture trb_net16_med_tlk_arch of trb_net16_med_tlk is - component trb_net_fifo_16bit_bram_dualport + component trb_net_fifo_16bit_bram_dualport + generic( + USE_STATUS_FLAGS : integer range 0 to 1 := c_YES + ); port ( read_clock_in: IN std_logic; write_clock_in: IN std_logic; @@ -77,11 +80,10 @@ architecture trb_net16_med_tlk_arch of trb_net16_med_tlk is signal buf_MED_PACKET_NUM_OUT : std_logic_vector(1 downto 0); signal buf_MED_READ_OUT : std_logic; signal buf_MED_DATAREADY_OUT : std_logic; - signal rx_locked : std_logic; + signal rx_allow : std_logic; signal tx_allow : std_logic; - signal rx_lock_counter : std_logic_vector(20 downto 0); signal internal_reset : std_logic; - signal reset_counter : std_logic_vector(16 downto 0); + signal reset_packet_num : std_logic; signal reg_RXD : std_logic_vector(15 downto 0); @@ -94,17 +96,16 @@ architecture trb_net16_med_tlk_arch of trb_net16_med_tlk is signal CLK_Out, CLK_FB_Out, FB_CLK : std_logic; signal buf_STAT : std_logic_vector(33 downto 32); + type tlk_state_t is (RESETTING, WAIT_FOR_RX_LOCK, WAIT_FOR_RX_ALLOW, WAIT_FOR_TX_ALLOW, WORKING); + signal current_state, next_state : tlk_state_t; + signal next_tx_allow, next_rx_allow : std_logic; + signal counter, next_counter : std_logic_vector(22 downto 0); + signal next_internal_reset : std_logic; + signal buf_MED_ERROR_OUT, next_MED_ERROR_OUT : std_logic_vector(2 downto 0); + begin --- STAT(3 downto 0) <= fifo_status_a; --- STAT(5 downto 4) <= fifo_empty_a & fifo_full_a; --- STAT(7 downto 6) <= (others => '0'); --- STAT(11 downto 8) <= fifo_status_m; --- STAT(13 downto 12) <= fifo_empty_m & fifo_full_m; --- STAT(31 downto 14) <= (others => '0'); - - TLK_ENABLE <= not RESET; TLK_LCKREFN <= '1'; TLK_PRBSEN <= '0'; @@ -119,6 +120,9 @@ begin ------------- FIFO_OPT_TO_MED: trb_net_fifo_16bit_bram_dualport + generic map( + USE_STATUS_FLAGS => c_NO + ) port map( read_clock_in => CLK, write_clock_in => TLK_RX_CLK, @@ -132,16 +136,12 @@ begin fifostatus_out => fifo_status_a ); - fifo_wr_en_a <= reg_RX_DV and not reg_RX_ER and rx_locked; - fifo_din_a <= rx_locked & reg_RX_ER & reg_RXD; + fifo_wr_en_a <= reg_RX_DV and not reg_RX_ER and rx_allow; + fifo_din_a <= rx_allow & reg_RX_ER & reg_RXD; fifo_rd_en_a <= not fifo_empty_a; fifo_reset <= internal_reset; - --MED_DATA_OUT <= fifo_dout_a(15 downto 0); buf_MED_DATAREADY_OUT <= last_fifo_rd_en_a and not fifo_dout_a(16) and fifo_dout_a(17); - MED_ERROR_OUT <= ERROR_OK when rx_locked = '1' else ERROR_NC; - --MED_PACKET_NUM_OUT <= buf_MED_PACKET_NUM_OUT; - --MED_DATAREADY_OUT <= buf_MED_DATAREADY_OUT; - + MED_ERROR_OUT <= buf_MED_ERROR_OUT; process(CLK) begin @@ -159,7 +159,7 @@ begin end process; STAT(0) <= internal_reset; - STAT(1) <= rx_locked; + STAT(1) <= rx_allow; STAT(2) <= tx_allow; STAT(3) <= fifo_wr_en_a; STAT(4) <= fifo_rd_en_a; @@ -171,11 +171,10 @@ begin STAT(14) <= reg_RX_DV; STAT(15) <= reg_RX_ER; STAT(31 downto 16) <= reg_RXD; - - STAT(32) <= buf_STAT(32); - STAT(33) <= buf_STAT(33); - STAT(39 downto 36) <= fifo_status_a; - STAT(43 downto 40) <= fifo_status_m; + STAT(32) <= buf_STAT(32); + STAT(33) <= buf_STAT(33); + STAT(39 downto 36) <= fifo_status_a; + STAT(43 downto 40) <= fifo_status_m; process(CLK) @@ -262,6 +261,9 @@ U1_BUFG: BUFG port map (I => CLK_FB_Out, O => FB_CLK); FIFO_MED_TO_OPT: trb_net_fifo_16bit_bram_dualport + generic map( + USE_STATUS_FLAGS => c_NO + ) port map( read_clock_in => TLK_CLK_neg, write_clock_in => CLK, @@ -278,8 +280,7 @@ U1_BUFG: BUFG port map (I => CLK_FB_Out, O => FB_CLK); fifo_rd_en_m <= tx_allow and not fifo_empty_m; --fifo_wr_en_m <= MED_DATAREADY_IN and buf_MED_READ_OUT; --fifo_din_m <= "00" & MED_DATA_IN; - TLK_TXD <= reg_TXD; - TLK_TX_EN <= reg_TX_EN; + TLK_TX_ER <= '0'; process(CLK) @@ -320,57 +321,90 @@ U1_BUFG: BUFG port map (I => CLK_FB_Out, O => FB_CLK); end if; end process; +------------- +--Medium states +------------- ---count time the receiver is locked - RESET_FIFO_COUNTER_PROC: process (TLK_RX_CLK) - begin - if rising_edge(TLK_RX_CLK) then - if internal_reset = '1' or TLK_RX_ER = '1' then - rx_lock_counter <= (others => '0'); - elsif rx_lock_counter(20) = '0' then --20 - rx_lock_counter <= rx_lock_counter + 1; - end if; - end if; - end process RESET_FIFO_COUNTER_PROC; - - ---wait 2.5us to see if receiver is really locked - process (TLK_RX_CLK) + medium_states : process(current_state, tx_allow, rx_allow, internal_reset, counter, + TLK_RX_ER, TLK_RX_DV, TLK_RXD, buf_MED_ERROR_OUT) begin - if rising_edge(TLK_RX_CLK) then - if internal_reset = '1' or TLK_RX_ER = '1' then - rx_locked <= '0'; - elsif rx_lock_counter(8) = '1' then --8 - rx_locked <= '1'; - end if; - end if; + next_state <= current_state; + next_tx_allow <= tx_allow; + next_rx_allow <= rx_allow; + next_internal_reset <= internal_reset; + next_counter <= counter + 1; + next_MED_ERROR_OUT <= buf_MED_ERROR_OUT; + case current_state is + when RESETTING => + next_MED_ERROR_OUT <= ERROR_NC; + next_internal_reset <= '1'; + if counter(16) = '1' then + next_counter <= (others => '0'); + next_state <= WAIT_FOR_RX_LOCK; + next_internal_reset <= '0'; + end if; + when WAIT_FOR_RX_LOCK => + if TLK_RX_ER = '0' then + next_counter <= (others => '0'); + next_state <= WAIT_FOR_RX_ALLOW; + end if; + when WAIT_FOR_RX_ALLOW => + next_MED_ERROR_OUT <= ERROR_WAIT; + if counter(22) = '1' then + next_rx_allow <= '1'; + next_counter <= (others => '0'); + next_state <= WAIT_FOR_TX_ALLOW; + end if; + if TLK_RX_ER = '1' then + next_counter <= (others => '0'); + end if; + when WAIT_FOR_TX_ALLOW => + next_MED_ERROR_OUT <= ERROR_WAIT; + if counter(20) = '1' then + next_tx_allow <= '1'; + next_state <= WORKING; + end if; + when WORKING => + next_MED_ERROR_OUT <= ERROR_OK; + if TLK_RX_ER = '1' then + next_state <= WAIT_FOR_RX_LOCK; + next_MED_ERROR_OUT <= ERROR_WAIT; + next_rx_allow <= '0'; + next_tx_allow <= '0'; + next_counter <= (others => '0'); + end if; + end case; end process; ---wait 2800us to enable transmitter after receiver is locked - process (TLK_RX_CLK) + states_reg : process(CLK) begin - if rising_edge(TLK_RX_CLK) then - if internal_reset = '1' or TLK_RX_ER = '1' then + if rising_edge(CLK) then + if internal_reset = '1' then + current_state <= RESETTING; tx_allow <= '0'; - elsif rx_lock_counter(10) = '1' then --10 - tx_allow <= '1'; + rx_allow <= '0'; + else + current_state <= next_state; + tx_allow <= next_tx_allow; + rx_allow <= next_rx_allow; end if; end if; end process; - ---internal reset is hold for approx. 650 us - internal_reset_counter: process (CLK) - begin + states_reg_2 : process(CLK) + begin if rising_edge(CLK) then if RESET = '1' then - reset_counter <= (others => '0'); - elsif reset_counter(16) = '0' then --16 - reset_counter <= reset_counter + 1; + internal_reset <= '1'; + counter <= (others => '0'); + buf_MED_ERROR_OUT <= ERROR_NC; + else + internal_reset <= next_internal_reset; + counter <= next_counter; + buf_MED_ERROR_OUT <= next_MED_ERROR_OUT; end if; end if; - end process internal_reset_counter; + end process; -internal_reset <= not reset_counter(16); --16 end architecture; diff --git a/trb_net_fifo_16bit_bram_dualport.vhd b/trb_net_fifo_16bit_bram_dualport.vhd index e9e14d2..f4205e2 100644 --- a/trb_net_fifo_16bit_bram_dualport.vhd +++ b/trb_net_fifo_16bit_bram_dualport.vhd @@ -6,9 +6,13 @@ use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; library unisim; use UNISIM.VComponents.all; - +library work; +use work.trb_net_std.all; entity trb_net_fifo_16bit_bram_dualport is + generic( + USE_STATUS_FLAGS : integer := c_YES + ); port ( read_clock_in: IN std_logic; write_clock_in: IN std_logic; diff --git a/xilinx/trb_net_fifo_16bit_bram_dualport_arch.vhd b/xilinx/trb_net_fifo_16bit_bram_dualport_arch.vhd index 09703c2..f4a4eb3 100644 --- a/xilinx/trb_net_fifo_16bit_bram_dualport_arch.vhd +++ b/xilinx/trb_net_fifo_16bit_bram_dualport_arch.vhd @@ -36,7 +36,8 @@ use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; library unisim; use UNISIM.VComponents.all; - +library work; +use work.trb_net_std.all; @@ -359,69 +360,74 @@ end PROCESS proc9; -- improving the circuit performance. -- -- -- ---------------------------------------------------------------- - -proc10: PROCESS (read_clock, fifo_gsr) -BEGIN - IF (fifo_gsr = '1') THEN - read_truegray <= "000000000"; - ELSIF (read_clock'EVENT AND read_clock = '1') THEN - read_truegray(8) <= read_addr(8); - read_truegray(7) <= read_addr(8) XOR read_addr(7); - read_truegray(6) <= read_addr(7) XOR read_addr(6); - read_truegray(5) <= read_addr(6) XOR read_addr(5); - read_truegray(4) <= read_addr(5) XOR read_addr(4); - read_truegray(3) <= read_addr(4) XOR read_addr(3); - read_truegray(2) <= read_addr(3) XOR read_addr(2); - read_truegray(1) <= read_addr(2) XOR read_addr(1); - read_truegray(0) <= read_addr(1) XOR read_addr(0); - end IF; -end PROCESS proc10; - -proc11: PROCESS (write_clock, fifo_gsr) -BEGIN - IF (fifo_gsr = '1') THEN - rag_writesync <= "000000000"; - ELSIF (write_clock'EVENT AND write_clock = '1') THEN - rag_writesync <= read_truegray; - end IF; -end PROCESS proc11; - -xorout(0) <= (rag_writesync(8) XOR rag_writesync(7) XOR rag_writesync(6) XOR - rag_writesync(5)); -xorout(1) <= (rag_writesync(4) XOR rag_writesync(3) XOR rag_writesync(2) XOR - rag_writesync(1)); - -ra_writesync(8) <= rag_writesync(8); -ra_writesync(7) <= (rag_writesync(8) XOR rag_writesync(7)); -ra_writesync(6) <= (rag_writesync(8) XOR rag_writesync(7) XOR rag_writesync(6)); -ra_writesync(5) <= xorout(0); -ra_writesync(4) <= (xorout(0) XOR rag_writesync(4)); -ra_writesync(3) <= (xorout(0) XOR rag_writesync(4) XOR rag_writesync(3)); -ra_writesync(2) <= (xorout(0) XOR rag_writesync(4) XOR rag_writesync(3) - XOR rag_writesync(2)); -ra_writesync(1) <= (xorout(0) XOR xorout(1)); -ra_writesync(0) <= (xorout(0) XOR xorout(1) XOR rag_writesync(0)); - -proc12: PROCESS (write_clock, fifo_gsr) -BEGIN - IF (fifo_gsr = '1') THEN - write_addrr <= "000000000"; - ELSIF (write_clock'EVENT AND write_clock = '1') THEN - write_addrr <= write_addr(8 downto 0); - end IF; -end PROCESS proc12; - -proc13: PROCESS (write_clock, fifo_gsr) -BEGIN - IF (fifo_gsr = '1') THEN - fifostatus <= "000000000"; - ELSIF (write_clock'EVENT AND write_clock = '1') THEN - IF (full = '0') THEN - fifostatus <= (write_addrr - ra_writesync); - end IF; - end IF; -end PROCESS proc13; - +gen_status0 : if USE_STATUS_FLAGS = 0 generate + fifostatus <= (others => '0'); +end generate; + +gen_status : if USE_STATUS_FLAGS = 1 generate + + proc10: PROCESS (read_clock, fifo_gsr) + BEGIN + IF (fifo_gsr = '1') THEN + read_truegray <= "000000000"; + ELSIF (read_clock'EVENT AND read_clock = '1') THEN + read_truegray(8) <= read_addr(8); + read_truegray(7) <= read_addr(8) XOR read_addr(7); + read_truegray(6) <= read_addr(7) XOR read_addr(6); + read_truegray(5) <= read_addr(6) XOR read_addr(5); + read_truegray(4) <= read_addr(5) XOR read_addr(4); + read_truegray(3) <= read_addr(4) XOR read_addr(3); + read_truegray(2) <= read_addr(3) XOR read_addr(2); + read_truegray(1) <= read_addr(2) XOR read_addr(1); + read_truegray(0) <= read_addr(1) XOR read_addr(0); + end IF; + end PROCESS proc10; + + proc11: PROCESS (write_clock, fifo_gsr) + BEGIN + IF (fifo_gsr = '1') THEN + rag_writesync <= "000000000"; + ELSIF (write_clock'EVENT AND write_clock = '1') THEN + rag_writesync <= read_truegray; + end IF; + end PROCESS proc11; + + xorout(0) <= (rag_writesync(8) XOR rag_writesync(7) XOR rag_writesync(6) XOR + rag_writesync(5)); + xorout(1) <= (rag_writesync(4) XOR rag_writesync(3) XOR rag_writesync(2) XOR + rag_writesync(1)); + + ra_writesync(8) <= rag_writesync(8); + ra_writesync(7) <= (rag_writesync(8) XOR rag_writesync(7)); + ra_writesync(6) <= (rag_writesync(8) XOR rag_writesync(7) XOR rag_writesync(6)); + ra_writesync(5) <= xorout(0); + ra_writesync(4) <= (xorout(0) XOR rag_writesync(4)); + ra_writesync(3) <= (xorout(0) XOR rag_writesync(4) XOR rag_writesync(3)); + ra_writesync(2) <= (xorout(0) XOR rag_writesync(4) XOR rag_writesync(3) + XOR rag_writesync(2)); + ra_writesync(1) <= (xorout(0) XOR xorout(1)); + ra_writesync(0) <= (xorout(0) XOR xorout(1) XOR rag_writesync(0)); + + proc12: PROCESS (write_clock, fifo_gsr) + BEGIN + IF (fifo_gsr = '1') THEN + write_addrr <= "000000000"; + ELSIF (write_clock'EVENT AND write_clock = '1') THEN + write_addrr <= write_addr(8 downto 0); + end IF; + end PROCESS proc12; + + proc13: PROCESS (write_clock, fifo_gsr) + BEGIN + IF (fifo_gsr = '1') THEN + fifostatus <= "000000000"; + ELSIF (write_clock'EVENT AND write_clock = '1') THEN + IF (full = '0') THEN + fifostatus <= (write_addrr - ra_writesync); + end IF; + end IF; + end PROCESS proc13; +end generate; ---------------------------------------------------------------- -- -- -- The two conditions decoded with special carry logic are --