From: hadeshyp Date: Mon, 8 Jun 2009 11:21:44 +0000 (+0000) Subject: added time registers X-Git-Tag: oldGBE~438 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=99a1f5010d84a1dab3fc340d55f7be2182997767;p=trbnet.git added time registers --- diff --git a/basics/wide_adder_17x16.vhd b/basics/wide_adder_17x16.vhd index 25b8127..0264798 100644 --- a/basics/wide_adder_17x16.vhd +++ b/basics/wide_adder_17x16.vhd @@ -106,8 +106,14 @@ begin end process; -OVERFLOW_OUT <= overflow; -READY_OUT <= ready; -RESULT_OUT <= result; + + PROC_OUTPUTS : process(CLK) + begin + if rising_edge(CLK) then + READY_OUT <= ready; + RESULT_OUT <= result; + OVERFLOW_OUT <= overflow; + end if; + end process; end architecture; \ No newline at end of file diff --git a/media_interfaces/trb_net16_lsm_sfp.vhd b/media_interfaces/trb_net16_lsm_sfp.vhd index 6094af6..e439905 100644 --- a/media_interfaces/trb_net16_lsm_sfp.vhd +++ b/media_interfaces/trb_net16_lsm_sfp.vhd @@ -367,9 +367,9 @@ begin when WTXA => state_bits <= "0110"; link_status_led <= timing_ctr(25); when CVFND => state_bits <= "0111"; - link_status_led <= '1'; + link_status_led <= timing_ctr(25) and timing_ctr(23); when LINK => state_bits <= "1000"; - link_status_led <= '0'; + link_status_led <= '1'; when CVBAD => state_bits <= "1001"; link_status_led <= timing_ctr(25) and timing_ctr(24) and timing_ctr(23); when others => state_bits <= "1111"; diff --git a/trb_net16_api_base.vhd b/trb_net16_api_base.vhd index 38609a0..d73e103 100644 --- a/trb_net16_api_base.vhd +++ b/trb_net16_api_base.vhd @@ -87,6 +87,11 @@ end entity; architecture trb_net16_api_base_arch of trb_net16_api_base is + -- Placer Directives + attribute HGROUP : string; + -- for whole architecture + attribute HGROUP of trb_net16_api_base_arch : architecture is "API_group"; + -- signals for the APL to INT fifo: signal fifo_to_int_data_in : std_logic_vector(c_DATA_WIDTH-1 downto 0); @@ -683,7 +688,7 @@ INT_MASTER_DATAREADY_OUT <= buf_INT_MASTER_DATAREADY_OUT; update_registered_header <= '0'; out_select <= DAT; next_INT_MASTER_DATAREADY_OUT <= '0'; - next_sequence_counter <= sequence_counter; +-- next_sequence_counter <= sequence_counter; fifo_to_int_read <= '0'; master_start <= '0'; master_end <= '0'; @@ -702,28 +707,33 @@ INT_MASTER_DATAREADY_OUT <= buf_INT_MASTER_DATAREADY_OUT; next_state_to_int <= IDLE; end if; end if; + when IDLE => next_fifo_was_not_empty <= '0'; if APL_SEND_IN = '1' then master_start <= '1'; if APL_SHORT_TRANSFER_IN = '1' then - next_state_to_int <= SEND_SHORT; + update_registered_trailer <= '1'; + next_state_to_int <= SEND_TRAILER; --SEND_SHORT; else update_registered_header <= '1'; next_state_to_int <= SEND_HEADER; end if; end if; + when SEND_SHORT => if APL_SEND_IN = '0' then - update_registered_trailer <= '1'; next_state_to_int <= SEND_TRAILER; + update_registered_trailer <= '1'; end if; + when SEND_HEADER => out_select <= HDR; next_INT_MASTER_DATAREADY_OUT <= sbuf_free; if master_counter = c_F3 and sbuf_free = '1' then next_state_to_int <= RUNNING; end if; + when RUNNING => fifo_to_int_read <= not fifo_to_int_empty and sbuf_free and not master_counter(2); next_INT_MASTER_DATAREADY_OUT <= sbuf_free and (fifo_to_int_read_before or (master_counter(2) and not fifo_to_int_empty)); @@ -735,6 +745,7 @@ INT_MASTER_DATAREADY_OUT <= buf_INT_MASTER_DATAREADY_OUT; next_state_to_int <= SHUTDOWN; -- send rest of data / padding end if; end if; + when SHUTDOWN => fifo_to_int_read <= not fifo_to_int_empty and sbuf_free and not master_counter(2); next_INT_MASTER_DATAREADY_OUT <= sbuf_free and @@ -743,54 +754,55 @@ INT_MASTER_DATAREADY_OUT <= buf_INT_MASTER_DATAREADY_OUT; if master_counter = c_F3 and fifo_to_int_empty = '1' and sbuf_free = '1' then next_state_to_int <= SEND_TRAILER; end if; + when SEND_TRAILER => out_select <= TRM; next_INT_MASTER_DATAREADY_OUT <= sbuf_free; if master_counter = c_F3 and sbuf_free = '1' then next_state_to_int <= INACTIVE; - next_sequence_counter <= sequence_counter +1; +-- next_sequence_counter <= sequence_counter +1; master_end <= '1'; end if; end case; end process; - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - if API_TYPE = 0 then - state_to_apl <= sa_IDLE; - state_to_int <= INACTIVE; - else - state_to_apl <= sa_INACTIVE; - state_to_int <= IDLE; - end if; - send_trm_wrong_addr <= '0'; - fifo_was_not_empty <= '0'; - elsif CLK_EN = '1' then - state_to_apl <= next_state_to_apl; - state_to_int <= next_state_to_int; - send_trm_wrong_addr <= next_send_trm_wrong_addr; - fifo_was_not_empty <= next_fifo_was_not_empty; + PROC_FSM_REG : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + if API_TYPE = 0 then + state_to_apl <= sa_IDLE; + state_to_int <= INACTIVE; + else + state_to_apl <= sa_INACTIVE; + state_to_int <= IDLE; end if; + send_trm_wrong_addr <= '0'; + fifo_was_not_empty <= '0'; + elsif CLK_EN = '1' then + state_to_apl <= next_state_to_apl; + state_to_int <= next_state_to_int; + send_trm_wrong_addr <= next_send_trm_wrong_addr; + fifo_was_not_empty <= next_fifo_was_not_empty; end if; - end process; + end if; + end process; PROC_SEQ_CNT : process(CLK) begin if rising_edge(CLK) then if RESET = '1' or CTRL_SEQNR_RESET = '1' then sequence_counter <= (others => '0'); - else - sequence_counter <= next_sequence_counter; + elsif master_end = '1' then + sequence_counter <= sequence_counter + 1; end if; end if; end process; - process(CLK) + PROC_ENDP_REACHED : process(CLK) begin if rising_edge(CLK) then if CLK_EN = '1' then diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd index bb1a1a3..556ebff 100644 --- a/trb_net16_hub_base.vhd +++ b/trb_net16_hub_base.vhd @@ -185,6 +185,7 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is signal resync : std_logic_vector(MII_NUMBER-1 downto 0); signal reset_i : std_logic; + signal reset_i_mux_io : std_logic_vector(MII_NUMBER-1 downto 0); attribute syn_keep : boolean; attribute syn_keep of reset_i : signal is true; @@ -208,6 +209,16 @@ begin end if; end process; + + gen_resync : for i in 0 to MII_NUMBER-1 generate + SYNC_RESET_MUX_IO : process(CLK) + begin + if rising_edge(CLK) then + reset_i_mux_io(i) <= MED_STAT_OP(i*16+14) or RESET; + end if; + end process; + end generate; + --generate media resync gen_resync : for i in 0 to MII_NUMBER-1 generate resync(i) <= MED_STAT_OP(i*16+15); @@ -223,7 +234,7 @@ begin MPLEX: trb_net16_io_multiplexer port map ( CLK => CLK, - RESET => reset_i, + RESET => reset_i_mux_io(i), CLK_EN => CLK_EN, MED_DATAREADY_IN => MED_DATAREADY_IN(i), MED_DATA_IN => MED_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), @@ -272,7 +283,7 @@ MED_DATA_OUT <= buf_MED_DATA_OUT; port map ( -- Misc CLK => CLK , - RESET => reset_i, + RESET => reset_i_mux_io(j), CLK_EN => CLK_EN, -- Media direction port MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2), @@ -320,7 +331,7 @@ MED_DATA_OUT <= buf_MED_DATA_OUT; port map ( -- Misc CLK => CLK , - RESET => reset_i, + RESET => reset_i_mux_io(j), CLK_EN => CLK_EN, -- Media direction port MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2), diff --git a/trb_net16_hub_func.vhd b/trb_net16_hub_func.vhd index 165a400..b25f0ee 100644 --- a/trb_net16_hub_func.vhd +++ b/trb_net16_hub_func.vhd @@ -7,6 +7,7 @@ use work.trb_net_std.all; package trb_net16_hub_func is +--type for hub arrays type hub_iobuf_config_t is array(0 to 63) of integer; --2**(c_MUX_WIDTH-1)*c_MAX_MII_PER_HUB-1 type hub_api_config_t is array(0 to 7) of integer; type hub_api_broadcast_t is array(0 to 7) of std_logic_vector(7 downto 0); @@ -79,6 +80,164 @@ package trb_net16_hub_func is return integer; + component trb_net16_hub_base is + generic ( + --hub control + HUB_CTRL_CHANNELNUM : integer range 0 to 3 := c_SLOW_CTRL_CHANNEL; + HUB_CTRL_DEPTH : integer range 0 to 6 := c_FIFO_BRAM; + HUB_USED_CHANNELS : hub_channel_config_t := (c_YES,c_YES,c_NO,c_YES); + USE_CHECKSUM : hub_channel_config_t := (c_NO,c_YES,c_YES,c_YES); + USE_VENDOR_CORES : integer range 0 to 1 := c_YES; + IBUF_SECURE_MODE : integer range 0 to 1 := c_NO; + INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F004"; + INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := (others => '0'); + COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; + COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; + HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; + --media interfaces + MII_NUMBER : integer range 2 to c_MAX_MII_PER_HUB := 3; + MII_IBUF_DEPTH : hub_iobuf_config_t := std_HUB_IBUF_DEPTH; + MII_IS_UPLINK : hub_mii_config_t := (others => c_YES); + MII_IS_DOWNLINK : hub_mii_config_t := (others => c_YES); + -- settings for external api connections + INT_NUMBER : integer range 0 to c_MAX_API_PER_HUB := 0; + INT_CHANNELS : hub_api_config_t := (3,3,3,3,3,3,3,3); + INT_IBUF_DEPTH : hub_api_config_t := (6,6,6,6,6,6,6,6) + ); + port ( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + --Media interfacces + MED_DATAREADY_OUT : out std_logic_vector (MII_NUMBER-1 downto 0); + MED_DATA_OUT : out std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT: out std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0); + MED_READ_IN : in std_logic_vector (MII_NUMBER-1 downto 0); + MED_DATAREADY_IN : in std_logic_vector (MII_NUMBER-1 downto 0); + MED_DATA_IN : in std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out std_logic_vector (MII_NUMBER-1 downto 0); + MED_STAT_OP : in std_logic_vector (MII_NUMBER*16-1 downto 0); + MED_CTRL_OP : out std_logic_vector (MII_NUMBER*16-1 downto 0); + --INT: interfaces to connect APIs + INT_INIT_DATAREADY_OUT : out std_logic_vector (INT_NUMBER downto 0); + INT_INIT_DATA_OUT : out std_logic_vector (INT_NUMBER*c_DATA_WIDTH downto 0); + INT_INIT_PACKET_NUM_OUT : out std_logic_vector (INT_NUMBER*c_NUM_WIDTH downto 0); + INT_INIT_READ_IN : in std_logic_vector (INT_NUMBER downto 0) := (others => '0'); + INT_INIT_DATAREADY_IN : in std_logic_vector (INT_NUMBER downto 0) := (others => '0'); + INT_INIT_DATA_IN : in std_logic_vector (INT_NUMBER*c_DATA_WIDTH downto 0) := (others => '0'); + INT_INIT_PACKET_NUM_IN : in std_logic_vector (INT_NUMBER*c_NUM_WIDTH downto 0) := (others => '0'); + INT_INIT_READ_OUT : out std_logic_vector (INT_NUMBER downto 0); + INT_REPLY_DATAREADY_OUT : out std_logic_vector (INT_NUMBER downto 0); + INT_REPLY_DATA_OUT : out std_logic_vector (INT_NUMBER*c_DATA_WIDTH downto 0); + INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (INT_NUMBER*c_NUM_WIDTH downto 0); + INT_REPLY_READ_IN : in std_logic_vector (INT_NUMBER downto 0) := (others => '0'); + INT_REPLY_DATAREADY_IN : in std_logic_vector (INT_NUMBER downto 0) := (others => '0'); + INT_REPLY_DATA_IN : in std_logic_vector (INT_NUMBER*c_DATA_WIDTH downto 0) := (others => '0'); + INT_REPLY_PACKET_NUM_IN : in std_logic_vector (INT_NUMBER*c_NUM_WIDTH downto 0) := (others => '0'); + INT_REPLY_READ_OUT : out std_logic_vector (INT_NUMBER downto 0); + ONEWIRE : inout std_logic; + ONEWIRE_MONITOR_OUT : out std_logic; + ONEWIRE_MONITOR_IN : in std_logic; + --Fixed status and control ports + HUB_STAT_CHANNEL : out std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0); + HUB_STAT_GEN : out std_logic_vector (31 downto 0); + MPLEX_CTRL : in std_logic_vector (MII_NUMBER*32-1 downto 0); + MPLEX_STAT : out std_logic_vector (MII_NUMBER*32-1 downto 0); + STAT_COMMON_STAT_REGS : out std_logic_vector (std_COMSTATREG*32-1 downto 0); --Status of common STAT regs + STAT_COMMON_CTRL_REGS : out std_logic_vector (std_COMCTRLREG*32-1 downto 0); --Status of common STAT regs + STAT_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom STAT regs + STAT_CTRL_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom CTRL regs + --Additional access to registers + REGIO_EXT_REG_DATA_IN : in std_logic_vector(31 downto 0); + REGIO_EXT_REG_DATA_OUT: out std_logic_vector(31 downto 0); + REGIO_EXT_REG_WRITE_IN: in std_logic; + REGIO_EXT_REG_ADDR_IN : in std_logic_vector(7 downto 0); + + --Debugging registers + STAT_DEBUG : out std_logic_vector (31 downto 0); --free status regs for debugging + CTRL_DEBUG : in std_logic_vector (31 downto 0) --free control regs for debugging + ); + end component; + + + + + + + component trb_net16_hub_ipu_logic is + generic ( + POINT_NUMBER : integer range 2 to 32 := 3 + ); + port ( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + --Internal interfaces to IOBufs + INIT_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); + INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); + INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); + INIT_READ_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); + INIT_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); + INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); + INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); + INIT_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); + REPLY_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); + REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_READ_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); + REPLY_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); + REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); + MY_ADDRESS_IN : in std_logic_vector (15 downto 0); + --Status ports + STAT_DEBUG : out std_logic_vector (31 downto 0); + STAT_POINTS_locked : out std_logic_vector (31 downto 0); + STAT_ERRORBITS : out std_logic_vector (31 downto 0); + CTRL : in std_logic_vector (15 downto 0); + CTRL_activepoints : in std_logic_vector (31 downto 0) := (others => '1') + ); + end component; + + + + component trb_net16_hub_logic is + generic ( + --media interfaces + POINT_NUMBER : integer range 2 to 32 := 2 + ); + port ( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + INIT_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); + INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); + INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); + INIT_READ_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); + INIT_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); + INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); + INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); + INIT_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); + REPLY_HEADER_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); + REPLY_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); + REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_READ_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); + REPLY_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); + REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); + STAT : out std_logic_vector (15 downto 0); + STAT_POINTS_locked : out std_logic_vector (31 downto 0); + STAT_ERRORBITS : out std_logic_vector (31 downto 0); + CTRL : in std_logic_vector (15 downto 0); + CTRL_activepoints : in std_logic_vector (31 downto 0) + ); + end component; + + end package trb_net16_hub_func; package body trb_net16_hub_func is diff --git a/trb_net16_hub_ipu_logic.vhd b/trb_net16_hub_ipu_logic.vhd index 7c7c009..07b60df 100644 --- a/trb_net16_hub_ipu_logic.vhd +++ b/trb_net16_hub_ipu_logic.vhd @@ -180,6 +180,9 @@ architecture trb_net16_hub_ipu_logic_arch of trb_net16_hub_ipu_logic is signal not_reading_HDR : std_logic; signal number_of_replies : unsigned(4 downto 0); signal expected_replies : std_logic_vector(POINT_NUMBER-1 downto 0); + signal reply_adder_final_result : std_logic_vector(15 downto 0); + signal next_reply_adder_final_result : std_logic_vector(15 downto 0); + signal last_reply_adder_ready: std_logic; begin @@ -725,7 +728,7 @@ reply_compare_finished <= reply_compare_start; current_waiting_for_reply, current_REPLY_reading_hdr, locking_point, real_activepoints, locked, MY_ADDRESS_IN, reply_adder_ready, reply_adder_result, reply_combined_trm_F3, reply_compare_finished, reply_adder_ready, - reply_adder_overflow, reply_adder_result, current_reply_reading_DHDR, + reply_adder_overflow, current_reply_reading_DHDR, reply_adder_final_result, evt_seqnr, evt_dtype, evt_random_code, evt_number, number_of_replies, current_muxed_reading_DAT,reply_data_counter, current_point_length, reply_arbiter_result, REPLY_DATAREADY_IN, saved_reply_arbiter_CLK_EN) @@ -747,7 +750,7 @@ reply_compare_finished <= reply_compare_start; reply_arbiter_CLK_EN <= '0'; reply_data_counter_reset <= '0'; start_read_padding <= (others => '0'); - + next_reply_adder_final_result <= reply_adder_final_result; case current_state is when IDLE => --wait for init transfer @@ -788,8 +791,9 @@ reply_compare_finished <= reply_compare_start; when GEN_LENGTH => --now, all HDR are stored, calc sum of HDR lengths last_dhdr_addr <= "010"; comb_REPLY_POOL_DATAREADY <= '0'; - comb_REPLY_POOL_DATA <= std_logic_vector(unsigned(reply_adder_result) - number_of_replies + 2); - if reply_adder_ready = '1' then --packet_counter = c_F2 + next_reply_adder_final_result <= std_logic_vector(unsigned(reply_adder_result) - number_of_replies + 2); + if last_reply_adder_ready = '1' then --packet_counter = c_F2 + comb_REPLY_POOL_DATA <= reply_adder_final_result; comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read; end if; if packet_counter = c_F3 then @@ -830,9 +834,9 @@ reply_compare_finished <= reply_compare_start; when c_F2 => next_reply_adder_start <= '1'; last_dhdr_addr <= "110"; - comb_REPLY_POOL_DATA <= std_logic_vector(unsigned(reply_adder_result) + number_of_replies); - if reply_adder_ready = '1' then - next_reply_adder_start <= '0'; + next_reply_adder_final_result <= std_logic_vector(unsigned(reply_adder_result) + number_of_replies); + if last_reply_adder_ready = '1' then + comb_REPLY_POOL_DATA <= reply_adder_final_result; comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read; end if; when others => --c_F3 @@ -941,6 +945,8 @@ reply_compare_finished <= reply_compare_start; waiting_for_DHDR_word <= (others => '1'); current_waiting_for_reply <= (others => '1'); got_all_reply_starts <= '0'; + reply_adder_final_result <= (others => '0'); + last_reply_adder_ready <= '0'; else current_state <= next_state; REPLY_POOL_next_read <= comb_REPLY_POOL_next_read; @@ -951,6 +957,8 @@ reply_compare_finished <= reply_compare_start; not_reading_HDR <= not or_all(current_reply_reading_HDR); number_of_replies <= to_unsigned(count_ones(expected_replies),5); expected_replies <= real_activepoints and not locking_point; + reply_adder_final_result <= next_reply_adder_final_result; + last_reply_adder_ready <= reply_adder_ready; end if; end if; end process; diff --git a/trb_net16_regIO.vhd b/trb_net16_regIO.vhd index 1369061..1fc04e4 100644 --- a/trb_net16_regIO.vhd +++ b/trb_net16_regIO.vhd @@ -466,34 +466,52 @@ begin when c_F0 => next_API_DATA_OUT <= address; when c_F1 => - if address(7 downto 6) = "01" then --0x40 - next_API_DATA_OUT <= rom_read_dout; - rom_read_addr <= address(1 downto 0) & '0'; - elsif address(7 downto 6) = "10" then --0x80 - next_API_DATA_OUT <= REGISTERS_IN(regnum_STAT*c_REGIO_REG_WIDTH+31 downto regnum_STAT*c_REGIO_REG_WIDTH+16); - elsif address(7 downto 6) = "11" then --0xC0 - next_API_DATA_OUT <= buf_REGISTERS_OUT(regnum_CTRL*c_REGIO_REG_WIDTH+31 downto regnum_CTRL*c_REGIO_REG_WIDTH+16); - elsif address(5) = '0' then --0x00 - next_API_DATA_OUT <= COMMON_STAT_REG_IN(regnum_cSTAT*c_REGIO_REG_WIDTH+31 downto regnum_cSTAT*c_REGIO_REG_WIDTH+16); - elsif address(5) = '1' then --0x20 - next_API_DATA_OUT <= buf_COMMON_CTRL_REG_OUT(regnum_cCTRL*c_REGIO_REG_WIDTH+31 downto regnum_cCTRL*c_REGIO_REG_WIDTH+16); - else - next_API_DATA_OUT <= (others => '0'); - end if; + case address(7 downto 4) is + when x"0" | x"1" => + next_API_DATA_OUT <= COMMON_STAT_REG_IN(regnum_cSTAT*c_REGIO_REG_WIDTH+31 downto regnum_cSTAT*c_REGIO_REG_WIDTH+16); + when x"2" | x"3" => + next_API_DATA_OUT <= buf_COMMON_CTRL_REG_OUT(regnum_cCTRL*c_REGIO_REG_WIDTH+31 downto regnum_cCTRL*c_REGIO_REG_WIDTH); + when x"4" => + next_API_DATA_OUT <= rom_read_dout; + rom_read_addr <= address(1 downto 0) & '0'; + when x"5" => + case address(0) is + when '0' => + next_API_DATA_OUT <= global_time_i(31 downto 16); + when '1' => + next_API_DATA_OUT <= time_since_last_trg_i(31 downto 16); + end case; + when x"8" | x"9" | x"A" | x"B" => + next_API_DATA_OUT <= REGISTERS_IN(regnum_STAT*c_REGIO_REG_WIDTH+31 downto regnum_STAT*c_REGIO_REG_WIDTH+16); + when x"C" | x"D" | x"E" | x"F" => + next_API_DATA_OUT <= buf_REGISTERS_OUT(regnum_CTRL*c_REGIO_REG_WIDTH+31 downto regnum_CTRL*c_REGIO_REG_WIDTH+16); + when others => + next_API_DATA_OUT <= (others => '0'); + end case; + when c_F2 => - if address(7 downto 6) = "01" then - next_API_DATA_OUT <= rom_read_dout; - elsif address(7 downto 6) = "10" then - next_API_DATA_OUT <= REGISTERS_IN(regnum_STAT*c_REGIO_REG_WIDTH+15 downto regnum_STAT*c_REGIO_REG_WIDTH); - elsif address(7 downto 6) = "11" then - next_API_DATA_OUT <= buf_REGISTERS_OUT(regnum_CTRL*c_REGIO_REG_WIDTH+15 downto regnum_CTRL*c_REGIO_REG_WIDTH); - elsif address(5) = '0' then - next_API_DATA_OUT <= COMMON_STAT_REG_IN(regnum_cSTAT*c_REGIO_REG_WIDTH+15 downto regnum_cSTAT*c_REGIO_REG_WIDTH); - elsif address(5) = '1' then - next_API_DATA_OUT <= buf_COMMON_CTRL_REG_OUT(regnum_cCTRL*c_REGIO_REG_WIDTH+15 downto regnum_cCTRL*c_REGIO_REG_WIDTH); - else - next_API_DATA_OUT <= (others => '0'); - end if; + case address(7 downto 4) is + when x"0" | x"1" => + next_API_DATA_OUT <= COMMON_STAT_REG_IN(regnum_cSTAT*c_REGIO_REG_WIDTH+15 downto regnum_cSTAT*c_REGIO_REG_WIDTH); + when x"2" | x"3" => + next_API_DATA_OUT <= buf_COMMON_CTRL_REG_OUT(regnum_cCTRL*c_REGIO_REG_WIDTH+15 downto regnum_cCTRL*c_REGIO_REG_WIDTH); + when x"4" => + next_API_DATA_OUT <= rom_read_dout; + when x"5" => + case address(0) is + when '0' => + next_API_DATA_OUT <= global_time_i(15 downto 0); + when '1' => + next_API_DATA_OUT <= time_since_last_trg_i(15 downto 0); + end case; + when x"8" | x"9" | x"A" | x"B" => + next_API_DATA_OUT <= REGISTERS_IN(regnum_STAT*c_REGIO_REG_WIDTH+15 downto regnum_STAT*c_REGIO_REG_WIDTH); + when x"C" | x"D" | x"E" | x"F" => + next_API_DATA_OUT <= buf_REGISTERS_OUT(regnum_CTRL*c_REGIO_REG_WIDTH+15 downto regnum_CTRL*c_REGIO_REG_WIDTH); + when others => + next_API_DATA_OUT <= (others => '0'); + end case; + when c_F3 => next_API_DATA_OUT <= (others => '0'); if API_READ_IN = '1' then diff --git a/trb_net_components.vhd b/trb_net_components.vhd index ba25b9b..115369d 100644 --- a/trb_net_components.vhd +++ b/trb_net_components.vhd @@ -13,6 +13,8 @@ package trb_net_components is + + component adc_ltc2308_readout is generic( CLOCK_FREQUENCY : integer := 100 --MHz @@ -44,6 +46,9 @@ package trb_net_components is + + + component trb_net16_api_base is generic ( API_TYPE : integer range 0 to 1 := c_API_PASSIVE; @@ -266,6 +271,8 @@ package trb_net_components is + + component trb_net16_fifo is generic ( USE_VENDOR_CORES : integer range 0 to 1 := c_NO; @@ -288,77 +295,9 @@ package trb_net_components is - component trb_net16_hub_ipu_logic is - generic ( - POINT_NUMBER : integer range 2 to 32 := 3 - ); - port ( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - --Internal interfaces to IOBufs - INIT_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); - INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); - INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); - INIT_READ_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); - INIT_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); - INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); - INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); - INIT_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); - REPLY_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); - REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); - REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); - REPLY_READ_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); - REPLY_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); - REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); - REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); - REPLY_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); - MY_ADDRESS_IN : in std_logic_vector (15 downto 0); - --Status ports - STAT_DEBUG : out std_logic_vector (31 downto 0); - STAT_POINTS_locked : out std_logic_vector (31 downto 0); - STAT_ERRORBITS : out std_logic_vector (31 downto 0); - CTRL : in std_logic_vector (15 downto 0); - CTRL_activepoints : in std_logic_vector (31 downto 0) := (others => '1') - ); - end component; - component trb_net16_hub_logic is - generic ( - --media interfaces - POINT_NUMBER : integer range 2 to 32 := 2 - ); - port ( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - INIT_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); - INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); - INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); - INIT_READ_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); - INIT_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); - INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); - INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); - INIT_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); - REPLY_HEADER_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); - REPLY_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); - REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); - REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); - REPLY_READ_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); - REPLY_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); - REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); - REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); - REPLY_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); - STAT : out std_logic_vector (15 downto 0); - STAT_POINTS_locked : out std_logic_vector (31 downto 0); - STAT_ERRORBITS : out std_logic_vector (31 downto 0); - CTRL : in std_logic_vector (15 downto 0); - CTRL_activepoints : in std_logic_vector (31 downto 0) - ); - end component; - @@ -493,6 +432,93 @@ package trb_net_components is + + + component trb_net16_med_ecp_sfp is + generic( + SERDES_NUM : integer range 0 to 3 := 0 + ); + port( + CLK : in std_logic; -- SerDes clock + SYSCLK : in std_logic; -- fabric clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset + CLK_EN : in std_logic; + --Internal Connection + MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_IN : in std_logic; + MED_READ_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_OUT : out std_logic; + MED_READ_IN : in std_logic; + REFCLK2CORE_OUT : out std_logic; + --SFP Connection + SD_RXD_P_IN : in std_logic; + SD_RXD_N_IN : in std_logic; + SD_TXD_P_OUT : out std_logic; + SD_TXD_N_OUT : out std_logic; + SD_REFCLK_P_IN : in std_logic; + SD_REFCLK_N_IN : in std_logic; + SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + -- Status and control port + STAT_OP : out std_logic_vector (15 downto 0); + CTRL_OP : in std_logic_vector (15 downto 0); + STAT_DEBUG : out std_logic_vector (63 downto 0); + CTRL_DEBUG : in std_logic_vector (63 downto 0) + ); + end component; + + + + + + + component trb_net16_med_ecp_sfp_4 is + generic( + REVERSE_ORDER : integer range 0 to 1 := c_NO + -- USED_PORTS : std_logic-vector(3 downto 0) := "1111" + ); + port( + CLK : in std_logic; -- SerDes clock + SYSCLK : in std_logic; -- fabric clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset + CLK_EN : in std_logic; + --Internal Connection + MED_DATA_IN : in std_logic_vector(4*c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector(4*c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_IN : in std_logic_vector(3 downto 0); + MED_READ_OUT : out std_logic_vector(3 downto 0); + MED_DATA_OUT : out std_logic_vector(4*c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector(4*c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_OUT : out std_logic_vector(3 downto 0); + MED_READ_IN : in std_logic_vector(3 downto 0); + REFCLK2CORE_OUT : out std_logic; + --SFP Connection + SD_RXD_P_IN : in std_logic_vector(3 downto 0); + SD_RXD_N_IN : in std_logic_vector(3 downto 0); + SD_TXD_P_OUT : out std_logic_vector(3 downto 0); + SD_TXD_N_OUT : out std_logic_vector(3 downto 0); + SD_REFCLK_P_IN : in std_logic; + SD_REFCLK_N_IN : in std_logic; + SD_PRSNT_N_IN : in std_logic_vector(3 downto 0); + SD_LOS_IN : in std_logic_vector(3 downto 0); + -- Status and control port + STAT_OP : out std_logic_vector (4*16-1 downto 0); + CTRL_OP : in std_logic_vector (4*16-1 downto 0); + STAT_DEBUG : out std_logic_vector (63 downto 0); + CTRL_DEBUG : in std_logic_vector (63 downto 0) + ); + end component; + + + + + + component trb_net_onewire is generic( USE_TEMPERATURE_READOUT : integer range 0 to 1 := 1; @@ -534,6 +560,20 @@ package trb_net_components is + component pll25 is + port( + CLK : in std_logic; + RESET : in std_logic; + CLKOP : out std_logic; + CLKOK : out std_logic; + LOCK : out std_logic + ); + end component; + + + + + component pll_in25_out100 is port ( @@ -548,6 +588,24 @@ package trb_net_components is + component signal_sync is + generic( + WIDTH : integer := 1; -- + DEPTH : integer := 3 + ); + port( + RESET : in std_logic; --Reset is neceessary to avoid optimization to shift register + CLK0 : in std_logic; --clock for first FF + CLK1 : in std_logic; --Clock for other FF + D_IN : in std_logic_vector(WIDTH-1 downto 0); --Data input + D_OUT : out std_logic_vector(WIDTH-1 downto 0) --Data output + ); + end component; + + + + + component trb_net_priority_arbiter is generic ( WIDTH : integer := 1 diff --git a/trb_net_std.vhd b/trb_net_std.vhd index ed03630..069f27d 100644 --- a/trb_net_std.vhd +++ b/trb_net_std.vhd @@ -133,6 +133,9 @@ package trb_net_std is constant c_max_word_number : std_logic_vector(2 downto 0) := "100"; --constant VERSION_NUMBER_TIME : std_logic_vector(31 downto 0) := conv_std_logic_vector(1234567890,32); + + + --function declarations function and_all (arg : std_logic_vector) return std_logic;