From: Jan Michel <j.michel@gsi.de>
Date: Mon, 11 Jul 2016 16:57:01 +0000 (+0200)
Subject: Disconnect some debug signals for better timing
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=9a75092eed5081a2ecc6363daece399dfdc7780b;p=trbnet.git

Disconnect some debug signals for better timing
---

diff --git a/media_interfaces/sync/tx_control.vhd b/media_interfaces/sync/tx_control.vhd
index 2ffcd57..313b015 100644
--- a/media_interfaces/sync/tx_control.vhd
+++ b/media_interfaces/sync/tx_control.vhd
@@ -486,11 +486,11 @@ tx_allow_q          <= tx_allow_qtx when rising_edge(CLK_100);
   DEBUG_OUT(1) <= ct_fifo_write;
   DEBUG_OUT(2) <= ct_fifo_read;
   DEBUG_OUT(3) <= tx_allow_qtx;
-  DEBUG_OUT(4) <= ram_empty;
+--   DEBUG_OUT(4) <= ram_empty;
   DEBUG_OUT(5) <= ram_afull;
   DEBUG_OUT(6) <= debug_sending_dlm when rising_edge(CLK_200);
   DEBUG_OUT(7) <= TX_WRITE_IN;
-  DEBUG_OUT(8) <= ram_read;
+--   DEBUG_OUT(8) <= ram_read;
   DEBUG_OUT(9) <= ram_write;
   DEBUG_OUT(13 downto 10) <= state_bits;
   DEBUG_OUT(15 downto 14) <= "00";
@@ -500,10 +500,11 @@ tx_allow_q          <= tx_allow_qtx when rising_edge(CLK_100);
   process(CLK_100)
     begin
       if rising_edge(CLK_100) then
+        STAT_REG_OUT <= (others => '0');
         STAT_REG_OUT(7 downto 0)   <= std_logic_vector(ram_fill_level);
         STAT_REG_OUT(15 downto 8)  <= std_logic_vector(ram_read_addr);
-        STAT_REG_OUT(16)           <= ram_afull;
-        STAT_REG_OUT(17)           <= ram_empty;
+--         STAT_REG_OUT(16)           <= ram_afull;
+--         STAT_REG_OUT(17)           <= ram_empty;
         STAT_REG_OUT(18)           <= tx_allow_qtx;
         STAT_REG_OUT(19)           <= TX_ALLOW_IN;
         STAT_REG_OUT(20)           <= make_restart_i;