From: hadeshyp Date: Tue, 31 Mar 2009 08:11:02 +0000 (+0000) Subject: *** empty log message *** X-Git-Tag: oldGBE~468 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=9b3772837f6ad2d5db70cf04611613cd22798d99;p=trbnet.git *** empty log message *** --- diff --git a/basics/ram_dp.vhd b/basics/ram_dp.vhd index a4c0f63..46dab7e 100644 --- a/basics/ram_dp.vhd +++ b/basics/ram_dp.vhd @@ -24,7 +24,7 @@ end entity; architecture ram_dp_arch of ram_dp is type ram_t is array(0 to 2**depth-1) of std_logic_vector(width-1 downto 0); - SIGNAL ram : ram_t := (others => (others => '0')); + SIGNAL ram : ram_t ; -- := (others => (others => '0')); begin diff --git a/special/adc_ltc2308_readout.vhd b/special/adc_ltc2308_readout.vhd index e63badf..38e70e1 100644 --- a/special/adc_ltc2308_readout.vhd +++ b/special/adc_ltc2308_readout.vhd @@ -159,7 +159,7 @@ begin dout2 => value_ram_data ); - ram_addr <= last_channel; + ram_addr <= std_logic_vector(unsigned(last_channel) - to_unsigned(1,1)); value_ram_addr <= range_ram_addr; @@ -213,7 +213,7 @@ begin case state is when IDLE => -- output bits: singleended/not differential & channel number(3) & unipolar/not bipolar & sleepmode - output_data <= "1" & current_channel & "00"; + output_data <= "1" & current_channel(0) & current_channel(2) & (current_channel(1)) & "10"; input_data <= (others => '0'); timecounter <= (others => '0'); ADC_SCK <= '0'; @@ -302,7 +302,7 @@ begin DAT_DATAREADY_OUT <= '0'; DAT_DATA_OUT <= (others => '0'); range_ram_wr <= '0'; - conv_enabled <= '0'; + conv_enabled <= '1'; conv_single <= '0'; conv_reset <= '0'; conv_compare_enable <= '0'; @@ -320,50 +320,48 @@ begin last_DAT_READ_EN_IN <= '0'; if DAT_WRITE_EN_IN = '1' then - case DAT_ADDR_IN is - when "000000" => - conv_enabled <= DAT_DATA_IN(0); - conv_single <= DAT_DATA_IN(1); - conv_reset <= DAT_DATA_IN(2); - conv_compare_enable <= DAT_DATA_IN(3); - DAT_WRITE_ACK_OUT <= '1'; - when "100---" => - range_ram_wr <= '1'; - DAT_WRITE_ACK_OUT <= '1'; - when others => - DAT_UNKNOWN_ADDR_OUT <= '1'; - end case; + if DAT_ADDR_IN = "000000" then + conv_enabled <= DAT_DATA_IN(0); + conv_single <= DAT_DATA_IN(1); + conv_reset <= DAT_DATA_IN(2); + conv_compare_enable <= DAT_DATA_IN(3); + DAT_WRITE_ACK_OUT <= '1'; + elsif DAT_ADDR_IN(5 downto 3) = "100" then -- "100---" + range_ram_wr <= '1'; + DAT_WRITE_ACK_OUT <= '1'; + else + DAT_UNKNOWN_ADDR_OUT <= '1'; + end if; end if; if DAT_READ_EN_IN = '1' or last_DAT_READ_EN_IN = '1' then - case DAT_ADDR_IN is - when "000000" => - DAT_DATA_OUT <= (0 => conv_enabled, 1 => conv_single, 3 => conv_compare_enable, others => '0'); - DAT_DATAREADY_OUT <= '1'; - when "000001" => - DAT_DATA_OUT <= status_overview; - DAT_DATAREADY_OUT <= '1'; - when "010---" => - DAT_DATA_OUT(31 downto 0) <= value_ram_data; - if DAT_READ_EN_IN = '1' then - last_DAT_READ_EN_IN <= '1'; - else - last_DAT_READ_EN_IN <= '0'; - DAT_DATAREADY_OUT <= '1'; - end if; - when "100---" => - DAT_DATA_OUT(11 downto 0) <= range_ram_data_out(11 downto 0); - DAT_DATA_OUT(15 downto 12) <= (others => '0'); - DAT_DATA_OUT(27 downto 16) <= range_ram_data_out(23 downto 12); - DAT_DATA_OUT(31 downto 28) <= (others => '0'); - if DAT_READ_EN_IN = '1' then - last_DAT_READ_EN_IN <= '1'; - else - last_DAT_READ_EN_IN <= '0'; - DAT_DATAREADY_OUT <= '1'; - end if; - when others => - DAT_UNKNOWN_ADDR_OUT <= '1'; - end case; + if DAT_ADDR_IN(5 downto 0) = "000000" then + DAT_DATA_OUT <= (0 => conv_enabled, 1 => conv_single, 3 => conv_compare_enable, others => '0'); + DAT_DATAREADY_OUT <= '1'; + elsif DAT_ADDR_IN(5 downto 0) = "000001" then + DAT_DATA_OUT <= status_overview; + DAT_DATAREADY_OUT <= '1'; + elsif DAT_ADDR_IN(5 downto 3) = "010" then --"010000" + DAT_DATA_OUT(31 downto 0) <= value_ram_data; + if DAT_READ_EN_IN = '1' then + last_DAT_READ_EN_IN <= '1'; + else + last_DAT_READ_EN_IN <= '0'; + DAT_DATAREADY_OUT <= '1'; + end if; + elsif DAT_ADDR_IN(5 downto 3) = "100" then --"100000" + DAT_DATA_OUT(11 downto 0) <= range_ram_data_out(11 downto 0); + DAT_DATA_OUT(15 downto 12) <= (others => '0'); + DAT_DATA_OUT(27 downto 16) <= range_ram_data_out(23 downto 12); + DAT_DATA_OUT(31 downto 28) <= (others => '0'); + if DAT_READ_EN_IN = '1' then + last_DAT_READ_EN_IN <= '1'; + else + last_DAT_READ_EN_IN <= '0'; + DAT_DATAREADY_OUT <= '1'; + end if; + else + DAT_UNKNOWN_ADDR_OUT <= '1'; + end if; end if; end if; end if; @@ -371,6 +369,5 @@ begin STAT_VOLTAGES_OUT <= status_overview; - DAT_NO_MORE_DATA_OUT <= '0'; end architecture; diff --git a/special/trb_net_bridge_etrax_apl.vhd b/special/trb_net_bridge_etrax_apl.vhd index 35b486c..a0edb2e 100644 --- a/special/trb_net_bridge_etrax_apl.vhd +++ b/special/trb_net_bridge_etrax_apl.vhd @@ -127,11 +127,11 @@ begin CPU_DATAREADY_OUT <= b_CPU_DATAREADY_OUT; - STAT(11) <= CPU_WRITE; + STAT(9 downto 0) <= reg_CPU_ADDRESS(9 downto 0); STAT(10) <= CPU_READ; + STAT(11) <= CPU_WRITE; STAT(12) <= b_CPU_DATAREADY_OUT; STAT(13) <= fifo_net_to_pci_read(1); - STAT(9 downto 0) <= reg_CPU_ADDRESS(9 downto 0); STAT(15 downto 14) <= reg_CPU_DATA_IN(1 downto 0); STAT(16) <= fifo_pci_to_net_read(1); STAT(17) <= fifo_pci_to_net_valid_read(1); @@ -141,6 +141,9 @@ begin STAT(21) <= fifo_pci_to_net_full(1); STAT(22) <= RESET; STAT(23) <= '0'; + STAT(24) <= fifo_net_to_pci_empty(1); + STAT(25) <= fifo_net_to_pci_read(1); + STAT(26) <= fifo_net_to_pci_write(1); STAT(31 downto 27) <= (others => '0'); -------------------------------- @@ -208,55 +211,62 @@ begin -------------------------------- -- connection to API -------------------------------- - fifo_pci_to_net_read <= APL_READ_IN; --NOT CORRECT - last packet may be lost + + + process(CLK) + begin + if rising_edge(CLK) then + APL_SEND_OUT <= next_APL_SEND_OUT; + end if; + end process; gen_api_connect : for i in 0 to 2**(c_MUX_WIDTH)-1 generate - APL_DTYPE_OUT(i*4+3 downto i*4) <= sender_control(i*32+3 downto i*32); - api_status(i*32+7 downto i*32) <= APL_SEQNR_IN(i*8+7 downto i*8); - api_status(i*32+31 downto i*32+8) <= (others => '0'); --- APL_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) --- <= fifo_pci_to_net_dout((c_DATA_WIDTH+c_NUM_WIDTH)*i+c_DATA_WIDTH-1 downto (c_DATA_WIDTH+c_NUM_WIDTH)*i); --- APL_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= fifo_pci_to_net_dout; - sender_status(i*32) <= APL_RUN_IN(i); + + + api_status(i*32+7 downto i*32) <= APL_SEQNR_IN(i*8+7 downto i*8); + api_status(i*32+31 downto i*32+8) <= (others => '0'); + sender_status(i*32) <= APL_RUN_IN(i); sender_status(i*32+31 downto i*32+1) <= (others => '0'); - --api_status(i*32+10 downto i*32+8) <= APL_TYP_IN; + + + --connection to API next_APL_SEND_OUT(i) <= '1' when reg_CPU_ADDRESS(11 downto 8) = "0001" and reg_CPU_ADDRESS(7 downto 4) = i and reg_CPU_ADDRESS(3 downto 0) = "0000" and reg_CPU_WRITE = '1' else '0'; - APL_DATAREADY_OUT(i) <= fifo_pci_to_net_valid_read(i); - APL_SHORT_TRANSFER_OUT(i) <= sender_control(i*32+8); - APL_ERROR_PATTERN_OUT(i*32+31 downto i*32) <= sender_error(i*32+31 downto i*32); + + APL_DATAREADY_OUT(i) <= fifo_pci_to_net_valid_read(i); + APL_DATA_OUT((i+1)*16-1 downto i*16) <= fifo_pci_to_net_dout(i*18+c_DATA_WIDTH-1 downto i*18); + APL_PACKET_NUM_OUT((i)*3+1 downto i*3) <= fifo_pci_to_net_dout(i*18+c_DATA_WIDTH+1 downto i*18+c_DATA_WIDTH); + APL_PACKET_NUM_OUT(i*3+2) <= '0'; + APL_SHORT_TRANSFER_OUT(i) <= sender_control(i*32+8); + APL_ERROR_PATTERN_OUT(i*32+31 downto i*32) <= sender_error(i*32+31 downto i*32); APL_TARGET_ADDRESS_OUT(i*16+15 downto i*16) <= sender_target(i*32+15 downto i*32); - APL_READ_OUT(i) <= not fifo_net_to_pci_full(i); - fifo_net_to_pci_write(i) <= APL_DATAREADY_IN(i) and not fifo_net_to_pci_full(i); + APL_DTYPE_OUT(i*4+3 downto i*4) <= sender_control(i*32+3 downto i*32); + fifo_pci_to_net_read(i) <= APL_READ_IN(i); --NOT CORRECT - last packet may be lost, but transfer size is limited anyhow + + + --connection from API + fifo_net_to_pci_dout(i*32+31 downto i*32+25) <= (others => '0'); + fifo_net_to_pci_dout(i*32+23 downto i*32+18) <= (others => '0'); + fifo_net_to_pci_dout(i*32+24) <= fifo_net_to_pci_valid_read(i); + + fifo_net_to_pci_din(18*i+c_DATA_WIDTH-1 downto 18*i) <= APL_DATA_IN(c_DATA_WIDTH*(i+1)-1 downto c_DATA_WIDTH*i); + fifo_net_to_pci_din(18*i+c_DATA_WIDTH) <= APL_PACKET_NUM_IN(c_NUM_WIDTH*i); + fifo_net_to_pci_din(18*i+c_DATA_WIDTH+1) <= APL_PACKET_NUM_IN(c_NUM_WIDTH*i+2); + fifo_net_to_pci_write(i) <= APL_DATAREADY_IN(i) and not fifo_net_to_pci_full(i); + APL_READ_OUT(i) <= not fifo_net_to_pci_full(i); + end generate; - process(CLK) - begin - if rising_edge(CLK) then - APL_SEND_OUT <= next_APL_SEND_OUT; - end if; - end process; + -------------------------------- -- fifo as bridge to pci -------------------------------- - gen_incoming_fifos : for i in 0 to 2**(c_MUX_WIDTH)-1 generate - - fifo_net_to_pci_dout(i*32+31 downto i*32+25) <= (others => '0'); - fifo_net_to_pci_dout(i*32+23 downto i*32+18) <= (others => '0'); - fifo_net_to_pci_dout(i*32+24) <= fifo_net_to_pci_valid_read(i); - fifo_net_to_pci_din(18*i+c_DATA_WIDTH+1 downto 18*i) <= APL_PACKET_NUM_IN(c_NUM_WIDTH*i+2) & APL_PACKET_NUM_IN(c_NUM_WIDTH*i) & APL_DATA_IN(c_DATA_WIDTH*(i+1)-1 downto c_DATA_WIDTH*i); --- fifo_net_to_pci_din(32*i+31 downto 32*i+c_DATA_WIDTH+18) <= (others => '0'); - APL_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= fifo_pci_to_net_dout(i*18+c_DATA_WIDTH-1 downto i*18); - APL_PACKET_NUM_OUT((i)*3+1 downto i*3) <= fifo_pci_to_net_dout(i*18+c_DATA_WIDTH+1 downto i*18+c_DATA_WIDTH); - APL_PACKET_NUM_OUT(i*3+2) <= '0'; - STAT(24) <= fifo_net_to_pci_empty(1); - STAT(25) <= fifo_net_to_pci_read(1); - STAT(26) <= fifo_net_to_pci_write(1); + gen_incoming_fifos : for i in 0 to 2**(c_MUX_WIDTH)-1 generate FIFO_NET_TO_PCI: trb_net16_fifo generic map( @@ -299,20 +309,18 @@ begin full_out => fifo_pci_to_net_full(i), empty_out => fifo_pci_to_net_empty(i) ); --- fifo_pci_to_net_dout(32*i+31 downto 32*i+18) <= (others => '0'); - end generate; -process(CLK) - begin - if rising_edge(CLK) then - fifo_pci_to_net_valid_read <= fifo_pci_to_net_read and not fifo_pci_to_net_empty; - fifo_net_to_pci_valid_read <= fifo_net_to_pci_read and not fifo_net_to_pci_empty; - end if; - end process; + end generate; ---write/read flags for fifo + proc_valid_read : process(CLK) + begin + if rising_edge(CLK) then + fifo_pci_to_net_valid_read <= fifo_pci_to_net_read and not fifo_pci_to_net_empty; + fifo_net_to_pci_valid_read <= fifo_net_to_pci_read and not fifo_net_to_pci_empty; + end if; + end process; - process(reg_CPU_ADDRESS, reg_CPU_READ, reg_CPU_WRITE, channel_address) + proc_fifo_readwrite : process(reg_CPU_ADDRESS, reg_CPU_READ, reg_CPU_WRITE, channel_address) begin fifo_net_to_pci_read <= (others => '0'); fifo_pci_to_net_write <= (others => '0'); @@ -324,11 +332,7 @@ process(CLK) end if; end process; --------------------------------- --- synchronize to slow PCI clock --------------------------------- - - register_slow_output : process(CLK) + proc_register_cpu_output : process(CLK) begin if rising_edge(CLK) then buf_CPU_DATA_OUT <= next_CPU_DATA_OUT; @@ -339,7 +343,6 @@ process(CLK) process(CPU_ADDRESS, buf_CPU_DATA_OUT, fifo_net_to_pci_dout,reg_CPU_ADDRESS, last_fifo_read, buf_CPU_DATAREADY_OUT) begin --- last_CPU_ADDRESS <= CPU_ADDRESS; if reg_CPU_ADDRESS(11 downto 8) & reg_CPU_ADDRESS(3 downto 0) = x"23" then CPU_DATA_OUT <= fifo_net_to_pci_dout((conv_integer(reg_CPU_ADDRESS(6 downto 4)))*32+31 downto conv_integer(reg_CPU_ADDRESS(6 downto 4))*32); b_CPU_DATAREADY_OUT <= last_fifo_read; @@ -350,7 +353,7 @@ process(CLK) end process; - register_slow_dat_addr_input : process(CLK) + proc_reg_cpu_input : process(CLK) begin if rising_edge(CLK) then reg_CPU_ADDRESS <= CPU_ADDRESS; diff --git a/special/trb_net_bridge_etrax_endpoint.vhd b/special/trb_net_bridge_etrax_endpoint.vhd index 1974f8b..63db4a6 100644 --- a/special/trb_net_bridge_etrax_endpoint.vhd +++ b/special/trb_net_bridge_etrax_endpoint.vhd @@ -314,23 +314,6 @@ begin CLK_EN <= '1'; APL_MY_ADDRESS_IN <= x"F00C"; RESET_i <= RESET; --- process(CLK) --- begin --- if rising_edge(CLK) then --- if RESET = '1' then --- RESET_i <= '1'; --- RESET_CNT <= "00"; --- else --- counter <= counter + 1; --- RESET_CNT <= RESET_CNT + 1; --- RESET_i <= '1'; --- if RESET_CNT = "11" then --- RESET_i <= '0'; --- RESET_CNT <= "11"; --- end if; --- end if; --- end if; --- end process; MED_DATAREADY_OUT <= buf_MED_DATAREADY_OUT; @@ -568,11 +551,28 @@ STAT_ENDP(4 downto 1) <= CPU_ADDRESS(3 downto 0); STAT_ENDP(5) <= CPU_READ; STAT_ENDP(6) <= APL_READ_OUT(1); STAT_ENDP(7) <= buf_MED_DATAREADY_OUT; -STAT_ENDP(11 downto 8) <= APL_DATA_IN(3 downto 0); -STAT_ENDP(13 downto 12) <= APL_PACKET_NUM_IN(4 downto 3); -STAT_ENDP(14) <= APL_DATAREADY_IN(1); +STAT_ENDP(11 downto 8) <= APL_DATA_OUT(51 downto 48); +STAT_ENDP(13 downto 12) <= APL_PACKET_NUM_OUT(4 downto 3); +STAT_ENDP(14) <= APL_DATAREADY_OUT(3); STAT_ENDP(15) <= buf_to_apl_REPLY_DATAREADY(0); -STAT_ENDP(31 downto 16) <= (others => '0'); -STAT_API1 <= buf_api_stat_fifo_to_int((2)*32-1 downto (1)*32); +STAT_ENDP(16) <= APL_READ_IN(3); + +STAT_ENDP(17) <= '0'; +STAT_ENDP(18) <= '0'; + +STAT_ENDP(21 downto 19) <= APL_PACKET_NUM_OUT(11 downto 9); +STAT_ENDP(22) <= APL_DATAREADY_OUT(3); +STAT_ENDP(23) <= APL_READ_IN(3); +STAT_ENDP(31 downto 24) <= APL_DATA_OUT(55 downto 48); + + +STAT_API1(7 downto 0) <= buf_to_apl_REPLY_DATA(23 downto 16); +STAT_API1(8) <= buf_to_apl_REPLY_READ(1); +STAT_API1(9) <= buf_to_apl_REPLY_DATAREADY(1); +STAT_API1(12 downto 10) <= buf_to_apl_REPLY_PACKET_NUM(5 downto 3); +STAT_API1(31 downto 13) <= (others => '0'); + + +--STAT_API1 <= buf_api_stat_fifo_to_int((2)*32-1 downto (1)*32); end architecture; \ No newline at end of file diff --git a/testbenches/trb_net16_dummy_apl.vhd b/testbenches/trb_net16_dummy_apl.vhd index a13a4e6..2d6fb8e 100644 --- a/testbenches/trb_net16_dummy_apl.vhd +++ b/testbenches/trb_net16_dummy_apl.vhd @@ -56,10 +56,12 @@ architecture trb_net16_dummy_apl_arch of trb_net16_dummy_apl is signal buf_APL_DATA_OUT, next_APL_DATA_OUT : std_logic_vector(c_DATA_WIDTH-1 downto 0); signal buf_APL_WRITE_OUT, next_APL_WRITE_OUT : std_logic; signal buf_APL_SEND_OUT, next_APL_SEND_OUT : std_logic; + signal buf_APL_READ_OUT : std_logic; signal next_packet_counter, packet_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal address, reghigh, reglow : std_logic_vector(15 downto 0); signal state_bits : std_logic_vector(2 downto 0); signal reg_F0, reg_F1, reg_F2, reg_F3 : std_logic_vector(15 downto 0); + signal timing : std_logic_vector(15 downto 0); begin -- address <= x"0008"; @@ -82,7 +84,18 @@ begin end case; end process; - APL_READ_OUT <= '0', '1' after 30000 ns; --just read, do not check + + PROC_READ_OUT : process(timing, CLK) + begin + if timing < 3000 then + buf_APL_READ_OUT <= '0'; + elsif rising_edge(CLK) then + buf_APL_READ_OUT <= not buf_APL_READ_OUT; + end if; + end process; + + APL_READ_OUT <= buf_APL_READ_OUT; + APL_ERROR_PATTERN_OUT <= x"12345678"; --APL_DATA_OUT <= reg_counter; @@ -170,6 +183,7 @@ APL_DATAREADY_OUT <= buf_APL_WRITE_OUT; buf_APL_DATA_OUT <= (others => '0'); buf_APL_WRITE_OUT <= '0'; buf_APL_SEND_OUT <= '0'; + timing <= (others => '0'); elsif CLK_EN = '1' then reg_counter <= next_counter; current_state <= next_state; @@ -177,6 +191,7 @@ APL_DATAREADY_OUT <= buf_APL_WRITE_OUT; buf_APL_DATA_OUT <= next_APL_DATA_OUT; buf_APL_WRITE_OUT <= next_APL_WRITE_OUT; buf_APL_SEND_OUT <= next_APL_SEND_OUT; + timing <= timing + 1; end if; end if; end process; diff --git a/trb_net16_api_base.vhd b/trb_net16_api_base.vhd index 0d6d124..56c0e0a 100644 --- a/trb_net16_api_base.vhd +++ b/trb_net16_api_base.vhd @@ -16,7 +16,7 @@ entity trb_net16_api_base is USE_VENDOR_CORES : integer range 0 to 1 := c_YES; SECURE_MODE_TO_APL: integer range 0 to 1 := c_YES; SECURE_MODE_TO_INT: integer range 0 to 1 := c_YES; - APL_WRITE_ALL_WORDS:integer range 0 to 1 := c_NO; + APL_WRITE_ALL_WORDS:integer range 0 to 1 := c_YES; BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF" ); @@ -747,7 +747,7 @@ INT_MASTER_DATAREADY_OUT <= buf_INT_MASTER_DATAREADY_OUT; else next_APL_DATAREADY_OUT <= fifo_to_apl_read_before and sbuf_to_apl_free; end if; - fifo_to_apl_read <= not fifo_to_apl_empty and not (fifo_to_apl_read_before and not sbuf_to_apl_free and not throw_away); + fifo_to_apl_read <= not fifo_to_apl_empty and not (fifo_to_apl_read_before and not (sbuf_to_apl_free or throw_away)); if reg_APL_TYP_OUT = TYPE_TRM and reg_APL_PACKET_NUM_OUT = c_F3 and sbuf_to_apl_free = '1' then next_state_to_apl <= sa_INACTIVE; slave_end <= '1'; diff --git a/trb_net16_endpoint_0_trg_1_api.vhd b/trb_net16_endpoint_0_trg_1_api.vhd index 22a163b..563b090 100644 --- a/trb_net16_endpoint_0_trg_1_api.vhd +++ b/trb_net16_endpoint_0_trg_1_api.vhd @@ -166,7 +166,7 @@ architecture trb_net16_endpoint_0_trg_1_api_arch of trb_net16_endpoint_0_trg_1_a USE_VENDOR_CORES : integer range 0 to 1 := c_YES; SECURE_MODE_TO_APL: integer range 0 to 1 := c_YES; SECURE_MODE_TO_INT: integer range 0 to 1 := c_YES; - APL_WRITE_ALL_WORDS:integer range 0 to 1 := c_NO; + APL_WRITE_ALL_WORDS:integer range 0 to 1 := c_YES; BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF" ); diff --git a/trb_net16_ibuf.vhd b/trb_net16_ibuf.vhd index bd9c72f..bdcfcdd 100644 --- a/trb_net16_ibuf.vhd +++ b/trb_net16_ibuf.vhd @@ -404,7 +404,7 @@ counter_match <= '1'; process(fifo_data_out, fifo_long_packet_num_out, sbuf_init_free, RESET, fifo_empty, sbuf_reply_free, last_fifo_read, current_fifo_packet_type, - fifo_read_before, CRC_match) + fifo_read_before, CRC_match, throw_away) begin tmp_INT_DATA_OUT <= fifo_data_out; @@ -433,6 +433,8 @@ counter_match <= '1'; ((sbuf_init_free and not current_fifo_packet_type(3)) or (sbuf_reply_free and current_fifo_packet_type(3)) or throw_away)); + + if (fifo_read_before = '1' and (current_fifo_packet_type(2 downto 0) /= TYPE_EOB)) then if SECURE_MODE = 1 then tmp_INT_INIT_DATAREADY_OUT <= (sbuf_init_free) and not current_fifo_packet_type(3); diff --git a/trb_net16_ipudata.vhd b/trb_net16_ipudata.vhd index f97154d..5bb44e4 100644 --- a/trb_net16_ipudata.vhd +++ b/trb_net16_ipudata.vhd @@ -73,10 +73,12 @@ architecture trb_net16_ipudata_arch of trb_net16_ipudata is signal waiting_word : std_logic; signal packet_number : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal reg_IPU_DATA : std_logic_vector (15 downto 0); + signal reg_IPU_DATA_high : std_logic_vector (15 downto 0); signal saved_IPU_READOUT_FINISHED_IN : std_logic; signal state_bits : std_logic_vector(2 downto 0); signal dhdr_counter : std_logic_vector(1 downto 0); signal first_ipu_read : std_logic; + signal ipu_read_before : std_logic; begin @@ -148,13 +150,19 @@ begin end if; when READING => - buf_API_DATAREADY_OUT <= IPU_DATAREADY_IN or waiting_word; + buf_API_DATAREADY_OUT <= IPU_DATAREADY_IN or waiting_word or ipu_read_before; + if API_READ_IN = '1' then + ipu_read_before <= '0'; + end if; if buf_API_DATAREADY_OUT = '1' and API_READ_IN = '1' then waiting_word <= '0'; end if; - if IPU_DATAREADY_IN = '1' and buf_IPU_READ = '1' then + if IPU_DATAREADY_IN = '1' and waiting_word = '0' and buf_IPU_READ = '1' then buf_API_DATA_OUT <= IPU_DATA_IN(31 downto 16); waiting_word <= '1'; + ipu_read_before <= '1'; + elsif ipu_read_before = '1' and API_READ_IN = '0' then + buf_API_DATA_OUT <= reg_IPU_DATA_high; else buf_API_DATA_OUT <= reg_IPU_DATA; end if; @@ -192,8 +200,10 @@ begin if rising_edge(CLK) then if RESET = '1' then reg_IPU_DATA <= (others => '0'); + reg_IPU_DATA_high <= (others => '0'); elsif IPU_DATAREADY_IN = '1' and buf_IPU_READ = '1' then - reg_IPU_DATA <= IPU_DATA_IN(15 downto 0); + reg_IPU_DATA <= IPU_DATA_IN(15 downto 0); + reg_IPU_DATA_high <= IPU_DATA_IN(31 downto 16); end if; end if; end process; diff --git a/trb_net16_obuf.vhd b/trb_net16_obuf.vhd index 0ed45ed..0ced3f9 100644 --- a/trb_net16_obuf.vhd +++ b/trb_net16_obuf.vhd @@ -176,7 +176,7 @@ begin STAT_BUFFER(1 downto 0) <= TRANSMITTED_BUFFERS; STAT_BUFFER(14 downto 2) <= (others => '0'); STAT_BUFFER(15) <= send_DATA; - STAT_BUFFER(20 downto 16) <= CURRENT_DATA_COUNT; + STAT_BUFFER(20 downto 16) <= CURRENT_DATA_COUNT(4 downto 0); STAT_BUFFER(31 downto 21) <= (others => '0'); SEND_BUFFER_SIZE_IN <= CTRL_BUFFER(3 downto 0); REC_BUFFER_SIZE_IN <= CTRL_BUFFER(7 downto 4); diff --git a/xilinx/virtex4/trb_net16_fifo_arch.vhd b/xilinx/virtex4/trb_net16_fifo_arch.vhd index 81731f6..219e9fc 100644 --- a/xilinx/virtex4/trb_net16_fifo_arch.vhd +++ b/xilinx/virtex4/trb_net16_fifo_arch.vhd @@ -28,7 +28,7 @@ entity trb_net16_fifo is end entity; architecture arch_trb_net16_fifo of trb_net16_fifo is -attribute box_type: string; +-- attribute box_type: string; component xilinx_fifo_18x1k port ( @@ -41,7 +41,7 @@ attribute box_type: string; empty: OUT std_logic; full: OUT std_logic); end component; -attribute box_type of xilinx_fifo_18x1k : component is "black_box"; +-- attribute box_type of xilinx_fifo_18x1k : component is "black_box"; component xilinx_fifo_18x16 @@ -56,7 +56,7 @@ attribute box_type of xilinx_fifo_18x1k : component is "black_box"; empty: OUT std_logic ); end component; -attribute box_type of xilinx_fifo_18x16 : component is "black_box"; +-- attribute box_type of xilinx_fifo_18x16 : component is "black_box"; component xilinx_fifo_18x32 port ( @@ -70,7 +70,7 @@ attribute box_type of xilinx_fifo_18x16 : component is "black_box"; empty: OUT std_logic ); end component; -attribute box_type of xilinx_fifo_18x32 : component is "black_box"; +-- attribute box_type of xilinx_fifo_18x32 : component is "black_box"; component xilinx_fifo_18x64 port ( @@ -84,7 +84,7 @@ attribute box_type of xilinx_fifo_18x32 : component is "black_box"; empty: OUT std_logic ); end component; -attribute box_type of xilinx_fifo_18x64 : component is "black_box"; +-- attribute box_type of xilinx_fifo_18x64 : component is "black_box"; component xilinx_fifo_lut generic ( @@ -116,7 +116,7 @@ attribute box_type of xilinx_fifo_18x64 : component is "black_box"; full: OUT std_logic ); end component; -attribute box_type of xilinx_fifo_18x1k_datacount : component is "black_box"; +-- attribute box_type of xilinx_fifo_18x1k_datacount : component is "black_box"; signal din, dout : std_logic_vector(c_DATA_WIDTH + 2-1 downto 0); signal data_counter : std_logic_vector(9 downto 0); diff --git a/xilinx/virtex4/xilinx_fifo_18x1k.vhd b/xilinx/virtex4/xilinx_fifo_18x1k.vhd index a00c341..dd7c698 100644 --- a/xilinx/virtex4/xilinx_fifo_18x1k.vhd +++ b/xilinx/virtex4/xilinx_fifo_18x1k.vhd @@ -66,7 +66,7 @@ component wrapped_xilinx_fifo_18x1k full: OUT std_logic); end component; --- Configuration specification +-- Configuration specification for all : wrapped_xilinx_fifo_18x1k use entity XilinxCoreLib.fifo_generator_v4_2(behavioral) generic map( c_has_int_clk => 0, diff --git a/xilinx/virtex4/xilinx_fifo_18x1k.xco b/xilinx/virtex4/xilinx_fifo_18x1k.xco index 0063e9f..a3e70d8 100644 --- a/xilinx/virtex4/xilinx_fifo_18x1k.xco +++ b/xilinx/virtex4/xilinx_fifo_18x1k.xco @@ -1,7 +1,7 @@ ############################################################## # # Xilinx Core Generator version J.40 -# Date: Mon Feb 25 11:08:40 2008 +# Date: Fri Mar 27 16:40:59 2009 # ############################################################## # @@ -41,14 +41,14 @@ CSET component_name=xilinx_fifo_18x1k CSET data_count=false CSET data_count_width=10 CSET dout_reset_value=0 -CSET empty_threshold_assert_value=19 -CSET empty_threshold_negate_value=20 +CSET empty_threshold_assert_value=2 +CSET empty_threshold_negate_value=3 CSET enable_ecc=false CSET enable_int_clk=false -CSET fifo_implementation=Common_Clock_Builtin_FIFO -CSET full_flags_reset_value=0 -CSET full_threshold_assert_value=1035 -CSET full_threshold_negate_value=1034 +CSET fifo_implementation=Common_Clock_Block_RAM +CSET full_flags_reset_value=1 +CSET full_threshold_assert_value=1022 +CSET full_threshold_negate_value=1021 CSET input_data_width=18 CSET input_depth=1024 CSET output_data_width=18 @@ -77,5 +77,5 @@ CSET write_data_count=false CSET write_data_count_width=10 # END Parameters GENERATE -# CRC: fa82e1b6 +# CRC: 54ceecf2