From: Jan Michel Date: Thu, 11 Aug 2022 08:09:46 +0000 (+0200) Subject: GbE: X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=9c011b9186de656afdc6f3af53f4c5008464e755;p=trbnet.git GbE: add missing memory make ECP5 / ECP3 gbe_wrapper compatible change MAC generation for I2C UIDs make endpoint with GbE compatible with ECP5 --- diff --git a/gbe_trb/ipcores/ecp5/ip_mem.vhd b/gbe_trb/ipcores/ecp5/ip_mem.vhd new file mode 100644 index 0000000..4c724e3 --- /dev/null +++ b/gbe_trb/ipcores/ecp5/ip_mem.vhd @@ -0,0 +1,266 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 +-- Module Version: 7.5 +--/d/jspc29/lattice/diamond/3.12/ispfpga/bin/lin64/scuba -w -n ip_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type bram -wp 11 -rp 1010 -data_width 32 -rdata_width 32 -num_rows 256 -outdataB REGISTERED -cascade -1 -resetmode SYNC -sync_reset -mem_init0 -writemodeA NORMAL -writemodeB NORMAL + +-- Tue Aug 9 14:03:12 2022 + +library IEEE; +use IEEE.std_logic_1164.all; +library ecp5um; +use ecp5um.components.all; + +entity ip_mem is + port ( + DataInA: in std_logic_vector(31 downto 0); + DataInB: in std_logic_vector(31 downto 0); + AddressA: in std_logic_vector(7 downto 0); + AddressB: in std_logic_vector(7 downto 0); + ClockA: in std_logic; + ClockB: in std_logic; + ClockEnA: in std_logic; + ClockEnB: in std_logic; + WrA: in std_logic; + WrB: in std_logic; + ResetA: in std_logic; + ResetB: in std_logic; + QA: out std_logic_vector(31 downto 0); + QB: out std_logic_vector(31 downto 0)); +end ip_mem; + +architecture Structure of ip_mem is + + -- internal signal declarations + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute MEM_LPC_FILE of ip_mem_0_0_1 : label is "ip_mem.lpc"; + attribute MEM_INIT_FILE of ip_mem_0_0_1 : label is "ip_mem.mem"; + attribute MEM_LPC_FILE of ip_mem_0_1_0 : label is "ip_mem.lpc"; + attribute MEM_INIT_FILE of ip_mem_0_1_0 : label is "ip_mem.mem"; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + ip_mem_0_0_1: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0F=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_0E=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_0D=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_0C=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_0B=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_0A=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_09=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_08=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_07=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_06=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_05=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_04=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_03=> "0x00000000000000000000000000000000000005780C35000008000133DC030C353000020001B397E9", + INITVAL_02=> "0x00000000000000000000000000000000000005780C35000007000133DC020C352000020001B397E9", + INITVAL_01=> "0x00000000000000000000000000000000000005780C35000006000133DC010C351000020001B397E9", + INITVAL_00=> "0x00000000000000000000000000000000000005780C35000005000133DC000C350000020001B397E9", + CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18, + DATA_WIDTH_A=> 18) + port map (DIA17=>DataInA(17), DIA16=>DataInA(16), + DIA15=>DataInA(15), DIA14=>DataInA(14), DIA13=>DataInA(13), + DIA12=>DataInA(12), DIA11=>DataInA(11), DIA10=>DataInA(10), + DIA9=>DataInA(9), DIA8=>DataInA(8), DIA7=>DataInA(7), + DIA6=>DataInA(6), DIA5=>DataInA(5), DIA4=>DataInA(4), + DIA3=>DataInA(3), DIA2=>DataInA(2), DIA1=>DataInA(1), + DIA0=>DataInA(0), ADA13=>scuba_vlo, ADA12=>scuba_vlo, + ADA11=>AddressA(7), ADA10=>AddressA(6), ADA9=>AddressA(5), + ADA8=>AddressA(4), ADA7=>AddressA(3), ADA6=>AddressA(2), + ADA5=>AddressA(1), ADA4=>AddressA(0), ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>ClockEnA, OCEA=>ClockEnA, CLKA=>ClockA, WEA=>WrA, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>scuba_vlo, + RSTA=>ResetA, DIB17=>DataInB(17), DIB16=>DataInB(16), + DIB15=>DataInB(15), DIB14=>DataInB(14), DIB13=>DataInB(13), + DIB12=>DataInB(12), DIB11=>DataInB(11), DIB10=>DataInB(10), + DIB9=>DataInB(9), DIB8=>DataInB(8), DIB7=>DataInB(7), + DIB6=>DataInB(6), DIB5=>DataInB(5), DIB4=>DataInB(4), + DIB3=>DataInB(3), DIB2=>DataInB(2), DIB1=>DataInB(1), + DIB0=>DataInB(0), ADB13=>scuba_vlo, ADB12=>scuba_vlo, + ADB11=>AddressB(7), ADB10=>AddressB(6), ADB9=>AddressB(5), + ADB8=>AddressB(4), ADB7=>AddressB(3), ADB6=>AddressB(2), + ADB5=>AddressB(1), ADB4=>AddressB(0), ADB3=>scuba_vlo, + ADB2=>scuba_vlo, ADB1=>scuba_vhi, ADB0=>scuba_vhi, + CEB=>ClockEnB, OCEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>scuba_vlo, + RSTB=>ResetB, DOA17=>QA(17), DOA16=>QA(16), DOA15=>QA(15), + DOA14=>QA(14), DOA13=>QA(13), DOA12=>QA(12), DOA11=>QA(11), + DOA10=>QA(10), DOA9=>QA(9), DOA8=>QA(8), DOA7=>QA(7), + DOA6=>QA(6), DOA5=>QA(5), DOA4=>QA(4), DOA3=>QA(3), + DOA2=>QA(2), DOA1=>QA(1), DOA0=>QA(0), DOB17=>QB(17), + DOB16=>QB(16), DOB15=>QB(15), DOB14=>QB(14), DOB13=>QB(13), + DOB12=>QB(12), DOB11=>QB(11), DOB10=>QB(10), DOB9=>QB(9), + DOB8=>QB(8), DOB7=>QB(7), DOB6=>QB(6), DOB5=>QB(5), + DOB4=>QB(4), DOB3=>QB(3), DOB2=>QB(2), DOB1=>QB(1), + DOB0=>QB(0)); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + ip_mem_0_1_0: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_09=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_08=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_07=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_06=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_05=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_04=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_03=> "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850", + INITVAL_02=> "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850", + INITVAL_01=> "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850", + INITVAL_00=> "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850", + CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18, + DATA_WIDTH_A=> 18) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>DataInA(31), DIA12=>DataInA(30), + DIA11=>DataInA(29), DIA10=>DataInA(28), DIA9=>DataInA(27), + DIA8=>DataInA(26), DIA7=>DataInA(25), DIA6=>DataInA(24), + DIA5=>DataInA(23), DIA4=>DataInA(22), DIA3=>DataInA(21), + DIA2=>DataInA(20), DIA1=>DataInA(19), DIA0=>DataInA(18), + ADA13=>scuba_vlo, ADA12=>scuba_vlo, ADA11=>AddressA(7), + ADA10=>AddressA(6), ADA9=>AddressA(5), ADA8=>AddressA(4), + ADA7=>AddressA(3), ADA6=>AddressA(2), ADA5=>AddressA(1), + ADA4=>AddressA(0), ADA3=>scuba_vlo, ADA2=>scuba_vlo, + ADA1=>scuba_vhi, ADA0=>scuba_vhi, CEA=>ClockEnA, + OCEA=>ClockEnA, CLKA=>ClockA, WEA=>WrA, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>scuba_vlo, RSTA=>ResetA, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>DataInB(31), DIB12=>DataInB(30), + DIB11=>DataInB(29), DIB10=>DataInB(28), DIB9=>DataInB(27), + DIB8=>DataInB(26), DIB7=>DataInB(25), DIB6=>DataInB(24), + DIB5=>DataInB(23), DIB4=>DataInB(22), DIB3=>DataInB(21), + DIB2=>DataInB(20), DIB1=>DataInB(19), DIB0=>DataInB(18), + ADB13=>scuba_vlo, ADB12=>scuba_vlo, ADB11=>AddressB(7), + ADB10=>AddressB(6), ADB9=>AddressB(5), ADB8=>AddressB(4), + ADB7=>AddressB(3), ADB6=>AddressB(2), ADB5=>AddressB(1), + ADB4=>AddressB(0), ADB3=>scuba_vlo, ADB2=>scuba_vlo, + ADB1=>scuba_vhi, ADB0=>scuba_vhi, CEB=>ClockEnB, + OCEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, CSB2=>scuba_vlo, + CSB1=>scuba_vlo, CSB0=>scuba_vlo, RSTB=>ResetB, DOA17=>open, + DOA16=>open, DOA15=>open, DOA14=>open, DOA13=>QA(31), + DOA12=>QA(30), DOA11=>QA(29), DOA10=>QA(28), DOA9=>QA(27), + DOA8=>QA(26), DOA7=>QA(25), DOA6=>QA(24), DOA5=>QA(23), + DOA4=>QA(22), DOA3=>QA(21), DOA2=>QA(20), DOA1=>QA(19), + DOA0=>QA(18), DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>QB(31), DOB12=>QB(30), DOB11=>QB(29), + DOB10=>QB(28), DOB9=>QB(27), DOB8=>QB(26), DOB7=>QB(25), + DOB6=>QB(24), DOB5=>QB(23), DOB4=>QB(22), DOB3=>QB(21), + DOB2=>QB(20), DOB1=>QB(19), DOB0=>QB(18)); + +end Structure; diff --git a/gbe_trb_ecp5/base/gbe_wrapper.vhd b/gbe_trb_ecp5/base/gbe_wrapper.vhd index d6646b8..5b45ed3 100644 --- a/gbe_trb_ecp5/base/gbe_wrapper.vhd +++ b/gbe_trb_ecp5/base/gbe_wrapper.vhd @@ -25,7 +25,7 @@ entity gbe_wrapper is UP_DOWN_MODE : integer range 0 to 1 := 0; -- only for debugging UP_DOWN_LIMIT : integer range 0 to 16777215 := 0; -- only for debugging FIXED_DELAY : integer range 0 to 16777215 := 16777215; -- only for debugging - NUMBER_OF_GBE_LINKS : integer range 1 to 4 := 4; + NUMBER_OF_GBE_LINKS : integer range 1 to 4 := 1; --can't be changed LINKS_ACTIVE : std_logic_vector(3 downto 0) := "1111"; LINK_HAS_PING : std_logic_vector(3 downto 0) := "1111"; LINK_HAS_ARP : std_logic_vector(3 downto 0) := "1111"; @@ -234,8 +234,13 @@ begin -- debug(63 downto 0) are media interface DEBUG_OUT <= debug; - mac_0 <= MC_UNIQUE_ID_IN(15 downto 8) & MC_UNIQUE_ID_IN(23 downto 16) & MC_UNIQUE_ID_IN(31 downto 24) & x"0" & MC_UNIQUE_ID_IN(35 downto 32) & x"7ada"; + --for 1-wire devices + --mac_0 <= MC_UNIQUE_ID_IN(15 downto 8) & MC_UNIQUE_ID_IN(23 downto 16) & MC_UNIQUE_ID_IN(31 downto 24) & x"0" & MC_UNIQUE_ID_IN(35 downto 32) & x"7ada"; + --for I2C devices + mac_0 <= MC_UNIQUE_ID_IN(23 downto 16) & MC_UNIQUE_ID_IN(31 downto 24) & MC_UNIQUE_ID_IN(39 downto 32) & MC_UNIQUE_ID_IN(47 downto 40) & x"1ada"; + + all_links_ready <= '1' when dhcp_done = '1' else '0'; MAKE_RESET_OUT <= '1' when make_reset0 = '1' else '0'; diff --git a/gbe_trb_ecp5/base/gbe_wrapper_single.vhd b/gbe_trb_ecp5/base/gbe_wrapper_single.vhd deleted file mode 100644 index d6646b8..0000000 --- a/gbe_trb_ecp5/base/gbe_wrapper_single.vhd +++ /dev/null @@ -1,720 +0,0 @@ -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_ARITH.all; -use IEEE.std_logic_UNSIGNED.all; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; - -use work.trb_net_gbe_components.all; -use work.trb_net_gbe_protocols.all; - - -entity gbe_wrapper is - generic( - DO_SIMULATION : integer range 0 to 1 := 0; - INCLUDE_DEBUG : integer range 0 to 1 := 0; - USE_INTERNAL_TRBNET_DUMMY : integer range 0 to 1 := 0; -- only for debugging - USE_EXTERNAL_TRBNET_DUMMY : integer range 0 to 1 := 0; -- only for debugging - RX_PATH_ENABLE : integer range 0 to 1 := 1; -- - FIXED_SIZE_MODE : integer range 0 to 1 := 1; -- only for debugging - INCREMENTAL_MODE : integer range 0 to 1 := 0; -- only for debugging - FIXED_SIZE : integer range 0 to 65535 := 10; -- only for debugging - FIXED_DELAY_MODE : integer range 0 to 1 := 1; -- only for debugging - UP_DOWN_MODE : integer range 0 to 1 := 0; -- only for debugging - UP_DOWN_LIMIT : integer range 0 to 16777215 := 0; -- only for debugging - FIXED_DELAY : integer range 0 to 16777215 := 16777215; -- only for debugging - NUMBER_OF_GBE_LINKS : integer range 1 to 4 := 4; - LINKS_ACTIVE : std_logic_vector(3 downto 0) := "1111"; - LINK_HAS_PING : std_logic_vector(3 downto 0) := "1111"; - LINK_HAS_ARP : std_logic_vector(3 downto 0) := "1111"; - LINK_HAS_DHCP : std_logic_vector(3 downto 0) := "1111"; - LINK_HAS_READOUT : std_logic_vector(3 downto 0) := "1111"; - LINK_HAS_SLOWCTRL : std_logic_vector(3 downto 0) := "1111"; - LINK_HAS_FWD : std_logic_vector(3 downto 0) := "1111" - ); - port( - CLK_SYS_IN : in std_logic; - CLK_125_IN : in std_logic; - RESET : in std_logic; - GSR_N : in std_logic; - SD_PRSNT_N_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); - SD_LOS_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); -- SFP Loss Of Signal ('0' = OK, '1' = no signal) - SD_TXDIS_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); -- SFP disable - -- - TRIGGER_IN : in std_logic; -- for debug purpose only - -- CTS interface - CTS_NUMBER_IN : in std_logic_vector(15 downto 0) := (others => '0'); - CTS_CODE_IN : in std_logic_vector(7 downto 0) := (others => '0'); - CTS_INFORMATION_IN : in std_logic_vector(7 downto 0) := (others => '0'); - CTS_READOUT_TYPE_IN : in std_logic_vector(3 downto 0) := (others => '0'); - CTS_START_READOUT_IN : in std_logic := '0'; - CTS_DATA_OUT : out std_logic_vector(31 downto 0); - CTS_DATAREADY_OUT : out std_logic; - CTS_READOUT_FINISHED_OUT : out std_logic; - CTS_READ_IN : in std_logic := '0'; - CTS_LENGTH_OUT : out std_logic_vector(15 downto 0); - CTS_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); - -- Data payload interface - FEE_DATA_IN : in std_logic_vector(15 downto 0) := (others => '0'); - FEE_DATAREADY_IN : in std_logic := '0'; - FEE_READ_OUT : out std_logic; - FEE_STATUS_BITS_IN : in std_logic_vector(31 downto 0) := (others => '0'); - FEE_BUSY_IN : in std_logic := '0'; - -- SlowControl - MY_TRBNET_ADDRESS_IN : in std_logic_vector(15 downto 0); - ISSUE_REBOOT_OUT : out std_logic; - MC_UNIQUE_ID_IN : in std_logic_vector(63 downto 0); - GSC_CLK_IN : in std_logic; - GSC_INIT_DATAREADY_OUT : out std_logic; - GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0); - GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); - GSC_INIT_READ_IN : in std_logic; - GSC_REPLY_DATAREADY_IN : in std_logic; - GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0); - GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0); - GSC_REPLY_READ_OUT : out std_logic; - GSC_BUSY_IN : in std_logic; - -- IP configuration - BUS_IP_RX : in CTRLBUS_RX; - BUS_IP_TX : out CTRLBUS_TX; - -- Registers config - BUS_REG_RX : in CTRLBUS_RX; - BUS_REG_TX : out CTRLBUS_TX; - -- Forwarder - FWD_DST_MAC_IN : in std_logic_vector(48 * NUMBER_OF_GBE_LINKS - 1 downto 0) := (others => '0'); - FWD_DST_IP_IN : in std_logic_vector(32 * NUMBER_OF_GBE_LINKS - 1 downto 0) := (others => '0'); - FWD_DST_UDP_IN : in std_logic_vector(16 * NUMBER_OF_GBE_LINKS - 1 downto 0) := (others => '0'); - FWD_DATA_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0) := (others => '0'); - FWD_DATA_VALID_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0) := (others => '0'); - FWD_SOP_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0) := (others => '0'); - FWD_EOP_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0) := (others => '0'); - FWD_READY_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); - FWD_FULL_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); - -- - MAKE_RESET_OUT : out std_logic; - -- - STATUS_OUT : out std_logic_vector(15 downto 0); - DEBUG_OUT : out std_logic_vector(127 downto 0) - ); -end entity gbe_wrapper; - -architecture RTL of gbe_wrapper is - signal mac_ready_conf : std_logic; - signal mac_reconf : std_logic; - signal mac_an_ready : std_logic; - signal mac_fifoavail : std_logic; - signal mac_fifoeof : std_logic; - signal mac_fifoempty : std_logic; - signal mac_rx_fifofull : std_logic; - signal mac_tx_data : std_logic_vector(7 downto 0); - signal mac_tx_read : std_logic; - signal mac_tx_discrfrm : std_logic; - signal mac_tx_stat_en : std_logic; - signal mac_tx_stats : std_logic_vector(30 downto 0); - signal mac_tx_done : std_logic; - signal mac_rx_fifo_err : std_logic; - signal mac_rx_stats : std_logic_vector(31 downto 0); - signal mac_rx_data : std_logic_vector(7 downto 0); - signal mac_rx_write : std_logic; - signal mac_rx_stat_en : std_logic; - signal mac_rx_eof : std_logic; - signal mac_rx_err : std_logic; - - signal cfg_gbe_enable : std_logic; - signal cfg_ipu_enable : std_logic; - signal cfg_mult_enable : std_logic; - signal cfg_subevent_id : std_logic_vector(31 downto 0); - signal cfg_subevent_dec : std_logic_vector(31 downto 0); - signal cfg_queue_dec : std_logic_vector(31 downto 0); - signal cfg_readout_ctr : std_logic_vector(23 downto 0); - signal cfg_readout_ctr_valid : std_logic; - signal cfg_insert_ttype : std_logic; - signal cfg_max_sub : std_logic_vector(15 downto 0); - signal cfg_max_queue : std_logic_vector(15 downto 0); - signal cfg_max_subs_in_queue : std_logic_vector(15 downto 0); - signal cfg_max_single_sub : std_logic_vector(15 downto 0); - signal cfg_additional_hdr : std_logic; - signal cfg_soft_rst : std_logic; - signal cfg_allow_rx : std_logic; - signal cfg_max_frame : std_logic_vector(15 downto 0); - - signal dbg_hist, dbg_hist2 : hist_array; - - signal mac_0 : std_logic_vector(47 downto 0); - signal cfg_max_reply : std_logic_vector(31 downto 0); - - signal mlt_cts_number : std_logic_vector(15 downto 0); - signal mlt_cts_code : std_logic_vector(7 downto 0); - signal mlt_cts_information : std_logic_vector(7 downto 0); - signal mlt_cts_readout_type : std_logic_vector(3 downto 0); - signal mlt_cts_start_readout : std_logic_vector(0 downto 0); - signal mlt_cts_data : std_logic_vector(31 downto 0); - signal mlt_cts_dataready : std_logic_vector(0 downto 0); - signal mlt_cts_readout_finished : std_logic_vector(0 downto 0); - signal mlt_cts_read : std_logic_vector(0 downto 0); - signal mlt_cts_length : std_logic_vector(15 downto 0); - signal mlt_cts_error_pattern : std_logic_vector(31 downto 0); - signal mlt_fee_data : std_logic_vector(15 downto 0); - signal mlt_fee_dataready : std_logic_vector(0 downto 0); - signal mlt_fee_read : std_logic_vector(0 downto 0); - signal mlt_fee_status : std_logic_vector(31 downto 0); - signal mlt_fee_busy : std_logic_vector(0 downto 0); - - signal mlt_gsc_clk : std_logic; - signal mlt_gsc_init_dataready : std_logic; - signal mlt_gsc_init_data : std_logic_vector(15 downto 0); - signal mlt_gsc_init_packet : std_logic_vector(2 downto 0); - signal mlt_gsc_init_read : std_logic; - signal mlt_gsc_reply_dataready : std_logic; - signal mlt_gsc_reply_data : std_logic_vector(15 downto 0); - signal mlt_gsc_reply_packet : std_logic_vector(2 downto 0); - signal mlt_gsc_reply_read : std_logic; - signal mlt_gsc_busy : std_logic; - - signal local_cts_number : std_logic_vector(15 downto 0); - signal local_cts_code : std_logic_vector(7 downto 0); - signal local_cts_information : std_logic_vector(7 downto 0); - signal local_cts_readout_type : std_logic_vector(3 downto 0); - signal local_cts_start_readout : std_logic; - signal local_cts_readout_finished : std_logic; - signal local_cts_status_bits : std_logic_vector(31 downto 0); - signal local_fee_data : std_logic_vector(15 downto 0); - signal local_fee_dataready : std_logic; - signal local_fee_read : std_logic; - signal local_fee_status_bits : std_logic_vector(31 downto 0); - signal local_fee_busy : std_logic; - signal dhcp_done : std_logic; - signal all_links_ready : std_logic; - signal monitor_rx_frames : std_logic_vector(31 downto 0); - signal monitor_rx_bytes : std_logic_vector(31 downto 0); - signal monitor_tx_frames : std_logic_vector(31 downto 0); - signal monitor_tx_bytes : std_logic_vector(31 downto 0); - signal monitor_tx_packets : std_logic_vector(31 downto 0); - signal monitor_dropped : std_logic_vector(31 downto 0); - signal sum_rx_frames : std_logic_vector(31 downto 0); - signal sum_rx_bytes : std_logic_vector(31 downto 0); - signal sum_tx_frames : std_logic_vector(31 downto 0); - signal sum_tx_bytes : std_logic_vector(31 downto 0); - signal sum_tx_packets : std_logic_vector(31 downto 0); - signal sum_dropped : std_logic_vector(31 downto 0); - - signal busip0 : CTRLBUS_TX; - signal SD_RXD_P_IN, SD_RXD_N_IN, SD_TXD_P_OUT, SD_TXD_N_OUT : std_logic; - --attribute nopad : string; - --attribute nopad of SD_RXD_P_IN, SD_RXD_N_IN, SD_TXD_P_OUT, SD_TXD_N_OUT : signal is "true"; - - signal dummy_event : std_logic_vector(15 downto 0); - signal dummy_mode : std_logic; - signal make_reset0 : std_logic := '0'; - signal monitor_gen_dbg : std_logic_vector(c_MAX_PROTOCOLS * 64 - 1 downto 0); - - signal cfg_autothrottle : std_logic; - signal cfg_throttle_pause : std_logic_vector(15 downto 0); - - signal issue_reboot : std_logic; - signal my_ip : std_logic_vector(127 downto 0); - signal debug : std_logic_vector(127 downto 0); - -begin - --- assert hits if condition in brackets is true, or overall condition is false - - assert not (NUMBER_OF_GBE_LINKS /= 1) report "Error: only one GbE link allowed" severity error; - assert not (LINKS_ACTIVE /= b"0001") report "Error: no / wrong GbE interface selected" severity error; - assert not (LINK_HAS_PING(3 downto 1) /= b"000") report "Error: only interface 0 supported" severity error; - assert not (LINK_HAS_ARP(3 downto 1) /= b"000") report "Error: only interface 0 supported" severity error; - assert not (LINK_HAS_DHCP(3 downto 1) /= b"000") report "Error: only interface 0 supported" severity error; - assert not (LINK_HAS_READOUT(3 downto 1) /= b"000") report "Error: only interface 0 supported" severity error; - assert not (LINK_HAS_SLOWCTRL(3 downto 1) /= b"000") report "Error: only interface 0 supported" severity error; - assert not (LINK_HAS_FWD(3 downto 1) /= b"000") report "Error: only interface 0 supported" severity error; - - -- debug(127 downto 64) are local - -- debug(63 downto 0) are media interface - DEBUG_OUT <= debug; - - mac_0 <= MC_UNIQUE_ID_IN(15 downto 8) & MC_UNIQUE_ID_IN(23 downto 16) & MC_UNIQUE_ID_IN(31 downto 24) & x"0" & MC_UNIQUE_ID_IN(35 downto 32) & x"7ada"; - - all_links_ready <= '1' when dhcp_done = '1' else '0'; - - MAKE_RESET_OUT <= '1' when make_reset0 = '1' else '0'; - - ISSUE_REBOOT_OUT <= '0' when issue_reboot = '0' else '1'; - - physical : entity work.gbe_med_interface_single - port map( - RESET => RESET, - GSR_N => GSR_N, - CLK_SYS_IN => CLK_SYS_IN, - CLK_125_OUT => open, -- not needed - CLK_125_IN => CLK_125_IN, - CLK_125_RX_OUT => open, -- not needed - MAC_READY_CONF_OUT => mac_ready_conf, - MAC_RECONF_IN => mac_reconf, - MAC_AN_READY_OUT => mac_an_ready, - MAC_FIFOAVAIL_IN => mac_fifoavail, - MAC_FIFOEOF_IN => mac_fifoeof, - MAC_FIFOEMPTY_IN => mac_fifoempty, - MAC_RX_FIFOFULL_IN => mac_rx_fifofull, - MAC_TX_DATA_IN => mac_tx_data, - MAC_TX_READ_OUT => mac_tx_read, - MAC_TX_DISCRFRM_OUT => mac_tx_discrfrm, - MAC_TX_STAT_EN_OUT => mac_tx_stat_en, - MAC_TX_STATS_OUT => mac_tx_stats, - MAC_TX_DONE_OUT => mac_tx_done, - MAC_RX_FIFO_ERR_OUT => mac_rx_fifo_err, - MAC_RX_STATS_OUT => mac_rx_stats, - MAC_RX_DATA_OUT => mac_rx_data, - MAC_RX_WRITE_OUT => mac_rx_write, - MAC_RX_STAT_EN_OUT => mac_rx_stat_en, - MAC_RX_EOF_OUT => mac_rx_eof, - MAC_RX_ERROR_OUT => mac_rx_err, - SD_RXD_P_IN => SD_RXD_P_IN, - SD_RXD_N_IN => SD_RXD_N_IN, - SD_TXD_P_OUT => SD_TXD_P_OUT, - SD_TXD_N_OUT => SD_TXD_N_OUT, - SD_PRSNT_N_IN => SD_PRSNT_N_IN(0), - SD_LOS_IN => SD_LOS_IN(0), - SD_TXDIS_OUT => SD_TXDIS_OUT(0), - STATUS_OUT => STATUS_OUT(7 downto 0), - DEBUG_OUT => debug(63 downto 0) --open - ); - --- -- "Good" debugging pins --- debug(7 downto 0) <= mac_rx_data; --- debug(15 downto 8) <= mac_tx_data; --- debug(16) <= mac_rx_write; --- debug(17) <= mac_tx_read; --- debug(18) <= mac_rx_eof; --- debug(19) <= mac_fifoeof; --- -- "Bad" debugging pins --- debug(20) <= mac_fifoempty; --- debug(21) <= mac_fifoavail; --- debug(22) <= mac_tx_discrfrm; --- debug(23) <= mac_rx_fifo_err; --- debug(24) <= mac_rx_fifofull; --- debug(25) <= mac_rx_err; --- debug(26) <= mac_tx_done; --- debug(27) <= mac_an_ready; --- debug(28) <= mac_ready_conf; --- debug(29) <= mac_reconf; --- debug(30) <= '0'; --- debug(31) <= '0'; --- debug(32) <= '0'; --- debug(33) <= '0'; - - STATUS_OUT(8) <= dhcp_done; -- DHCP has completed - STATUS_OUT(15 downto 9) <= (others => '0'); - - gbe_inst : entity work.gbe_logic_wrapper - generic map(DO_SIMULATION => DO_SIMULATION, - INCLUDE_DEBUG => INCLUDE_DEBUG, - USE_INTERNAL_TRBNET_DUMMY => USE_INTERNAL_TRBNET_DUMMY, - RX_PATH_ENABLE => RX_PATH_ENABLE, - INCLUDE_READOUT => LINK_HAS_READOUT(0), - INCLUDE_SLOWCTRL => LINK_HAS_SLOWCTRL(0), - INCLUDE_DHCP => LINK_HAS_DHCP(0), - INCLUDE_ARP => LINK_HAS_ARP(0), - INCLUDE_PING => LINK_HAS_PING(0), - INCLUDE_FWD => LINK_HAS_FWD(0), - FRAME_BUFFER_SIZE => 1, - READOUT_BUFFER_SIZE => 4, - SLOWCTRL_BUFFER_SIZE => 2, - FIXED_SIZE_MODE => FIXED_SIZE_MODE, - INCREMENTAL_MODE => INCREMENTAL_MODE, - FIXED_SIZE => FIXED_SIZE, - FIXED_DELAY_MODE => FIXED_DELAY_MODE, - UP_DOWN_MODE => UP_DOWN_MODE, - UP_DOWN_LIMIT => UP_DOWN_LIMIT, - FIXED_DELAY => FIXED_DELAY) - port map( - CLK_SYS_IN => CLK_SYS_IN, - CLK_125_IN => CLK_125_IN, - CLK_RX_125_IN => CLK_125_IN, - RESET => RESET, - GSR_N => GSR_N, - MY_MAC_IN => mac_0, - DHCP_DONE_OUT => dhcp_done, - MY_IP_OUT => my_ip(31 downto 0), - MY_TRBNET_ADDRESS_IN => MY_TRBNET_ADDRESS_IN, - ISSUE_REBOOT_OUT => issue_reboot, - MAC_READY_CONF_IN => mac_ready_conf, - MAC_RECONF_OUT => mac_reconf, - MAC_AN_READY_IN => mac_an_ready, - MAC_FIFOAVAIL_OUT => mac_fifoavail, - MAC_FIFOEOF_OUT => mac_fifoeof, - MAC_FIFOEMPTY_OUT => mac_fifoempty, - MAC_RX_FIFOFULL_OUT => mac_rx_fifofull, - MAC_TX_DATA_OUT => mac_tx_data, - MAC_TX_READ_IN => mac_tx_read, - MAC_TX_DISCRFRM_IN => mac_tx_discrfrm, - MAC_TX_STAT_EN_IN => mac_tx_stat_en, - MAC_TX_STATS_IN => mac_tx_stats, - MAC_TX_DONE_IN => mac_tx_done, - MAC_RX_FIFO_ERR_IN => mac_rx_fifo_err, - MAC_RX_STATS_IN => mac_rx_stats, - MAC_RX_DATA_IN => mac_rx_data, - MAC_RX_WRITE_IN => mac_rx_write, - MAC_RX_STAT_EN_IN => mac_rx_stat_en, - MAC_RX_EOF_IN => mac_rx_eof, - MAC_RX_ERROR_IN => mac_rx_err, - CTS_NUMBER_IN => mlt_cts_number, - CTS_CODE_IN => mlt_cts_code, - CTS_INFORMATION_IN => mlt_cts_information, - CTS_READOUT_TYPE_IN => mlt_cts_readout_type, - CTS_START_READOUT_IN => mlt_cts_start_readout(0), - CTS_DATA_OUT => mlt_cts_data, - CTS_DATAREADY_OUT => mlt_cts_dataready(0), - CTS_READOUT_FINISHED_OUT => mlt_cts_readout_finished(0), - CTS_READ_IN => mlt_cts_read(0), - CTS_LENGTH_OUT => mlt_cts_length, - CTS_ERROR_PATTERN_OUT => mlt_cts_error_pattern, - FEE_DATA_IN => mlt_fee_data, - FEE_DATAREADY_IN => mlt_fee_dataready(0), - FEE_READ_OUT => mlt_fee_read(0), - FEE_STATUS_BITS_IN => mlt_fee_status, - FEE_BUSY_IN => mlt_fee_busy(0), - GSC_CLK_IN => mlt_gsc_clk, - GSC_INIT_DATAREADY_OUT => mlt_gsc_init_dataready, - GSC_INIT_DATA_OUT => mlt_gsc_init_data, - GSC_INIT_PACKET_NUM_OUT => mlt_gsc_init_packet, - GSC_INIT_READ_IN => mlt_gsc_init_read, - GSC_REPLY_DATAREADY_IN => mlt_gsc_reply_dataready, - GSC_REPLY_DATA_IN => mlt_gsc_reply_data, - GSC_REPLY_PACKET_NUM_IN => mlt_gsc_reply_packet, - GSC_REPLY_READ_OUT => mlt_gsc_reply_read, - GSC_BUSY_IN => mlt_gsc_busy, - SLV_ADDR_IN => BUS_IP_RX.addr(7 downto 0), - SLV_READ_IN => BUS_IP_RX.read, - SLV_WRITE_IN => BUS_IP_RX.write, - SLV_BUSY_OUT => busip0.nack, - SLV_ACK_OUT => busip0.ack, - SLV_DATA_IN => BUS_IP_RX.data, - SLV_DATA_OUT => busip0.data, - CFG_GBE_ENABLE_IN => cfg_gbe_enable, - CFG_IPU_ENABLE_IN => cfg_ipu_enable, - CFG_MULT_ENABLE_IN => cfg_mult_enable, - CFG_MAX_FRAME_IN => cfg_max_frame, - CFG_ALLOW_RX_IN => cfg_allow_rx, - CFG_SOFT_RESET_IN => cfg_soft_rst, - CFG_SUBEVENT_ID_IN => cfg_subevent_id, - CFG_SUBEVENT_DEC_IN => cfg_subevent_dec, - CFG_QUEUE_DEC_IN => cfg_queue_dec, - CFG_READOUT_CTR_IN => cfg_readout_ctr, - CFG_READOUT_CTR_VALID_IN => cfg_readout_ctr_valid, - CFG_INSERT_TTYPE_IN => cfg_insert_ttype, - CFG_MAX_SUB_IN => cfg_max_sub, - CFG_MAX_QUEUE_IN => cfg_max_queue, - CFG_MAX_SUBS_IN_QUEUE_IN => cfg_max_subs_in_queue, - CFG_MAX_SINGLE_SUB_IN => cfg_max_single_sub, - CFG_ADDITIONAL_HDR_IN => cfg_additional_hdr, - CFG_MAX_REPLY_SIZE_IN => cfg_max_reply, - CFG_AUTO_THROTTLE_IN => cfg_autothrottle, - CFG_THROTTLE_PAUSE_IN => cfg_throttle_pause, - FWD_DST_MAC_IN => FWD_DST_MAC_IN(47 downto 0), - FWD_DST_IP_IN => FWD_DST_IP_IN(31 downto 0), - FWD_DST_UDP_IN => FWD_DST_UDP_IN(15 downto 0), - FWD_DATA_IN => FWD_DATA_IN(7 downto 0), - FWD_DATA_VALID_IN => FWD_DATA_VALID_IN(0), - FWD_SOP_IN => FWD_SOP_IN(0), - FWD_EOP_IN => FWD_EOP_IN(0), - FWD_READY_OUT => FWD_READY_OUT(0), - FWD_FULL_OUT => FWD_FULL_OUT(0), - MONITOR_RX_FRAMES_OUT => monitor_rx_frames, - MONITOR_RX_BYTES_OUT => monitor_rx_bytes, - MONITOR_TX_FRAMES_OUT => monitor_tx_frames, - MONITOR_TX_BYTES_OUT => monitor_tx_bytes, - MONITOR_TX_PACKETS_OUT => monitor_tx_packets, - MONITOR_DROPPED_OUT => monitor_dropped, - MONITOR_GEN_DBG_OUT => monitor_gen_dbg, - MAKE_RESET_OUT => make_reset0 - ); - - BUS_IP_TX.ack <= busip0.ack when rising_edge(CLK_SYS_IN); - BUS_IP_TX.nack <= busip0.nack when rising_edge(CLK_SYS_IN); - BUS_IP_TX.data <= busip0.data when rising_edge(CLK_SYS_IN); - - real_ipu_gen : if USE_EXTERNAL_TRBNET_DUMMY = 0 generate - ipu_mult : entity work.gbe_ipu_multiplexer - generic map( - DO_SIMULATION => DO_SIMULATION, - INCLUDE_DEBUG => INCLUDE_DEBUG, - LINK_HAS_READOUT => LINK_HAS_READOUT, - NUMBER_OF_GBE_LINKS => NUMBER_OF_GBE_LINKS - ) - port map( - CLK_SYS_IN => CLK_SYS_IN, - RESET => RESET, - CTS_NUMBER_IN => CTS_NUMBER_IN, - CTS_CODE_IN => CTS_CODE_IN, - CTS_INFORMATION_IN => CTS_INFORMATION_IN, - CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN, - CTS_START_READOUT_IN => CTS_START_READOUT_IN, - CTS_DATA_OUT => CTS_DATA_OUT, - CTS_DATAREADY_OUT => CTS_DATAREADY_OUT, - CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT, - CTS_READ_IN => CTS_READ_IN, - CTS_LENGTH_OUT => CTS_LENGTH_OUT, - CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT, - FEE_DATA_IN => FEE_DATA_IN, - FEE_DATAREADY_IN => FEE_DATAREADY_IN, - FEE_READ_OUT => FEE_READ_OUT, - FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN, - FEE_BUSY_IN => FEE_BUSY_IN, - MLT_CTS_NUMBER_OUT => mlt_cts_number, - MLT_CTS_CODE_OUT => mlt_cts_code, - MLT_CTS_INFORMATION_OUT => mlt_cts_information, - MLT_CTS_READOUT_TYPE_OUT => mlt_cts_readout_type, - MLT_CTS_START_READOUT_OUT => mlt_cts_start_readout, - MLT_CTS_DATA_IN => mlt_cts_data, - MLT_CTS_DATAREADY_IN => mlt_cts_dataready, - MLT_CTS_READOUT_FINISHED_IN => mlt_cts_readout_finished, - MLT_CTS_READ_OUT => mlt_cts_read, - MLT_CTS_LENGTH_IN => mlt_cts_length, - MLT_CTS_ERROR_PATTERN_IN => mlt_cts_error_pattern, - MLT_FEE_DATA_OUT => mlt_fee_data, - MLT_FEE_DATAREADY_OUT => mlt_fee_dataready, - MLT_FEE_READ_IN => mlt_fee_read, - MLT_FEE_STATUS_BITS_OUT => mlt_fee_status, - MLT_FEE_BUSY_OUT => mlt_fee_busy, - DEBUG_OUT => open - ); - end generate real_ipu_gen; - - dummy_ipu_gen : if (USE_EXTERNAL_TRBNET_DUMMY = 1) generate - ipu_mult : entity work.gbe_ipu_multiplexer - generic map( - DO_SIMULATION => DO_SIMULATION, - INCLUDE_DEBUG => INCLUDE_DEBUG, - LINK_HAS_READOUT => LINK_HAS_READOUT, - NUMBER_OF_GBE_LINKS => NUMBER_OF_GBE_LINKS - ) - port map( - CLK_SYS_IN => CLK_SYS_IN, - RESET => RESET, - CTS_NUMBER_IN => local_cts_number, - CTS_CODE_IN => local_cts_code, - CTS_INFORMATION_IN => local_cts_information, - CTS_READOUT_TYPE_IN => local_cts_readout_type, - CTS_START_READOUT_IN => local_cts_start_readout, - CTS_DATA_OUT => open, - CTS_DATAREADY_OUT => open, - CTS_READOUT_FINISHED_OUT => local_cts_readout_finished, - CTS_READ_IN => '1', - CTS_LENGTH_OUT => open, - CTS_ERROR_PATTERN_OUT => local_cts_status_bits, - FEE_DATA_IN => local_fee_data, - FEE_DATAREADY_IN => local_fee_dataready, - FEE_READ_OUT => local_fee_read, - FEE_STATUS_BITS_IN => local_fee_status_bits, - FEE_BUSY_IN => local_fee_busy, - MLT_CTS_NUMBER_OUT => mlt_cts_number, - MLT_CTS_CODE_OUT => mlt_cts_code, - MLT_CTS_INFORMATION_OUT => mlt_cts_information, - MLT_CTS_READOUT_TYPE_OUT => mlt_cts_readout_type, - MLT_CTS_START_READOUT_OUT => mlt_cts_start_readout, - MLT_CTS_DATA_IN => mlt_cts_data, - MLT_CTS_DATAREADY_IN => mlt_cts_dataready, - MLT_CTS_READOUT_FINISHED_IN => mlt_cts_readout_finished, - MLT_CTS_READ_OUT => mlt_cts_read, - MLT_CTS_LENGTH_IN => mlt_cts_length, - MLT_CTS_ERROR_PATTERN_IN => mlt_cts_error_pattern, - MLT_FEE_DATA_OUT => mlt_fee_data, - MLT_FEE_DATAREADY_OUT => mlt_fee_dataready, - MLT_FEE_READ_IN => mlt_fee_read, - MLT_FEE_STATUS_BITS_OUT => mlt_fee_status, - MLT_FEE_BUSY_OUT => mlt_fee_busy, - DEBUG_OUT => open - ); - - dummy : entity work.gbe_ipu_dummy - generic map( - DO_SIMULATION => DO_SIMULATION, - FIXED_SIZE_MODE => FIXED_SIZE_MODE, - INCREMENTAL_MODE => INCREMENTAL_MODE, - FIXED_SIZE => FIXED_SIZE, - UP_DOWN_MODE => UP_DOWN_MODE, - UP_DOWN_LIMIT => UP_DOWN_LIMIT, - FIXED_DELAY_MODE => FIXED_DELAY_MODE, - FIXED_DELAY => FIXED_DELAY - ) - port map( - clk => CLK_SYS_IN, - rst => RESET, - GBE_READY_IN => all_links_ready, - CFG_EVENT_SIZE_IN => dummy_event, - CFG_TRIGGERED_MODE_IN => '0', - TRIGGER_IN => TRIGGER_IN, - CTS_NUMBER_OUT => local_cts_number, - CTS_CODE_OUT => local_cts_code, - CTS_INFORMATION_OUT => local_cts_information, - CTS_READOUT_TYPE_OUT => local_cts_readout_type, - CTS_START_READOUT_OUT => local_cts_start_readout, - CTS_DATA_IN => (others => '0'), - CTS_DATAREADY_IN => '0', - CTS_READOUT_FINISHED_IN => local_cts_readout_finished, - CTS_READ_OUT => open, - CTS_LENGTH_IN => (others => '0'), - CTS_ERROR_PATTERN_IN => local_cts_status_bits, - -- Data payload interface - FEE_DATA_OUT => local_fee_data, - FEE_DATAREADY_OUT => local_fee_dataready, - FEE_READ_IN => local_fee_read, - FEE_STATUS_BITS_OUT => local_fee_status_bits, - FEE_BUSY_OUT => local_fee_busy - ); - - -- handler for triggers - DUMMY_HANDLER : entity work.trb_net16_gbe_ipu_interface - port map( - CLK_IPU => CLK_SYS_IN, - CLK_GBE => CLK_125_IN, - RESET => RESET, - --Event information coming from CTS - CTS_NUMBER_IN => CTS_NUMBER_IN, - CTS_CODE_IN => CTS_CODE_IN, - CTS_INFORMATION_IN => CTS_INFORMATION_IN, - CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN, - CTS_START_READOUT_IN => CTS_START_READOUT_IN, - --Information sent to CTS - --status data, equipped with DHDR - CTS_DATA_OUT => CTS_DATA_OUT, - CTS_DATAREADY_OUT => CTS_DATAREADY_OUT, - CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT, - CTS_READ_IN => CTS_READ_IN, - CTS_LENGTH_OUT => CTS_LENGTH_OUT, - CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT, - -- Data from Frontends - FEE_DATA_IN => FEE_DATA_IN, - FEE_DATAREADY_IN => FEE_DATAREADY_IN, - FEE_READ_OUT => FEE_READ_OUT, - FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN, - FEE_BUSY_IN => FEE_BUSY_IN, - -- slow control interface - START_CONFIG_OUT => open, - BANK_SELECT_OUT => open, - CONFIG_DONE_IN => '1', - DATA_GBE_ENABLE_IN => '1', - DATA_IPU_ENABLE_IN => '1', - MULT_EVT_ENABLE_IN => '1', - MAX_SUBEVENT_SIZE_IN => (others => '0'), - MAX_QUEUE_SIZE_IN => (others => '0'), - MAX_SUBS_IN_QUEUE_IN => (others => '0'), - MAX_SINGLE_SUB_SIZE_IN => (others => '0'), - READOUT_CTR_IN => (others => '0'), - READOUT_CTR_VALID_IN => '0', - CFG_AUTO_THROTTLE_IN => '0', - CFG_THROTTLE_PAUSE_IN => (others => '0'), - -- PacketConstructor interface - PC_WR_EN_OUT => open, - PC_DATA_OUT => open, - PC_READY_IN => '1', - PC_SOS_OUT => open, - PC_EOS_OUT => open, - PC_EOQ_OUT => open, - PC_SUB_SIZE_OUT => open, - PC_TRIG_NR_OUT => open, - PC_TRIGGER_TYPE_OUT => open, - MONITOR_OUT => open, - DEBUG_OUT => open - ); - end generate dummy_ipu_gen; - - SETUP : gbe_setup - port map( - CLK => CLK_SYS_IN, - RESET => RESET, - -- interface to regio bus - BUS_ADDR_IN => BUS_REG_RX.addr(7 downto 0), - BUS_DATA_IN => BUS_REG_RX.data, - BUS_DATA_OUT => BUS_REG_TX.data, - BUS_WRITE_EN_IN => BUS_REG_RX.write, - BUS_READ_EN_IN => BUS_REG_RX.read, - BUS_ACK_OUT => BUS_REG_TX.ack, - -- output to gbe_buf - GBE_SUBEVENT_ID_OUT => cfg_subevent_id, - GBE_SUBEVENT_DEC_OUT => cfg_subevent_dec, - GBE_QUEUE_DEC_OUT => cfg_queue_dec, - GBE_MAX_FRAME_OUT => cfg_max_frame, - GBE_USE_GBE_OUT => cfg_gbe_enable, - GBE_USE_TRBNET_OUT => cfg_ipu_enable, - GBE_USE_MULTIEVENTS_OUT => cfg_mult_enable, - GBE_READOUT_CTR_OUT => cfg_readout_ctr, - GBE_READOUT_CTR_VALID_OUT => cfg_readout_ctr_valid, - GBE_ALLOW_RX_OUT => cfg_allow_rx, - GBE_ADDITIONAL_HDR_OUT => cfg_additional_hdr, - GBE_INSERT_TTYPE_OUT => cfg_insert_ttype, - GBE_SOFT_RESET_OUT => cfg_soft_rst, - GBE_MAX_REPLY_OUT => cfg_max_reply, - GBE_MAX_SUB_OUT => cfg_max_sub, - GBE_MAX_QUEUE_OUT => cfg_max_queue, - GBE_MAX_SUBS_IN_QUEUE_OUT => cfg_max_subs_in_queue, - GBE_MAX_SINGLE_SUB_OUT => cfg_max_single_sub, - GBE_AUTOTHROTTLE_OUT => cfg_autothrottle, - GBE_THROTTLE_PAUSE_OUT => cfg_throttle_pause, - MONITOR_RX_BYTES_IN => sum_rx_bytes, - MONITOR_RX_FRAMES_IN => sum_rx_frames, - MONITOR_TX_BYTES_IN => sum_tx_bytes, - MONITOR_TX_FRAMES_IN => sum_tx_frames, - MONITOR_TX_PACKETS_IN => sum_tx_packets, - MONITOR_DROPPED_IN => sum_dropped, - MONITOR_SELECT_REC_IN => (others => '0'), - MONITOR_SELECT_REC_BYTES_IN => (others => '0'), - MONITOR_SELECT_SENT_BYTES_IN => (others => '0'), - MONITOR_SELECT_SENT_IN => (others => '0'), - MONITOR_SELECT_DROP_IN_IN => (others => '0'), - MONITOR_SELECT_DROP_OUT_IN => (others => '0'), - MONITOR_SELECT_GEN_DBG_IN => monitor_gen_dbg, - MONITOR_IP_IN => my_ip, - DUMMY_EVENT_SIZE_OUT => dummy_event, - DUMMY_TRIGGERED_MODE_OUT => dummy_mode, - DATA_HIST_IN => (others => (others => '0')), - SCTRL_HIST_IN => (others => (others => '0')) - ); - - NOSCTRL_MAP_GEN : if (LINK_HAS_SLOWCTRL = "0000") generate - GSC_INIT_DATAREADY_OUT <= '0'; - GSC_INIT_DATA_OUT <= (others => '0'); - GSC_INIT_PACKET_NUM_OUT <= (others => '0'); - GSC_REPLY_READ_OUT <= '1'; - mlt_gsc_clk <= '0'; - mlt_gsc_init_read <= '0'; - mlt_gsc_reply_dataready <= '0'; - mlt_gsc_reply_data <= (others => '0'); - mlt_gsc_reply_packet <= (others => '0'); - mlt_gsc_busy <= '0'; - end generate NOSCTRL_MAP_GEN; - - SCTRL_MAP_GEN : if (LINK_HAS_SLOWCTRL /= "0000") generate - ACTIVE_MAP_GEN : if (LINK_HAS_SLOWCTRL(0) = '1') generate - mlt_gsc_clk <= GSC_CLK_IN; - GSC_INIT_DATAREADY_OUT <= mlt_gsc_init_dataready; - GSC_INIT_DATA_OUT <= mlt_gsc_init_data; - GSC_INIT_PACKET_NUM_OUT <= mlt_gsc_init_packet; - mlt_gsc_init_read <= GSC_INIT_READ_IN; - mlt_gsc_reply_dataready <= GSC_REPLY_DATAREADY_IN; - mlt_gsc_reply_data <= GSC_REPLY_DATA_IN; - mlt_gsc_reply_packet <= GSC_REPLY_PACKET_NUM_IN; - GSC_REPLY_READ_OUT <= mlt_gsc_reply_read; - mlt_gsc_busy <= GSC_BUSY_IN; - end generate ACTIVE_MAP_GEN; - - INACTIVE_MAP_GEN : if (LINK_HAS_SLOWCTRL(0) = '0') generate - mlt_gsc_clk <= '0'; - mlt_gsc_init_read <= '0'; - mlt_gsc_reply_dataready <= '0'; - mlt_gsc_reply_data <= (others => '0'); - mlt_gsc_reply_packet <= (others => '0'); - mlt_gsc_busy <= '0'; - end generate INACTIVE_MAP_GEN; - end generate SCTRL_MAP_GEN; - - sum_rx_bytes <= monitor_rx_bytes; - sum_rx_frames <= monitor_rx_frames; - sum_tx_bytes <= monitor_tx_bytes; - sum_tx_frames <= monitor_tx_frames; - sum_tx_packets <= monitor_tx_packets; - sum_dropped <= monitor_dropped; - -end architecture RTL; diff --git a/trb_net16_endpoint_hades_full_gbe.vhd b/trb_net16_endpoint_hades_full_gbe.vhd index d028dc2..41cad6f 100644 --- a/trb_net16_endpoint_hades_full_gbe.vhd +++ b/trb_net16_endpoint_hades_full_gbe.vhd @@ -8,6 +8,7 @@ USE IEEE.std_logic_UNSIGNED.ALL; library work; use work.trb_net_std.all; use work.trb_net_components.all; +use work.config.all; entity trb_net16_endpoint_hades_full_gbe is @@ -545,27 +546,16 @@ begin THE_GBE : gbe_wrapper generic map( - DO_SIMULATION => 0, - INCLUDE_DEBUG => 0, - USE_INTERNAL_TRBNET_DUMMY => 0, - USE_EXTERNAL_TRBNET_DUMMY => 0, - RX_PATH_ENABLE => 1, - FIXED_SIZE_MODE => 1, - INCREMENTAL_MODE => 1, - FIXED_SIZE => 100, - FIXED_DELAY_MODE => 1, - UP_DOWN_MODE => 0, - UP_DOWN_LIMIT => 100, - FIXED_DELAY => 100, - - NUMBER_OF_GBE_LINKS => 4, + + NUMBER_OF_GBE_LINKS => 4-(FPGA_TYPE/5*3), LINKS_ACTIVE => "0001", LINK_HAS_READOUT => "0001", LINK_HAS_SLOWCTRL => "0000", LINK_HAS_DHCP => "0001", LINK_HAS_ARP => "0001", - LINK_HAS_PING => "0001" + LINK_HAS_PING => "0001", + LINK_HAS_FWD => "0000" ) port map( @@ -576,11 +566,8 @@ begin TRIGGER_IN => '0', - SD_PRSNT_N_IN(0) => '1', - SD_PRSNT_N_IN(3 downto 1)=> "111", - SD_LOS_IN(0) => '0', - SD_LOS_IN(3 downto 1) => "111", - SD_TXDIS_OUT(0) => open, + SD_PRSNT_N_IN => (0 => '0', others => '1'), + SD_LOS_IN => (0 => '0', others => '1'), CTS_NUMBER_IN => gbe_cts_number_out, CTS_CODE_IN => gbe_cts_code_out,