From: hadeshyp Date: Tue, 6 Nov 2007 12:35:20 +0000 (+0000) Subject: renamed some files, Jan X-Git-Tag: oldGBE~679 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=9ce6ad87e1e546d20ff08df102ab32e938691401;p=trbnet.git renamed some files, Jan --- diff --git a/trb_net16_api_active.vhd b/trb_net16_api_active.vhd new file mode 100644 index 0000000..cb41ebb --- /dev/null +++ b/trb_net16_api_active.vhd @@ -0,0 +1,221 @@ +-- connection between the TRBNET and any application +-- for a description see HADES wiki +-- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetAPI + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +use work.trb_net_std.all; + + +entity trb_net16_api_active is + + generic ( + --FIFO size is given in 2^(n+1) 64Bit-packets i.e. 2^(n+3) 16bit packets + FIFO_TO_INT_DEPTH : integer := 0; -- direction to medium + FIFO_TO_APL_DEPTH : integer := 0; -- direction to application + FIFO_TERM_BUFFER_DEPTH : integer := 0 -- fifo for auto-answering master path + -- if set to 0, no buffer is used + ); + + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + -- APL Transmitter port + APL_DATA_IN : in std_logic_vector (15 downto 0); -- Data word "application to network" + APL_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + APL_WRITE_IN : in std_logic; -- Data word is valid and should be transmitted + APL_FIFO_FULL_OUT : out std_logic; -- Stop transfer, the fifo is full + APL_SHORT_TRANSFER_IN : in std_logic; -- + APL_DTYPE_IN : in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr + APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr + APL_SEND_IN : in std_logic; -- Release sending of the data + APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0); -- Address of + -- the target (only for active APIs) + + -- Receiver port + APL_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word "network to application" + APL_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM + APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out + APL_READ_IN : in std_logic; -- Read data word + + -- APL Control port + APL_RUN_OUT : out std_logic; -- Data transfer is running + APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!) + APL_SEQNR_OUT : out std_logic_vector (7 downto 0); + + -- Internal direction port + -- the ports with master or slave in their name are to be mapped by the active api + -- to the init respectivly the reply path and vice versa in the passive api. + -- lets define: the "master" path is the path that I send data on. + INT_INIT_DATAREADY_OUT : out std_logic; + INT_INIT_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word + INT_INIT_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + INT_INIT_READ_IN : in std_logic; + + INT_INIT_DATAREADY_IN : in std_logic; + INT_INIT_DATA_IN : in std_logic_vector (15 downto 0); -- Data word + INT_INIT_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + INT_INIT_READ_OUT : out std_logic; + + + INT_REPLY_HEADER_IN : in std_logic; -- Concentrator kindly asks to resend the last + -- header (only for the reply path) + INT_REPLY_DATAREADY_OUT : out std_logic; + INT_REPLY_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word + INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + INT_REPLY_READ_IN : in std_logic; + + INT_REPLY_DATAREADY_IN : in std_logic; + INT_REPLY_DATA_IN : in std_logic_vector (15 downto 0); -- Data word + INT_REPLY_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + INT_REPLY_READ_OUT : out std_logic; + + -- Status and control port + STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0); + STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0) + ); +end entity; + +architecture trb_net16_api_active_arch of trb_net16_api_active is + + component trb_net16_base_api is + generic ( + API_TYPE : integer := 0; -- type of api: 0 passive, 1 active + --FIFO size is given in 2^(n+1) 64Bit-packets i.e. 2^(n+3) 16bit packets + FIFO_TO_INT_DEPTH : integer := 0; -- direction to medium + FIFO_TO_APL_DEPTH : integer := 0; -- direction to application + FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering master path + -- if set to 0, no buffer is used + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + -- APL Transmitter port + APL_DATA_IN : in std_logic_vector (15 downto 0); -- Data word "application to network" + APL_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + APL_WRITE_IN : in std_logic; -- Data word is valid and should be transmitted + APL_FIFO_FULL_OUT : out std_logic; -- Stop transfer, the fifo is full + APL_SHORT_TRANSFER_IN : in std_logic; -- + APL_DTYPE_IN : in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr + APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr + APL_SEND_IN : in std_logic; -- Release sending of the data + APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0); -- Address of + -- the target (only for active APIs) + + -- Receiver port + APL_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word "network to application" + APL_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM + APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out + APL_READ_IN : in std_logic; -- Read data word + + -- APL Control port + APL_RUN_OUT : out std_logic; -- Data transfer is running + APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!) + APL_SEQNR_OUT : out std_logic_vector (7 downto 0); + + -- Internal direction port + -- the ports with master or slave in their name are to be mapped by the active api + -- to the init respectivly the reply path and vice versa in the passive api. + -- lets define: the "master" path is the path that I send data on. + INT_MASTER_DATAREADY_OUT : out std_logic; + INT_MASTER_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word + INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + INT_MASTER_READ_IN : in std_logic; + + INT_MASTER_DATAREADY_IN : in std_logic; + INT_MASTER_DATA_IN : in std_logic_vector (15 downto 0); -- Data word + INT_MASTER_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + INT_MASTER_READ_OUT : out std_logic; + + + INT_SLAVE_HEADER_IN : in std_logic; -- Concentrator kindly asks to resend the last + -- header (only for the reply path) + INT_SLAVE_DATAREADY_OUT : out std_logic; + INT_SLAVE_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word + INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + INT_SLAVE_READ_IN : in std_logic; + + INT_SLAVE_DATAREADY_IN : in std_logic; + INT_SLAVE_DATA_IN : in std_logic_vector (15 downto 0); -- Data word + INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + INT_SLAVE_READ_OUT : out std_logic; + + -- Status and control port + STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0); + STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0) + ); + end component; + +begin + + BASE_API: trb_net16_base_api + generic map ( + API_TYPE => 1, + FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH, + FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH, + FIFO_TERM_BUFFER_DEPTH => FIFO_TERM_BUFFER_DEPTH + ) + port map ( + CLK => CLK, + CLK_EN => CLK_EN, + RESET => RESET, + + APL_DATA_IN => APL_DATA_IN, + APL_PACKET_NUM_IN => APL_PACKET_NUM_IN, + APL_WRITE_IN => APL_WRITE_IN, + APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT, + APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN, + APL_DTYPE_IN => APL_DTYPE_IN, + APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN, + APL_SEND_IN => APL_SEND_IN, + APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN, + APL_DATA_OUT => APL_DATA_OUT, + APL_PACKET_NUM_OUT => APL_PACKET_NUM_OUT, + APL_TYP_OUT => APL_TYP_OUT, + APL_DATAREADY_OUT => APL_DATAREADY_OUT, + APL_READ_IN => APL_READ_IN, + + -- APL Control port + APL_RUN_OUT => APL_RUN_OUT, + APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN, + APL_SEQNR_OUT => APL_SEQNR_OUT, + + -- Internal direction port + INT_MASTER_DATAREADY_OUT => INT_INIT_DATAREADY_OUT, + INT_MASTER_DATA_OUT => INT_INIT_DATA_OUT, + INT_MASTER_PACKET_NUM_OUT => INT_INIT_PACKET_NUM_OUT, + INT_MASTER_READ_IN => INT_INIT_READ_IN, + + INT_MASTER_DATAREADY_IN => INT_INIT_DATAREADY_IN, + INT_MASTER_DATA_IN => INT_INIT_DATA_IN, + INT_MASTER_PACKET_NUM_IN => INT_INIT_PACKET_NUM_IN, + INT_MASTER_READ_OUT => INT_INIT_READ_OUT, + + INT_SLAVE_HEADER_IN => INT_REPLY_HEADER_IN, + + INT_SLAVE_DATAREADY_OUT => INT_REPLY_DATAREADY_OUT, + INT_SLAVE_DATA_OUT => INT_REPLY_DATA_OUT, + INT_SLAVE_PACKET_NUM_OUT => INT_REPLY_PACKET_NUM_OUT, + INT_SLAVE_READ_IN => INT_REPLY_READ_IN, + + INT_SLAVE_DATAREADY_IN => INT_REPLY_DATAREADY_IN, + INT_SLAVE_DATA_IN => INT_REPLY_DATA_IN, + INT_SLAVE_PACKET_NUM_IN => INT_REPLY_PACKET_NUM_IN, + INT_SLAVE_READ_OUT => INT_REPLY_READ_OUT, + -- Status and control port + STAT_FIFO_TO_INT => STAT_FIFO_TO_INT, + STAT_FIFO_TO_APL => STAT_FIFO_TO_APL + -- not needed now, but later + ); + +end architecture; diff --git a/trb_net16_api_base.vhd b/trb_net16_api_base.vhd new file mode 100644 index 0000000..fc86f5e --- /dev/null +++ b/trb_net16_api_base.vhd @@ -0,0 +1,813 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.std_logic_ARITH.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +use work.trb_net_std.all; + + +entity trb_net16_api_base is + + generic ( + API_TYPE : integer := 0; -- type of api: 0 passive, 1 active + --FIFO size is given in 2^(n+1) 64Bit-packets i.e. 2^(n+3) 16bit packets + FIFO_TO_INT_DEPTH : integer := 1; -- direction to medium + FIFO_TO_APL_DEPTH : integer := 1; -- direction to application + FIFO_TERM_BUFFER_DEPTH : integer := 0; -- fifo for auto-answering master path + -- if set to 0, no buffer is used + SBUF_VERSION : integer range 0 to 1 := 0 + ); + + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + -- APL Transmitter port + APL_DATA_IN : in std_logic_vector (15 downto 0); -- Data word "application to network" + APL_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + APL_WRITE_IN : in std_logic; -- Data word is valid and should be transmitted + APL_FIFO_FULL_OUT : out std_logic; -- Stop transfer, the fifo is full + APL_SHORT_TRANSFER_IN : in std_logic; -- + APL_DTYPE_IN : in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr + APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr + APL_SEND_IN : in std_logic; -- Release sending of the data + APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0); -- Address of + -- the target (only for active APIs) + + -- Receiver port + APL_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word "network to application" + APL_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM + APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out + APL_READ_IN : in std_logic; -- Read data word + + -- APL Control port + APL_RUN_OUT : out std_logic; -- Data transfer is running + APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!) + APL_SEQNR_OUT : out std_logic_vector (7 downto 0); + + -- Internal direction port + -- the ports with master or slave in their name are to be mapped by the active api + -- to the init respectivly the reply path and vice versa in the passive api. + -- lets define: the "master" path is the path that I send data on. + INT_MASTER_DATAREADY_OUT : out std_logic; + INT_MASTER_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word + INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + INT_MASTER_READ_IN : in std_logic; + + INT_MASTER_DATAREADY_IN : in std_logic; + INT_MASTER_DATA_IN : in std_logic_vector (15 downto 0); -- Data word + INT_MASTER_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + INT_MASTER_READ_OUT : out std_logic; + + + INT_SLAVE_HEADER_IN : in std_logic; -- Concentrator kindly asks to resend the last + -- header (only for the reply path) + INT_SLAVE_DATAREADY_OUT : out std_logic; + INT_SLAVE_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word + INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + INT_SLAVE_READ_IN : in std_logic; + + INT_SLAVE_DATAREADY_IN : in std_logic; + INT_SLAVE_DATA_IN : in std_logic_vector (15 downto 0); -- Data word + INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + INT_SLAVE_READ_OUT : out std_logic; + + -- Status and control port + STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0); + STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0) + ); +end entity; + + + +architecture trb_net16_api_base_arch of trb_net16_api_base is + + component trb_net16_dummy_fifo is + generic ( + DATA_WIDTH : integer := 16; -- FIFO word width + NUM_WIDTH : integer := 2 + ); + port ( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + DATA_IN : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- Input data + PACKET_NUM_IN : in std_logic_vector(NUM_WIDTH - 1 downto 0); -- Input data + WRITE_ENABLE_IN : in std_logic; + DATA_OUT : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- Output data + PACKET_NUM_OUT : out std_logic_vector(NUM_WIDTH - 1 downto 0); -- Input data + READ_ENABLE_IN : in std_logic; + FULL_OUT : out std_logic; -- Full Flag + EMPTY_OUT : out std_logic; + DEPTH_OUT : out std_logic_vector(7 downto 0) + ); + end component; + + component trb_net16_fifo is + generic ( + DATA_WIDTH : integer := 16; -- FIFO word width + NUM_WIDTH : integer := 2; + DEPTH : integer := 3 -- Depth of the FIFO, 2^(n+1) 64Bit packets + ); + port ( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + DATA_IN : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- Input data + PACKET_NUM_IN : in std_logic_vector(NUM_WIDTH - 1 downto 0); -- Input data + WRITE_ENABLE_IN : in std_logic; + DATA_OUT : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- Output data + PACKET_NUM_OUT : out std_logic_vector(NUM_WIDTH - 1 downto 0); -- Input data + READ_ENABLE_IN : in std_logic; + FULL_OUT : out std_logic; -- Full Flag + EMPTY_OUT : out std_logic; + DEPTH_OUT : out std_logic_vector(7 downto 0) + ); + end component; + + component trb_net16_sbuf is + generic ( + DATA_WIDTH : integer := 16; + NUM_WIDTH : integer := 2; + VERSION : integer := 0 + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- port to combinatorial logic + COMB_DATAREADY_IN : in STD_LOGIC; --comb logic provides data word + COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle + COMB_READ_IN : in STD_LOGIC; --comb logic IS reading + COMB_DATA_IN : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word + COMB_PACKET_NUM_IN: in STD_LOGIC_VECTOR(NUM_WIDTH-1 downto 0); + -- Port to synchronous output. + SYN_DATAREADY_OUT : out STD_LOGIC; + SYN_DATA_OUT : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word + SYN_PACKET_NUM_OUT: out STD_LOGIC_VECTOR(NUM_WIDTH-1 downto 0); + SYN_READ_IN : in STD_LOGIC; + -- Status and control port + STAT_BUFFER : out STD_LOGIC + ); + end component; + + component trb_net16_term is + generic ( + FIFO_TERM_BUFFER_DEPTH : integer := FIFO_TERM_BUFFER_DEPTH; + -- fifo for auto-answering of the master path, if set to 0 no buffer is used at all + SECURE_MODE : integer range 0 to 1 := 0 + --if secure_mode is not used, apl must provide error pattern and dtype until + --next trigger comes in. In secure mode these must be available when hold_trm goes low + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + INT_DATAREADY_OUT: out std_logic; + INT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word + INT_PACKET_NUM_OUT: out std_logic_vector (1 downto 0); + INT_READ_IN: in std_logic; + INT_DATAREADY_IN: in std_logic; + INT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word + INT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + INT_READ_OUT: out std_logic; + -- "mini" APL, just to see the triggers coming in + APL_DTYPE_OUT: out std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr + APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr + APL_SEQNR_OUT: out std_logic_vector (7 downto 0); + APL_GOT_TRM: out std_logic; + APL_RELEASE_TRM: in std_logic; + APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0) + -- Status and control port + ); + end component; + + -- signals for the APL to INT fifo: + signal fifo_to_int_data_in : std_logic_vector(15 downto 0); + signal fifo_to_int_packet_num_in : std_logic_vector(1 downto 0); + signal fifo_to_int_write : std_logic; + signal fifo_to_int_data_out : std_logic_vector(15 downto 0); + signal fifo_to_int_packet_num_out : std_logic_vector(1 downto 0); + signal fifo_to_int_read : std_logic; + signal fifo_to_int_full : std_logic; + signal fifo_to_int_empty : std_logic; + + -- signals for the INT to APL: + signal fifo_to_apl_data_in : std_logic_vector(15 downto 0); + signal fifo_to_apl_packet_num_in : std_logic_vector(1 downto 0); + signal fifo_to_apl_write : std_logic; + signal fifo_to_apl_data_out : std_logic_vector(15 downto 0); + signal fifo_to_apl_packet_num_out : std_logic_vector(1 downto 0); + signal fifo_to_apl_read : std_logic; + signal fifo_to_apl_full : std_logic; + signal fifo_to_apl_empty : std_logic; + signal saved_fifo_to_apl_packet_type, current_fifo_to_apl_packet_type : std_logic_vector(2 downto 0); + + + -- signals for the test buffer + signal fifo_term_buffer_data_in : std_logic_vector(15 downto 0); + signal fifo_term_buffer_packet_num_in : std_logic_vector(1 downto 0); + signal fifo_term_buffer_write : std_logic; + signal fifo_term_buffer_data_out : std_logic_vector(15 downto 0); + signal fifo_term_buffer_packet_num_out : std_logic_vector(1 downto 0); + signal fifo_term_buffer_read : std_logic; + signal fifo_term_buffer_full : std_logic; + signal fifo_term_buffer_empty : std_logic; + + signal state_bits : std_logic_vector(2 downto 0); + type API_STATE is (IDLE, SEND_HEADER, RUNNING, SHUTDOWN, SEND_SHORT, SEND_TRAILER, WAITING,MY_ERROR); + type TERM_BUFFER_STATE is (IDLE, RUNNING, SEND_TRAILER, MY_ERROR); + signal current_state, next_state : API_STATE; + signal tb_current_state, tb_next_state : TERM_BUFFER_STATE; + signal slave_running, next_slave_running : std_logic; + + signal next_INT_MASTER_DATA_OUT: std_logic_vector(15 downto 0); + signal next_INT_MASTER_PACKET_NUM_OUT: std_logic_vector(1 downto 0); + signal next_INT_MASTER_DATAREADY_OUT: std_logic; + signal sbuf_free, sbuf_next_READ: std_logic; + signal next_INT_SLAVE_READ_OUT, reg_INT_SLAVE_READ_OUT: std_logic; + signal next_APL_DATAREADY_OUT, reg_APL_DATAREADY_OUT: std_logic; + signal next_APL_DATA_OUT, reg_APL_DATA_OUT: std_logic_vector(15 downto 0); + signal next_APL_PACKET_NUM_OUT, reg_APL_PACKET_NUM_OUT: std_logic_vector(1 downto 0); + signal next_APL_TYP_OUT, reg_APL_TYP_OUT: std_logic_vector(2 downto 0); + + type OUTPUT_SELECT is (HDR, DAT, TRM, TRM_COMB); + signal out_select, last_out_select: OUTPUT_SELECT; + signal sequence_counter,next_sequence_counter : std_logic_vector(7 downto 0); + signal combined_header_F1, combined_header_F2, combined_header_F3 : std_logic_vector(15 downto 0); + signal combined_trailer_F1, combined_trailer_F2, combined_trailer_F3 : std_logic_vector(15 downto 0); + signal next_registered_trailer_F1, next_registered_trailer_F2, next_registered_trailer_F3 : std_logic_vector(15 downto 0); + signal registered_trailer_F1, registered_trailer_F2, registered_trailer_F3 : std_logic_vector(15 downto 0); + signal current_combined_header, current_registered_trailer, current_combined_trailer, current_data : std_logic_vector(15 downto 0); + + signal update_registered_trailer: std_logic; + signal master_counter : std_logic_vector(1 downto 0); + signal out_enable : std_logic_vector(1 downto 0); +begin +--------------------------------------- +-- termination for active api +--------------------------------------- + genterm: if API_TYPE = 1 generate + TrbNetTerm: trb_net16_term + generic map( + SECURE_MODE => 0 + ) + port map( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + INT_DATAREADY_OUT => INT_SLAVE_DATAREADY_OUT, + INT_DATA_OUT => INT_SLAVE_DATA_OUT, + INT_PACKET_NUM_OUT=> INT_SLAVE_PACKET_NUM_OUT, + INT_READ_IN => INT_SLAVE_READ_IN, + INT_DATAREADY_IN => INT_MASTER_DATAREADY_IN, + INT_DATA_IN => INT_MASTER_DATA_IN, + INT_PACKET_NUM_IN => INT_MASTER_PACKET_NUM_IN, + INT_READ_OUT => INT_MASTER_READ_OUT, + APL_RELEASE_TRM => '1', + APL_ERROR_PATTERN_IN => (others => '0') + ); + end generate; + gennotterm: if API_TYPE = 0 generate + INT_MASTER_READ_OUT <= '1'; + INT_SLAVE_DATAREADY_OUT <= '0'; + end generate; + +--------------------------------------- +-- fifo to internal +--------------------------------------- + + CHECK_BUFFER3: if FIFO_TO_INT_DEPTH >0 generate + FIFO_TO_INT: trb_net16_fifo + generic map ( + DATA_WIDTH => 16, + NUM_WIDTH => 2, + DEPTH => FIFO_TO_INT_DEPTH) + port map ( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + DATA_IN => fifo_to_int_data_in, + PACKET_NUM_IN => fifo_to_int_packet_num_in, + WRITE_ENABLE_IN => fifo_to_int_write, + DATA_OUT => fifo_to_int_data_out, + PACKET_NUM_OUT => fifo_to_int_packet_num_out, + READ_ENABLE_IN => fifo_to_int_read, + FULL_OUT => fifo_to_int_full, + EMPTY_OUT => fifo_to_int_empty + ); + end generate; + + CHECK_BUFFER4: if FIFO_TO_INT_DEPTH =0 generate + FIFO_TO_INT: trb_net16_dummy_fifo + generic map ( + DATA_WIDTH => 16, + NUM_WIDTH => 2) + port map ( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + DATA_IN => fifo_to_int_data_in, + PACKET_NUM_IN => fifo_to_int_packet_num_in, + WRITE_ENABLE_IN => fifo_to_int_write, + DATA_OUT => fifo_to_int_data_out, + PACKET_NUM_OUT => fifo_to_int_packet_num_out, + READ_ENABLE_IN => fifo_to_int_read, + FULL_OUT => fifo_to_int_full, + EMPTY_OUT => fifo_to_int_empty + ); + end generate CHECK_BUFFER4; + + STAT_FIFO_TO_INT(2 downto 0) <= fifo_to_int_data_in(2 downto 0); + STAT_FIFO_TO_INT(3) <= fifo_to_int_write; + STAT_FIFO_TO_INT(10 downto 8) <= fifo_to_int_data_out(2 downto 0); + STAT_FIFO_TO_INT(11) <= fifo_to_int_read; + STAT_FIFO_TO_INT(14) <= fifo_to_int_full; + STAT_FIFO_TO_INT(15) <= fifo_to_int_empty; + STAT_FIFO_TO_INT(7 downto 4) <= (others => '0'); + STAT_FIFO_TO_INT(13 downto 12) <= (others => '0'); + STAT_FIFO_TO_INT(28 downto 16) <= (others => '0'); + STAT_FIFO_TO_INT(31 downto 29) <= state_bits; +--------------------------------------- +-- fifo to apl +--------------------------------------- + + CHECK_BUFFER5: if FIFO_TO_APL_DEPTH >0 generate + FIFO_TO_APL: trb_net16_fifo + generic map ( + DATA_WIDTH => 16, + NUM_WIDTH => 2, + DEPTH => FIFO_TO_APL_DEPTH) + port map ( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + DATA_IN => fifo_to_apl_data_in, + PACKET_NUM_IN => fifo_to_apl_packet_num_in, + WRITE_ENABLE_IN => fifo_to_apl_write, + DATA_OUT => fifo_to_apl_data_out, + PACKET_NUM_OUT => fifo_to_apl_packet_num_out, + READ_ENABLE_IN => fifo_to_apl_read, + FULL_OUT => fifo_to_apl_full, + EMPTY_OUT => fifo_to_apl_empty + ); + end generate CHECK_BUFFER5; + + CHECK_BUFFER6: if FIFO_TO_APL_DEPTH =0 generate + FIFO_TO_APL: trb_net16_dummy_fifo + generic map ( + DATA_WIDTH => 16, + NUM_WIDTH => 2) + port map ( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + DATA_IN => fifo_to_apl_data_in, + PACKET_NUM_IN => fifo_to_apl_packet_num_in, + WRITE_ENABLE_IN => fifo_to_apl_write, + DATA_OUT => fifo_to_apl_data_out, + PACKET_NUM_OUT => fifo_to_apl_packet_num_out, + READ_ENABLE_IN => fifo_to_apl_read, + FULL_OUT => fifo_to_apl_full, + EMPTY_OUT => fifo_to_apl_empty + ); + end generate CHECK_BUFFER6; + + STAT_FIFO_TO_APL(2 downto 0) <= fifo_to_apl_data_in(2 downto 0); + STAT_FIFO_TO_APL(3) <= fifo_to_apl_write; + STAT_FIFO_TO_APL(9 downto 8) <= fifo_to_apl_data_out(1 downto 0); + STAT_FIFO_TO_APL(11) <= fifo_to_apl_read; + STAT_FIFO_TO_APL(14) <= fifo_to_apl_full; + STAT_FIFO_TO_APL(15) <= fifo_to_apl_empty; + STAT_FIFO_TO_APL(7 downto 4) <= (others => '0'); + --STAT_FIFO_TO_APL(13 downto 12) <= (others => '0'); + STAT_FIFO_TO_APL(31 downto 16) <= (others => '0'); + STAT_FIFO_TO_APL(13) <= reg_INT_SLAVE_READ_OUT; + STAT_FIFO_TO_APL(12) <= INT_SLAVE_DATAREADY_IN; + STAT_FIFO_TO_APL(10) <= reg_APL_DATAREADY_OUT; + +--------------------------------------- +-- a sbuf on the active channel +--------------------------------------- + + ACTIVE_SBUF: trb_net16_sbuf + generic map ( + DATA_WIDTH => 16, + NUM_WIDTH => 2, + VERSION => SBUF_VERSION) + port map ( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + COMB_DATAREADY_IN => next_INT_MASTER_DATAREADY_OUT, + COMB_next_READ_OUT => sbuf_next_READ, + COMB_READ_IN => '1', + COMB_DATA_IN => next_INT_MASTER_DATA_OUT, + COMB_PACKET_NUM_IN => next_INT_MASTER_PACKET_NUM_OUT, + SYN_DATAREADY_OUT => INT_MASTER_DATAREADY_OUT, + SYN_DATA_OUT => INT_MASTER_DATA_OUT, + SYN_PACKET_NUM_OUT => INT_MASTER_PACKET_NUM_OUT, + SYN_READ_IN => INT_MASTER_READ_IN + ); + + sbuf_free <= sbuf_next_READ; + + + next_APL_DATA_OUT <= fifo_to_apl_data_out; + next_APL_PACKET_NUM_OUT <= fifo_to_apl_packet_num_out; + next_APL_TYP_OUT <= current_fifo_to_apl_packet_type; + + + --this holds the current packet type from fifo_to_apl + process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + saved_fifo_to_apl_packet_type <= TYPE_ILLEGAL; + elsif fifo_to_apl_packet_num_out = "00" then + saved_fifo_to_apl_packet_type <= fifo_to_apl_data_out(2 downto 0); + end if; + end if; + end process; + --create comb. real packet type + current_fifo_to_apl_packet_type <= fifo_to_apl_data_out(2 downto 0) when (fifo_to_apl_packet_num_out = "00") + else saved_fifo_to_apl_packet_type; + +--------------------------------------- +-- select data for int direction +--------------------------------------- + + + process(current_combined_header, current_registered_trailer, current_combined_trailer, current_data, out_select) + begin + case out_select is + when HDR => next_INT_MASTER_DATA_OUT <= current_combined_header; + when TRM => next_INT_MASTER_DATA_OUT <= current_registered_trailer; + when TRM_COMB => next_INT_MASTER_DATA_OUT <= current_combined_trailer; + when others => next_INT_MASTER_DATA_OUT <= current_data; + end case; + end process; + + + + process(master_counter, fifo_to_int_data_out, combined_header_F1, registered_trailer_F1, + combined_trailer_F1, combined_header_F2, registered_trailer_F2, combined_trailer_F2, + combined_header_F3, registered_trailer_F3, combined_trailer_F3) + begin + case master_counter is + when "01" => + current_combined_header <= combined_header_F1; + current_registered_trailer <= registered_trailer_F1; + current_combined_trailer <= combined_trailer_F1; + current_data <= fifo_to_int_data_out; + when "10" => + current_combined_header <= combined_header_F2; + current_registered_trailer <= registered_trailer_F2; + current_combined_trailer <= combined_trailer_F2; + current_data <= fifo_to_int_data_out; + when "11" => + current_combined_header <= combined_header_F3; + current_registered_trailer <= registered_trailer_F3; + current_combined_trailer <= combined_trailer_F3; + current_data <= fifo_to_int_data_out; + when others => + current_combined_header <= "0000000000000" & TYPE_HDR; + current_registered_trailer <= "0000000000000" & TYPE_TRM; + current_combined_trailer <= "0000000000000" & TYPE_TRM; + current_data <= "0000000000000" & TYPE_DAT; + end case; + end process; + + next_INT_MASTER_PACKET_NUM_OUT <= master_counter; + + MASTER_TRANSFER_COUNTER : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + master_counter <= (others => '0'); + elsif next_INT_MASTER_DATAREADY_OUT = '1' then + master_counter <= master_counter + 1; + end if; + end if; + end process; + + +--------------------------------------- +--the state machine +--------------------------------------- + + STATE_COMB: process(current_state, APL_SEND_IN, slave_running, sequence_counter, + APL_SHORT_TRANSFER_IN, APL_WRITE_IN, fifo_to_int_empty, + sbuf_free, master_counter, fifo_to_apl_full, + reg_APL_DATAREADY_OUT, reg_INT_SLAVE_READ_OUT, + INT_SLAVE_DATAREADY_IN, fifo_to_apl_empty, APL_READ_IN, + fifo_to_apl_packet_num_out, reg_APL_TYP_OUT, + reg_APL_PACKET_NUM_OUT, last_out_select) + begin + next_state <= MY_ERROR; + next_INT_MASTER_DATAREADY_OUT <= '0'; + out_select <= DAT; + update_registered_trailer <= '0'; + fifo_to_int_read <= '0'; + next_INT_SLAVE_READ_OUT <= '0'; + fifo_to_apl_write <= '0'; + next_APL_DATAREADY_OUT <= '0'; + fifo_to_apl_read <= '0'; + next_slave_running <= slave_running; + next_sequence_counter <= sequence_counter; + ------------------------------------------------------------------------------- + -- IDLE + ------------------------------------------------------------------------------- + if current_state = IDLE then + if APL_SEND_IN = '1' then + if APL_SHORT_TRANSFER_IN = '1' then -- and APL_WRITE_IN = '0' and fifo_to_int_empty = '1' + next_state <= SEND_SHORT; -- no next data word, waiting for falling edge of APL_SEND_IN + update_registered_trailer <= '1'; -- moved from SEND_SHORT + else -- normal transfer, prepare the header + next_state <= SEND_HEADER; + out_select <= HDR; + next_INT_MASTER_DATAREADY_OUT <= '1'; + end if; -- next word will be a header + else + next_state <= IDLE; + end if; -- APL_SEND_IN + ------------------------------------------------------------------------------- + -- SEND_SHORT + ------------------------------------------------------------------------------- + elsif current_state = SEND_SHORT then + next_state <= SEND_SHORT; + out_select <= TRM; + if APL_SEND_IN = '0' then -- terminate the transfer + next_state <= SEND_TRAILER; + next_INT_MASTER_DATAREADY_OUT <= '1'; + end if; + ------------------------------------------------------------------------------- + -- SEND_HEADER + ------------------------------------------------------------------------------- + elsif current_state = SEND_HEADER then + out_select <= HDR; + if sbuf_free = '1' then + next_INT_MASTER_DATAREADY_OUT <= '1'; + end if; + if master_counter = "00" then + next_state <= RUNNING; + next_INT_MASTER_DATAREADY_OUT <= '0'; + else + next_state <= SEND_HEADER; + end if; + ------------------------------------------------------------------------------- + -- RUNNING + ------------------------------------------------------------------------------- + elsif current_state = RUNNING then + if sbuf_free = '1' then + fifo_to_int_read <= '1'; + end if; + if APL_SEND_IN = '0' then -- terminate the transfer + update_registered_trailer <= '1'; + if fifo_to_int_empty = '1' then -- immediate stop + next_INT_MASTER_DATAREADY_OUT <= '1'; + if master_counter = "11" then + next_state <= SEND_TRAILER; + out_select <= TRM_COMB; + end if; + else + next_state <= SHUTDOWN; + if sbuf_free = '1' then + next_INT_MASTER_DATAREADY_OUT <= '1'; + end if; + end if; + else -- APL_SEND_IN: still running + next_state <= RUNNING; + if fifo_to_int_empty = '0' and sbuf_free = '1' then + -- data words have to be prepared + next_INT_MASTER_DATAREADY_OUT <= '1'; + end if; -- fifo_to_int_empty = '0' + end if; + ------------------------------------------------------------------------------- + -- SHUTDOWN: Empty the pipe + ------------------------------------------------------------------------------- + elsif current_state = SHUTDOWN then + next_state <= SHUTDOWN; + if sbuf_free = '1' then +-- next_INT_MASTER_DATAREADY_OUT <= '1'; +-- -- we are done +-- --implicit: fill with padding words +-- if master_counter = "00" and fifo_to_int_empty = '1' then +-- next_state <= SEND_TRAILER; +-- out_select <= TRM; + if fifo_to_int_empty = '0' then + -- data words have to be prepared + fifo_to_int_read <= '1'; + next_INT_MASTER_DATAREADY_OUT <= '1'; + else + -- we are done + --implicit: fill with padding words + if master_counter = "00" then + next_state <= SEND_TRAILER; + out_select <= TRM; + end if; + next_INT_MASTER_DATAREADY_OUT <= '1'; + end if; + end if; + ------------------------------------------------------------------------------- + -- SEND_TRAILER + ------------------------------------------------------------------------------- + elsif current_state = SEND_TRAILER then + out_select <= TRM; + if sbuf_free = '1' then + next_INT_MASTER_DATAREADY_OUT <= '1'; + end if; + if master_counter = "00" then + next_state <= WAITING; + next_INT_MASTER_DATAREADY_OUT <= '0'; + if API_TYPE = 0 then --here is the end of the passive transfer + next_sequence_counter <= sequence_counter +1; + next_slave_running <= '0'; + end if; + else + next_state <= SEND_TRAILER; + end if; + ------------------------------------------------------------------------------- + -- WAITING => for the answer or a request + ------------------------------------------------------------------------------- + elsif current_state = WAITING then + next_state <= WAITING; + -- here we have to supply the receiver port + -- part 1: connection to network + if fifo_to_apl_full = '0' or (fifo_to_apl_read = '1' and reg_APL_DATAREADY_OUT = '1') then + next_INT_SLAVE_READ_OUT <= '1'; + end if; + if reg_INT_SLAVE_READ_OUT = '1' and INT_SLAVE_DATAREADY_IN = '1' then + fifo_to_apl_write <= '1'; -- use fifo as the pipe + end if; + + -- part 2: connection to apl +-- if fifo_to_apl_empty = '0' then + if fifo_to_apl_empty = '0' --and not (reg_APL_DATAREADY_OUT = '1' and APL_READ_IN = '1') + and fifo_to_apl_packet_num_out /= "00" then --is this really correct???? + next_APL_DATAREADY_OUT <= '1'; + end if; -- read/no read + + if (reg_APL_DATAREADY_OUT = '1' and APL_READ_IN = '1') or fifo_to_apl_packet_num_out = "00" then + -- valid read + fifo_to_apl_read <= not fifo_to_apl_empty; + if API_TYPE = 0 then + if (reg_APL_TYP_OUT = TYPE_TRM or reg_APL_TYP_OUT = TYPE_HDR) then + next_slave_running <= '1'; + end if; + end if; + if reg_APL_TYP_OUT = TYPE_TRM and reg_APL_PACKET_NUM_OUT= "11" and (APL_READ_IN = '1' and reg_APL_DATAREADY_OUT = '1') + then --fifo_to_apl_read = '1' + next_state <= IDLE; + if API_TYPE = 1 then + next_sequence_counter <= sequence_counter +1; + end if; + end if; + end if; + -- MISSING: SEQNR check + -- OPEN QUESTION: Address matching? makes sense for a reply transfer? + end if; + if master_counter = "00" or fifo_to_int_empty = '1' then + fifo_to_int_read <= '0'; + end if; + end process; + + CLK_REG: process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + sequence_counter <= (others => '0'); + reg_INT_SLAVE_READ_OUT <= '0'; + last_out_select <= DAT; + if API_TYPE = 1 then + current_state <= IDLE; + else + current_state <= WAITING; + end if; + slave_running <= '0'; + elsif CLK_EN = '1' then + sequence_counter <= next_sequence_counter; + last_out_select <= out_select; + reg_INT_SLAVE_READ_OUT <= next_INT_SLAVE_READ_OUT; + current_state <= next_state; + slave_running <= next_slave_running; + end if; + end if; + end process; + +--------------------------------------- +-- +--------------------------------------- + + --get target address from active APL + gentarget1: if API_TYPE = 1 generate + combined_header_F2 <= APL_TARGET_ADDRESS_IN; + end generate; + --save target address for passive api + gentarget0: if API_TYPE = 0 generate + reg_hdr_f1: process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + combined_header_F2 <= (others => '1'); + elsif current_fifo_to_apl_packet_type = TYPE_HDR and fifo_to_apl_packet_num_out = "01" then + combined_header_F2 <= fifo_to_apl_data_out; + end if; + end if; + end process; + end generate; + -- combine the next header + combined_header_F1 <= APL_MY_ADDRESS_IN; + combined_header_F3(15 downto 14) <= (others => '0'); -- LAY + combined_header_F3(13 downto 12) <= (others => '0'); -- VERS + combined_header_F3(11 downto 4) <= sequence_counter; -- SEQNR + combined_header_F3(3 downto 0) <= APL_DTYPE_IN; + combined_trailer_F1 <= APL_ERROR_PATTERN_IN(31 downto 16); + combined_trailer_F2 <= APL_ERROR_PATTERN_IN(15 downto 0); + combined_trailer_F3(15 downto 14) <= (others => '0'); -- res. + combined_trailer_F3(13 downto 12) <= (others => '0'); -- VERS + combined_trailer_F3(11 downto 4) <= sequence_counter; -- SEQNR + combined_trailer_F3(3 downto 0) <= APL_DTYPE_IN; + + -- connect Transmitter port + fifo_to_int_data_in <= APL_DATA_IN; + fifo_to_int_packet_num_in <= APL_PACKET_NUM_IN; + fifo_to_int_write <= (APL_WRITE_IN and not fifo_to_int_full) + when (current_state = IDLE or current_state = SEND_HEADER or current_state = RUNNING) + else '0'; + + APL_FIFO_FULL_OUT <= fifo_to_int_full; -- APL has to stop writing + + INT_SLAVE_READ_OUT <= reg_INT_SLAVE_READ_OUT; + + process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + reg_APL_DATAREADY_OUT <= '0'; + reg_APL_DATA_OUT <= (others => '0'); + reg_APL_PACKET_NUM_OUT <= (others => '0'); + reg_APL_TYP_OUT <= (others => '0'); + elsif CLK_EN = '1' then + reg_APL_DATAREADY_OUT <= next_APL_DATAREADY_OUT; + reg_APL_DATA_OUT <= next_APL_DATA_OUT; + reg_APL_PACKET_NUM_OUT <= next_APL_PACKET_NUM_OUT; + reg_APL_TYP_OUT <= next_APL_TYP_OUT; + end if; + end if; + end process; + + + -- connect receiver + fifo_to_apl_data_in <= INT_SLAVE_DATA_IN; + fifo_to_apl_packet_num_in <= INT_SLAVE_PACKET_NUM_IN; + + APL_DATAREADY_OUT <= reg_APL_DATAREADY_OUT; + APL_DATA_OUT <= reg_APL_DATA_OUT; + APL_PACKET_NUM_OUT <= reg_APL_PACKET_NUM_OUT; + APL_TYP_OUT <= reg_APL_TYP_OUT; + + genAPL_RUN_OUT_0: if API_TYPE = 0 generate + APL_RUN_OUT <= slave_running; + end generate; + genAPL_RUN_OUT_1: if API_TYPE = 1 generate + APL_RUN_OUT <= '0' when current_state = IDLE else '1'; + end generate; + + APL_SEQNR_OUT <= sequence_counter; + + REG3 : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + registered_trailer_F1 <= (others => '0'); + registered_trailer_F2 <= (others => '0'); + registered_trailer_F3 <= (others => '0'); + elsif update_registered_trailer = '1' then + registered_trailer_F1 <= combined_trailer_F1; + registered_trailer_F2 <= combined_trailer_F2; + registered_trailer_F3 <= combined_trailer_F3; + end if; + end if; + end process; + + process(current_state) + begin + case current_state is + when IDLE => state_bits <= "000"; + when SEND_HEADER => state_bits <= "001"; + when RUNNING => state_bits <= "010"; + when SHUTDOWN => state_bits <= "011"; + when SEND_SHORT => state_bits <= "100"; + when SEND_TRAILER => state_bits <= "101"; + when WAITING => state_bits <= "110"; + when others => state_bits <= "111"; + end case; + end process; + +end architecture; \ No newline at end of file diff --git a/trb_net16_api_passive.vhd b/trb_net16_api_passive.vhd new file mode 100644 index 0000000..52a9f57 --- /dev/null +++ b/trb_net16_api_passive.vhd @@ -0,0 +1,221 @@ +-- connection between the TRBNET and any application +-- for a description see HADES wiki +-- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetAPI + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +use work.trb_net_std.all; + + +entity trb_net16_api_passive is + + generic ( + --FIFO size is given in 2^(n+1) 64Bit-packets i.e. 2^(n+3) 16bit packets + FIFO_TO_INT_DEPTH : integer := 0; -- direction to medium + FIFO_TO_APL_DEPTH : integer := 0; -- direction to application + FIFO_TERM_BUFFER_DEPTH : integer := 0 -- fifo for auto-answering master path + -- if set to 0, no buffer is used + ); + + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + -- APL Transmitter port + APL_DATA_IN : in std_logic_vector (15 downto 0); -- Data word "application to network" + APL_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + APL_WRITE_IN : in std_logic; -- Data word is valid and should be transmitted + APL_FIFO_FULL_OUT : out std_logic; -- Stop transfer, the fifo is full + APL_SHORT_TRANSFER_IN : in std_logic; -- + APL_DTYPE_IN : in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr + APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr + APL_SEND_IN : in std_logic; -- Release sending of the data + APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0); -- Address of + -- the target (only for active APIs) + + -- Receiver port + APL_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word "network to application" + APL_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM + APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out + APL_READ_IN : in std_logic; -- Read data word + + -- APL Control port + APL_RUN_OUT : out std_logic; -- Data transfer is running + APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!) + APL_SEQNR_OUT : out std_logic_vector (7 downto 0); + + -- Internal direction port + -- the ports with master or slave in their name are to be mapped by the active api + -- to the init respectivly the reply path and vice versa in the passive api. + -- lets define: the "master" path is the path that I send data on. + INT_INIT_DATAREADY_OUT : out std_logic; + INT_INIT_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word + INT_INIT_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + INT_INIT_READ_IN : in std_logic; + + INT_INIT_DATAREADY_IN : in std_logic; + INT_INIT_DATA_IN : in std_logic_vector (15 downto 0); -- Data word + INT_INIT_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + INT_INIT_READ_OUT : out std_logic; + + + INT_REPLY_HEADER_IN : in std_logic; -- Concentrator kindly asks to resend the last + -- header (only for the reply path) + INT_REPLY_DATAREADY_OUT : out std_logic; + INT_REPLY_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word + INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + INT_REPLY_READ_IN : in std_logic; + + INT_REPLY_DATAREADY_IN : in std_logic; + INT_REPLY_DATA_IN : in std_logic_vector (15 downto 0); -- Data word + INT_REPLY_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + INT_REPLY_READ_OUT : out std_logic; + + -- Status and control port + STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0); + STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0) + ); +end entity; + +architecture trb_net16_api_passive_arch of trb_net16_api_passive is + + component trb_net16_base_api is + generic ( + API_TYPE : integer := 0; -- type of api: 0 passive, 1 active + --FIFO size is given in 2^(n+1) 64Bit-packets i.e. 2^(n+3) 16bit packets + FIFO_TO_INT_DEPTH : integer := 0; -- direction to medium + FIFO_TO_APL_DEPTH : integer := 0; -- direction to application + FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering master path + -- if set to 0, no buffer is used + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + -- APL Transmitter port + APL_DATA_IN : in std_logic_vector (15 downto 0); -- Data word "application to network" + APL_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + APL_WRITE_IN : in std_logic; -- Data word is valid and should be transmitted + APL_FIFO_FULL_OUT : out std_logic; -- Stop transfer, the fifo is full + APL_SHORT_TRANSFER_IN : in std_logic; -- + APL_DTYPE_IN : in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr + APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr + APL_SEND_IN : in std_logic; -- Release sending of the data + APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0); -- Address of + -- the target (only for active APIs) + + -- Receiver port + APL_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word "network to application" + APL_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM + APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out + APL_READ_IN : in std_logic; -- Read data word + + -- APL Control port + APL_RUN_OUT : out std_logic; -- Data transfer is running + APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!) + APL_SEQNR_OUT : out std_logic_vector (7 downto 0); + + -- Internal direction port + -- the ports with master or slave in their name are to be mapped by the active api + -- to the init respectivly the reply path and vice versa in the passive api. + -- lets define: the "master" path is the path that I send data on. + INT_MASTER_DATAREADY_OUT : out std_logic; + INT_MASTER_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word + INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + INT_MASTER_READ_IN : in std_logic; + + INT_MASTER_DATAREADY_IN : in std_logic; + INT_MASTER_DATA_IN : in std_logic_vector (15 downto 0); -- Data word + INT_MASTER_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + INT_MASTER_READ_OUT : out std_logic; + + + INT_SLAVE_HEADER_IN : in std_logic; -- Concentrator kindly asks to resend the last + -- header (only for the reply path) + INT_SLAVE_DATAREADY_OUT : out std_logic; + INT_SLAVE_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word + INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + INT_SLAVE_READ_IN : in std_logic; + + INT_SLAVE_DATAREADY_IN : in std_logic; + INT_SLAVE_DATA_IN : in std_logic_vector (15 downto 0); -- Data word + INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + INT_SLAVE_READ_OUT : out std_logic; + + -- Status and control port + STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0); + STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0) + ); + end component; + +begin + + BASE_API: trb_net16_base_api + generic map ( + API_TYPE => 0, + FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH, + FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH, + FIFO_TERM_BUFFER_DEPTH => FIFO_TERM_BUFFER_DEPTH + ) + port map ( + CLK => CLK, + CLK_EN => CLK_EN, + RESET => RESET, + + APL_DATA_IN => APL_DATA_IN, + APL_PACKET_NUM_IN => APL_PACKET_NUM_IN, + APL_WRITE_IN => APL_WRITE_IN, + APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT, + APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN, + APL_DTYPE_IN => APL_DTYPE_IN, + APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN, + APL_SEND_IN => APL_SEND_IN, + APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN, + APL_DATA_OUT => APL_DATA_OUT, + APL_PACKET_NUM_OUT => APL_PACKET_NUM_OUT, + APL_TYP_OUT => APL_TYP_OUT, + APL_DATAREADY_OUT => APL_DATAREADY_OUT, + APL_READ_IN => APL_READ_IN, + + -- APL Control port + APL_RUN_OUT => APL_RUN_OUT, + APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN, + APL_SEQNR_OUT => APL_SEQNR_OUT, + + -- Internal direction port + INT_MASTER_DATAREADY_OUT => INT_REPLY_DATAREADY_OUT, + INT_MASTER_DATA_OUT => INT_REPLY_DATA_OUT, + INT_MASTER_PACKET_NUM_OUT => INT_REPLY_PACKET_NUM_OUT, + INT_MASTER_READ_IN => INT_REPLY_READ_IN, + + INT_MASTER_DATAREADY_IN => INT_REPLY_DATAREADY_IN, + INT_MASTER_DATA_IN => INT_REPLY_DATA_IN, + INT_MASTER_PACKET_NUM_IN => INT_REPLY_PACKET_NUM_IN, + INT_MASTER_READ_OUT => INT_REPLY_READ_OUT, + + INT_SLAVE_HEADER_IN => INT_REPLY_HEADER_IN, + + INT_SLAVE_DATAREADY_OUT => INT_INIT_DATAREADY_OUT, + INT_SLAVE_DATA_OUT => INT_INIT_DATA_OUT, + INT_SLAVE_PACKET_NUM_OUT => INT_INIT_PACKET_NUM_OUT, + INT_SLAVE_READ_IN => INT_INIT_READ_IN, + + INT_SLAVE_DATAREADY_IN => INT_INIT_DATAREADY_IN, + INT_SLAVE_DATA_IN => INT_INIT_DATA_IN, + INT_SLAVE_PACKET_NUM_IN => INT_INIT_PACKET_NUM_IN, + INT_SLAVE_READ_OUT => INT_INIT_READ_OUT, + -- Status and control port + STAT_FIFO_TO_INT => STAT_FIFO_TO_INT, + STAT_FIFO_TO_APL => STAT_FIFO_TO_APL + -- not needed now, but later + ); + +end architecture;