From: Cahit Date: Tue, 8 Dec 2015 15:26:54 +0000 (+0100) Subject: tidy up X-Git-Tag: v2.3~61 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=9d4ce7d381ad601dcb7a5d9306c9cf8d275fdb33;p=tdc.git tidy up --- diff --git a/releases/tdc_v2.3/Channel.vhd b/releases/tdc_v2.3/Channel.vhd index 570ec4d..ee09c05 100644 --- a/releases/tdc_v2.3/Channel.vhd +++ b/releases/tdc_v2.3/Channel.vhd @@ -94,12 +94,9 @@ architecture Channel of Channel is ------------------------------------------------------------------------------- attribute syn_keep : boolean; --- attribute syn_keep of trg_win_end_tdc : signal is true; attribute syn_keep of trg_win_end_rdo : signal is true; attribute syn_preserve : boolean; --- attribute syn_preserve of trg_win_end_tdc : signal is true; attribute nomerge : string; --- attribute nomerge of trg_win_end_tdc : signal is "true"; attribute nomerge of trg_win_end_rdo : signal is "true"; ------------------------------------------------------------------------------- @@ -176,7 +173,7 @@ begin FIFO_DATA_VALID_OUT <= buf_data_valid; -- FIFO_EMPTY_OUT <= buf_empty; FIFO_EMPTY_OUT <= buf_empty when rising_edge(CLK_100); - trg_win_end_tdc <= TRG_WIN_END_TDC_IN; -- when rising_edge(CLK_200); + trg_win_end_tdc <= TRG_WIN_END_TDC_IN; trg_win_end_rdo <= TRG_WIN_END_RDO_IN; rd_en_reg <= READ_EN_IN when rising_edge(CLK_100); buf_empty_reg <= buf_empty when rising_edge(CLK_100); diff --git a/releases/tdc_v2.3/Readout_record.vhd b/releases/tdc_v2.3/Readout_record.vhd index e1690eb..9c2da78 100644 --- a/releases/tdc_v2.3/Readout_record.vhd +++ b/releases/tdc_v2.3/Readout_record.vhd @@ -5,7 +5,7 @@ -- File : Readout_record.vhd -- Author : cugur@gsi.de -- Created : 2012-10-25 --- Last update: 2015-10-16 +-- Last update: 2015-12-07 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- @@ -190,6 +190,8 @@ architecture behavioral of Readout_record is signal hit_in_i : std_logic_vector(CHANNEL_NUMBER-1 downto 1); -- debug signal header_error_bits : std_logic_vector(15 downto 0); + signal header_trg_type : std_logic_vector(3 downto 0); + signal header_trg_code : std_logic_vector(7 downto 0); signal trailer_error_bits : std_logic_vector(15 downto 0); signal rd_fsm_debug : std_logic_vector(3 downto 0); signal rd_fsm_debug_r : std_logic_vector(3 downto 0); @@ -355,9 +357,9 @@ begin -- behavioral RD_NEXT <= WAIT_FOR_BUFFER_TRANSFER; if MISSING_REF_TIME_IN = '1' or isNoHit_r = '0' then wr_header_fsm <= '1'; - if MISSING_REF_TIME_IN = '1' then + end if; + if MISSING_REF_TIME_IN = '1' then missing_ref_time_fsm <= '1'; - end if; end if; end if; wait_fsm <= '1'; @@ -656,6 +658,17 @@ begin -- behavioral header_error_bits(1) <= missing_ref_time; header_error_bits(15 downto 2) <= (others => '0'); + HeaderTriggerInfo: process (CLK_100) is + begin + if rising_edge(CLK_100) then -- rising clock edge + if READOUT_RX.data_valid = '1' then + header_trg_type <= READOUT_RX.trg_type when ; + header_trg_code <= READOUT_RX.trg_code when ; + end if; + end if; + end process HeaderTriggerInfo; + + -- Error, warning bits set in the trailer trailer_error_bits <= (others => '0'); -- trailer_error_bits (0) <= wrong_readout; -- if there is a wrong readout because of a spurious timing trigger diff --git a/releases/tdc_v2.3/TDC_record.vhd b/releases/tdc_v2.3/TDC_record.vhd index 6afe545..6639c72 100644 --- a/releases/tdc_v2.3/TDC_record.vhd +++ b/releases/tdc_v2.3/TDC_record.vhd @@ -46,8 +46,6 @@ architecture TDC_record of TDC_record is -- Coarse counters signal coarse_cntr : std_logic_vector_array_11(0 to CHANNEL_NUMBER); signal coarse_cntr_reset : std_logic; - --signal coarse_cntr_reset_r : std_logic_vector(CHANNEL_NUMBER downto 0); - --signal coarse_cntr_reset_2r : std_logic_vector(CHANNEL_NUMBER downto 0); -- Slow control signal ctrl_reg : std_logic_vector_array_32(0 to 8); signal logic_anal_control : std_logic_vector(3 downto 0); @@ -129,7 +127,6 @@ architecture TDC_record of TDC_record is signal trg_win_en : std_logic; signal trg_win_end_rdo : std_logic; signal trg_win_end_tdc : std_logic; - signal trg_win_end_tdc_r : std_logic_vector(CHANNEL_NUMBER downto 0); signal missing_ref_time : std_logic; signal valid_trg_rdo : std_logic; signal valid_trg_tdc : std_logic; @@ -159,15 +156,9 @@ architecture TDC_record of TDC_record is attribute syn_keep : boolean; attribute syn_keep of reset_tdc : signal is true; attribute syn_keep of coarse_cntr : signal is true; - --attribute syn_keep of coarse_cntr_reset_r : signal is true; - --attribute syn_keep of coarse_cntr_reset_2r : signal is true; - --attribute syn_keep of trg_win_end_tdc_r : signal is true; attribute syn_keep of hit_in_i : signal is true; attribute syn_preserve : boolean; attribute syn_preserve of coarse_cntr : signal is true; - --attribute syn_preserve of coarse_cntr_reset_r : signal is true; - --attribute syn_preserve of coarse_cntr_reset_2r : signal is true; - --attribute syn_preserve of trg_win_end_tdc_r : signal is true; attribute syn_preserve of hit_in_i : signal is true; attribute nomerge : string; attribute nomerge of hit_in_i : signal is "true"; @@ -415,7 +406,7 @@ begin CLK_100 => CLK_READOUT, HIT_IN => hit_in_i(0), HIT_EDGE_IN => '1', - TRG_WIN_END_TDC_IN => trg_win_end_tdc, --trg_win_end_tdc_r(0), + TRG_WIN_END_TDC_IN => trg_win_end_tdc, TRG_WIN_END_RDO_IN => trg_win_end_rdo, EPOCH_COUNTER_IN => epoch_cntr, COARSE_COUNTER_IN => coarse_cntr(0), @@ -450,7 +441,7 @@ begin CLK_100 => CLK_READOUT, HIT_IN => hit_in_i(i), HIT_EDGE_IN => hit_edge_2r(i), - TRG_WIN_END_TDC_IN => trg_win_end_tdc, --trg_win_end_tdc_r(i), + TRG_WIN_END_TDC_IN => trg_win_end_tdc, TRG_WIN_END_RDO_IN => trg_win_end_rdo, EPOCH_COUNTER_IN => epoch_cntr, COARSE_COUNTER_IN => coarse_cntr(i), -- coarse_cntr(integer(ceil(real(i)/real(8)))), @@ -515,9 +506,6 @@ begin DEBUG_OUT => trg_handler_status_registers ); trg_in <= REFERENCE_TIME; - --GenTriggerWindowEnd : for i in 0 to CHANNEL_NUMBER generate - -- trg_win_end_tdc_r(i) <= trg_win_end_tdc when rising_edge(CLK_TDC); - --end generate GenTriggerWindowEnd; ------------------------------------------------------------------------------- -- Readout @@ -548,7 +536,7 @@ begin TRG_WIN_POST_IN => trg_win_post, TRG_WIN_EN_IN => trg_win_en, -- from the trigger handler - TRG_WIN_END_TDC_IN => trg_win_end_tdc, --trg_win_end_tdc_r(CHANNEL_NUMBER), + TRG_WIN_END_TDC_IN => trg_win_end_tdc, TRG_WIN_END_RDO_IN => trg_win_end_rdo, TRG_TDC_IN => trg_tdc, TRG_TIME_IN => trg_time, @@ -570,7 +558,7 @@ begin NUMBER_OF_BITS => 11) port map ( CLK => CLK_TDC, - RESET => coarse_cntr_reset, --coarse_cntr_reset_2r(i), + RESET => coarse_cntr_reset, COUNT_OUT => coarse_cntr(i), UP_IN => '1'); end generate GenCoarseCounter; @@ -581,7 +569,7 @@ begin if reset_tdc = '1' then coarse_cntr_reset <= '1'; --elsif run_mode_200 = '0' then - -- coarse_cntr_reset <= trg_win_end_tdc_r(1); + -- coarse_cntr_reset <= trg_win_end_tdc; --elsif run_mode_edge_200 = '1' then -- coarse_cntr_reset <= '1'; elsif reset_coarse_cntr_flag = '1' and valid_trg_tdc = '1' then @@ -609,11 +597,6 @@ begin SIGNAL_IN => reset_coarse_cntr_200, PULSE_OUT => reset_coarse_cntr_edge_200); - --GenCoarseCounterReset : for i in 0 to CHANNEL_NUMBER generate - -- coarse_cntr_reset_r(i) <= coarse_cntr_reset when rising_edge(CLK_TDC); - -- coarse_cntr_reset_2r(i) <= coarse_cntr_reset_r(i) when rising_edge(CLK_TDC); - --end generate GenCoarseCounterReset; - -- EPOCH counter TheEpochCounter : up_counter generic map ( @@ -624,7 +607,7 @@ begin COUNT_OUT => epoch_cntr, UP_IN => epoch_cntr_up); epoch_cntr_up <= and_all(coarse_cntr(CHANNEL_NUMBER)); - epoch_cntr_reset <= coarse_cntr_reset; --coarse_cntr_reset_2r(CHANNEL_NUMBER); + epoch_cntr_reset <= coarse_cntr_reset; ------------------------------------------------------------------------------- -- Statistics