From: Ingo Froehlich <ingo@nomail.fake>
Date: Mon, 20 Aug 2018 11:26:57 +0000 (+0200)
Subject: small merge
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=9d7ff0ad3001b9fb7bfb6840dcf37013ff67d2bc;p=trbnet.git

small merge
---

9d7ff0ad3001b9fb7bfb6840dcf37013ff67d2bc
diff --cc media_interfaces/sync/med_sync_control.vhd
index 9b7912f,48771a6..0246a2d
--- a/media_interfaces/sync/med_sync_control.vhd
+++ b/media_interfaces/sync/med_sync_control.vhd
@@@ -70,9 -64,7 +70,9 @@@ architecture med_sync_control_arch of m
  signal rx_fsm_state : std_logic_vector(3 downto 0);
  signal tx_fsm_state : std_logic_vector(3 downto 0);
  signal wa_position_rx : std_logic_vector(3 downto 0);
- --signal start_timer       : unsigned(20 downto 0) := (others => '0'); --REAL
- signal start_timer       : unsigned(11 downto 0) := (others => '0'); --SIM
 -signal start_timer       : unsigned(21 downto 0) := (others => '0');
 +
++signal start_timer       : unsigned(21 downto 0) := (others => '0'); --REAL
++--signal start_timer       : unsigned(11 downto 0) := (others => '0'); --SIM
  
  signal request_retr_i     : std_logic;
  signal start_retr_i       : std_logic;
diff --cc media_interfaces/sync/rx_control.vhd
index 7cc82c9,2a04916..63acb22
--- a/media_interfaces/sync/rx_control.vhd
+++ b/media_interfaces/sync/rx_control.vhd
@@@ -231,10 -141,6 +231,11 @@@ PROC_RX_FSM : process begi
    rx_dlm_i             <= '0';
    idle_hist_i(3 downto 1) <= idle_hist_i(2 downto 0);
    idle_hist_i(0)       <= got_link_ready_i;
 +  crc_en               <= '0';
 +  crc_reset            <= '0';
 +  pulse_good           <= '0';
 +  pulse_bad            <= '0';
++
    
    case rx_state is
      when SLEEP =>
diff --cc media_interfaces/sync/tx_control.vhd
index 5ef8ec5,298e8d2..a52fcee
--- a/media_interfaces/sync/tx_control.vhd
+++ b/media_interfaces/sync/tx_control.vhd
@@@ -110,14 -103,7 +110,15 @@@ architecture arch of tx_control i
    signal crc_en                  : std_logic;
    signal crc_data                : std_logic_vector(7 downto 0);
    signal first_idle              : std_logic;
 -  signal toggle_idle             : std_logic;
 +  signal toggle_idle             : std_logic := '0';
 +
 +  signal send_chksum_counter : std_logic_vector(7 downto 0) := x"00";
 +
 +  --signal num_pak          : unsigned(15 downto 0) := (others => '0');
 +  signal resub_mode    : std_logic := '0';
 +  signal reset_retrans : std_logic;
 +  
++
  begin
  
  ----------------------------------------------------------------------
@@@ -262,8 -247,6 +263,8 @@@
              TX_K_OUT           <= '1';
              current_state      <= SEND_IDLE_H;
              first_idle         <= first_idle;
 +            load_eop           <= '0';
-                     resub_mode <= '0';
++            resub_mode <= '0';
  
            when SEND_IDLE_H =>
              if rx_allow_qtx = '1' or toggle_idle = '1' then