From: Jan Michel Date: Tue, 18 Jul 2017 16:41:33 +0000 (+0200) Subject: Update Serdes settings X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=9d89dc69c187b5400a3fd3ad6fcd0908d63d3abf;p=dirich.git Update Serdes settings --- diff --git a/cores/serdes_sync_0.vhd b/cores/serdes_sync_0.vhd index afcffb8..fe73c09 100644 --- a/cores/serdes_sync_0.vhd +++ b/cores/serdes_sync_0.vhd @@ -114,10 +114,10 @@ architecture v1 of serdes_sync_0 is end component serdes_sync_0rsl_core; -- syn_black_box=1 -- /d/jspc29/lattice/diamond/3.9_x64/ispfpga/sa5p00/data/rsl_core_syn.v(72) component serdes_sync_0sll_core is generic (PPROTOCOL: string := "G8B10B"; - PLOL_SETTING: integer := 3; + PLOL_SETTING: integer := 1; PDYN_RATE_CTRL: string := "DISABLED"; - PDIFF_VAL_LOCK: integer := 262; - PDIFF_VAL_UNLOCK: integer := 393; + PDIFF_VAL_LOCK: integer := 19; + PDIFF_VAL_UNLOCK: integer := 131; PPCLK_TC: integer := 65536; PDIFF_DIV11_VAL_LOCK: integer := 0; PDIFF_DIV11_VAL_UNLOCK: integer := 0; @@ -156,7 +156,7 @@ begin pll_lol <= pll_lol_c; DCU0_inst: component DCUA generic map (D_MACROPDB=>"0b1",D_IB_PWDNB=>"0b1", D_XGE_MODE=>"0b0",D_LOW_MARK=>"0d4",D_HIGH_MARK=>"0d12",D_BUS8BIT_SEL=>"0b0", - D_CDR_LOL_SET=>"0b10",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1", + D_CDR_LOL_SET=>"0b11",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1", D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1", D_SYNC_ND_EN=>"0b0",CH0_UC_MODE=>"0b1",CH0_PCIE_MODE=>"0b0",CH0_RIO_MODE=>"0b0", CH0_WA_MODE=>"0b0",CH0_INVERT_RX=>"0b0",CH0_INVERT_TX=>"0b0",CH0_PRBS_SELECTION=>"0b0", @@ -180,9 +180,9 @@ begin CH0_SEL_SD_RX_CLK=>"0b1",CH0_FF_RX_H_CLK_EN=>"0b0",CH0_FF_RX_F_CLK_DIS=>"0b0", CH0_FF_TX_H_CLK_EN=>"0b0",CH0_FF_TX_F_CLK_DIS=>"0b0",CH0_TDRV_POST_EN=>"0b0", CH0_TX_POST_SIGN=>"0b0",CH0_TX_PRE_SIGN=>"0b0",CH0_REQ_LVL_SET=>"0b00", - CH0_REQ_EN=>"0b0",CH0_RTERM_RX=>"0d11",CH0_RXTERM_CM=>"0b11",CH0_PDEN_SEL=>"0b1", + CH0_REQ_EN=>"0b0",CH0_RTERM_RX=>"0d22",CH0_RXTERM_CM=>"0b11",CH0_PDEN_SEL=>"0b1", CH0_RXIN_CM=>"0b11",CH0_LEQ_OFFSET_SEL=>"0b0",CH0_LEQ_OFFSET_TRIM=>"0b000", - CH0_RLOS_SEL=>"0b1",CH0_RX_LOS_LVL=>"0b010",CH0_RX_LOS_CEQ=>"0b11", + CH0_RLOS_SEL=>"0b1",CH0_RX_LOS_LVL=>"0b000",CH0_RX_LOS_CEQ=>"0b11", CH0_RX_LOS_HYST_EN=>"0b0",CH0_RX_LOS_EN=>"0b1",CH0_LDR_RX2CORE_SEL=>"0b0", CH0_LDR_CORE2TX_SEL=>"0b0",D_TX_MAX_RATE=>"2",CH0_CDR_MAX_RATE=>"2", CH0_TXAMPLITUDE=>"0d800",CH0_TXDEPRE=>"DISABLED",CH0_TXDEPOST=>"DISABLED", @@ -201,7 +201,7 @@ begin D_CMUSETINITVCT=>"0b00",D_CMUSETZGM=>"0b000",D_CMUSETP2AGM=>"0b000", D_CMUSETP1GM=>"0b000",D_CMUSETI4CPZ=>"0d3",D_CMUSETI4CPP=>"0d3",D_CMUSETICP4Z=>"0b101", D_CMUSETICP4P=>"0b01",D_CMUSETBIASI=>"0b00",D_SETPLLRC=>"0d1",CH0_RX_RATE_SEL=>"0d10", - D_REFCK_MODE=>"0b001",D_TX_VCO_CK_DIV=>"0b000",D_PLL_LOL_SET=>"0b11", + D_REFCK_MODE=>"0b001",D_TX_VCO_CK_DIV=>"0b000",D_PLL_LOL_SET=>"0b01", D_RG_EN=>"0b0",D_RG_SET=>"0b00") port map (CH0_HDINP=>hdinp,CH1_HDINP=>n106,CH0_HDINN=>hdinn,CH1_HDINN=>n106, D_TXBIT_CLKP_FROM_ND=>n47,D_TXBIT_CLKN_FROM_ND=>n47,D_SYNC_ND=>n47,D_TXPLL_LOL_FROM_ND=>n47,