From: Jan Michel Date: Thu, 20 Jul 2023 14:33:36 +0000 (+0200) Subject: Couple of changes to MDC OEP X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=9e0b63da642a1bc9d6022d39134a81868fe0b9f2;p=mdcupgrade.git Couple of changes to MDC OEP - add debug features - few general updates --- diff --git a/OEP/config.vhd b/OEP/config.vhd index 76e6373..c659ce3 100644 --- a/OEP/config.vhd +++ b/OEP/config.vhd @@ -29,7 +29,7 @@ package config is constant INCLUDE_SPI : integer := c_NO; constant INCLUDE_ADC : integer := c_YES; constant INCLUDE_I2C : integer := c_YES; - constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; + constant INCLUDE_DEBUG_INTERFACE: integer := c_YES; --input monitor and trigger generation logic constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; diff --git a/OEP/mdcoep.prj b/OEP/mdcoep.prj index 4523d84..4ce1a6c 100644 --- a/OEP/mdcoep.prj +++ b/OEP/mdcoep.prj @@ -14,6 +14,7 @@ set_option -default_enum_encoding sequential set_option -symbolic_fsm_compiler 1 set_option -top_module "mdcoep" set_option -resource_sharing false +set_option -vhdl2008 1 # map options set_option -frequency 120 @@ -128,6 +129,8 @@ add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_rx_reset_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd" diff --git a/OEP/mdcoep.vhd b/OEP/mdcoep.vhd index f2c9e47..d6a14c6 100644 --- a/OEP/mdcoep.vhd +++ b/OEP/mdcoep.vhd @@ -47,10 +47,10 @@ entity mdcoep is ADC_CS : out std_logic; --LED - LED : out std_logic_vector(7 downto 0); + LED : out std_logic_vector(7 downto 0); --Other Connectors - TEST : out std_logic_vector(8 downto 1) + IO : inout std_logic_vector(8 downto 1) ); @@ -98,6 +98,7 @@ architecture arch of mdcoep is signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + signal hub_stat_debug : std_logic_vector(31 downto 0); signal sed_error_i : std_logic; signal bus_master_active : std_logic; @@ -139,6 +140,7 @@ begin THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync_2 generic map( + USE_NEW_ECP5_RESET => 0, DUAL => 0, IS_SYNC_SLAVE => (c_YES,c_NO) ) @@ -178,6 +180,7 @@ begin --------------------------------------------------------------------------- THE_DOWN_INTERFACE_2 : entity work.med_ecp5_sfp_sync_2 generic map( + USE_NEW_ECP5_RESET => 0, DUAL => 1, IS_SYNC_SLAVE => (c_NO,c_NO) @@ -215,13 +218,14 @@ begin MII_IS_UPLINK => (1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), MII_IS_DOWNLINK => (0,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0), MII_IS_UPLINK_ONLY => (1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), + HUB_CTRL_BROADCAST_BITMASK => x"FA", --hub and mdc USE_ONEWIRE => c_I2C, HARDWARE_VERSION => HARDWARE_INFO, INCLUDED_FEATURES => INCLUDED_FEATURES, INIT_ENDPOINT_ID => x"0005", INIT_CTRL_REGS => x"00000000_00000000_00000000_00000000" & x"00000000_00000000_00000000_00000000" & - x"00000000_00000000_800a4000_00000000" & + x"00000000_00000000_800a2000_00000000" & x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF", CLOCK_FREQUENCY => CLOCK_FREQUENCY, BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR, @@ -268,7 +272,7 @@ begin --Status ports (for debugging) MPLEX_CTRL => (others => '0'), CTRL_DEBUG => (others => '0'), - STAT_DEBUG => open + STAT_DEBUG => hub_stat_debug ); gen_media_record : for i in 0 to INTERFACE_NUM-1 generate @@ -354,8 +358,11 @@ begin ADC_CLK => ADC_SCK, --I2C HEADER_IO(7) => SFP_MOD2, - HEADER_IO(8) => SFP_MOD1, - --Trigger & Monitor + HEADER_IO(8) => SFP_MOD1, + HEADER_IO(9) => IO(1), --uart rx + HEADER_IO(10) => IO(2), --uart tx + + --Trigger & Monitor MONITOR_INPUTS => monitor_inputs_i, TRIG_GEN_INPUTS => trigger_inputs_i, TRIG_GEN_OUTPUTS(1 downto 0) => open, @@ -383,11 +390,15 @@ begin monitor_inputs_i <= (others => '0'); trigger_inputs_i <= (others => '0'); +IO(3) <= GPIO(1) when rising_edge(clk_sys); +IO(4) <= med_dataready_in(1); +IO(5) <= hub_stat_debug(8); +IO(6) <= GPIO(5) when rising_edge(clk_sys); +IO(7) <= med_dataready_in(3); +IO(8) <= hub_stat_debug(9); +--IO(7) <= hub_stat_debug(8); +--IO(8) <= hub_stat_debug(9); --- TEST(1) <= ADC_CS; --- TEST(2) <= ADC_MOSI; --- TEST(3) <= ADC_MISO; --- TEST(4) <= ADC_SCK; --------------------------------------------------------------------------- -- LED diff --git a/pinout/oep.lpf b/pinout/oep.lpf index 7686d07..ee7d3e2 100644 --- a/pinout/oep.lpf +++ b/pinout/oep.lpf @@ -68,16 +68,16 @@ LOCATE COMP "LED_7" SITE "K20"; DEFINE PORT GROUP "LED_group" "LED*"; IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 ; -LOCATE COMP "TEST_1" SITE "U19"; -LOCATE COMP "TEST_2" SITE "N20"; -LOCATE COMP "TEST_3" SITE "U20"; -LOCATE COMP "TEST_4" SITE "M20"; -LOCATE COMP "TEST_5" SITE "T20"; -LOCATE COMP "TEST_6" SITE "L20"; -LOCATE COMP "TEST_7" SITE "R20"; -LOCATE COMP "TEST_8" SITE "P20"; -DEFINE PORT GROUP "TEST_group" "TEST*"; -IOBUF GROUP "TEST_group" IO_TYPE=LVCMOS25 ; +LOCATE COMP "IO_1" SITE "U19"; +LOCATE COMP "IO_2" SITE "N20"; +LOCATE COMP "IO_3" SITE "U20"; +LOCATE COMP "IO_4" SITE "M20"; +LOCATE COMP "IO_5" SITE "T20"; +LOCATE COMP "IO_6" SITE "L20"; +LOCATE COMP "IO_7" SITE "R20"; +LOCATE COMP "IO_8" SITE "P20"; +DEFINE PORT GROUP "IO_group" "IO*"; +IOBUF GROUP "IO_group" IO_TYPE=LVCMOS25 ; LOCATE COMP "TMP_ALERT" SITE "A12"; @@ -100,4 +100,3 @@ LOCATE COMP "ADC_CS" SITE "B20"; DEFINE PORT GROUP "ADC_group" "ADC*"; IOBUF GROUP "ADC_group" IO_TYPE=LVCMOS25 ; -