From: Jan Michel <jan@mueschelsoft.de>
Date: Thu, 10 Apr 2014 12:50:07 +0000 (+0200)
Subject: few bugfixes to USB sctrl
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=9e68171b18ada528c8b074e3828761bd9ffe2d82;p=padiwa.git

few bugfixes to USB sctrl
---

diff --git a/pulser/padiwa_pulser.vhd b/pulser/padiwa_pulser.vhd
index dc062fe..d53a57e 100644
--- a/pulser/padiwa_pulser.vhd
+++ b/pulser/padiwa_pulser.vhd
@@ -98,11 +98,11 @@ THE_UART : entity work.uart_sctrl
 
 PROC_REGISTERS : process begin
   wait until rising_edge(clk_i);
-  if WRITE_IN = '1' then
+  if bus_write= '1' then
     if uart_addr = x"01" then
       lcd_data_i(31 downto 0) <= uart_rx_data;
     elsif uart_addr = x"02" then
-      lcd_data_i(79 downto 64) <= uart_rx_data;
+      lcd_data_i(79 downto 64) <= uart_rx_data(15 downto 0);
     end if;
   end if;
 end process;
diff --git a/source/uart_rec.vhd b/source/uart_rec.vhd
index 28a9f1c..5edbaf0 100644
--- a/source/uart_rec.vhd
+++ b/source/uart_rec.vhd
@@ -73,10 +73,10 @@ DEBUG(3) <= '0';
   clock_division : process begin
     wait until rising_edge(CLK);
     -- scaling down the main clock to the desired baudrate
-    if clk_div_counter < CLK_DIV-1 then
-      clk_div_counter <= clk_div_counter + 1;
-    else
+    if clk_div_counter = CLK_DIV-1 then
       clk_div_counter <= x"0000";
+    else
+      clk_div_counter <= clk_div_counter + 1;
     end if;
     -- generates symbol_pulse, a signal that has 1 clock cycle pulses, one symbol duration period apart 
     -- in contrast to the transceiver module, the symbol pulse is generated in the middle of the
diff --git a/source/uart_sctrl.vhd b/source/uart_sctrl.vhd
index c4b6221..380b758 100644
--- a/source/uart_sctrl.vhd
+++ b/source/uart_sctrl.vhd
@@ -39,7 +39,7 @@ signal rx_ready  : std_logic;
 signal tx_send   : std_logic;
 signal tx_ready  : std_logic;
 
-type   rx_state_t is (IDLE,ADDR,GET_BYTE0,GET_BYTE1,GET_BYTE2,GET_BYTE3,DO_WRITE,DO_READ,SEND_BYTE0,SEND_BYTE1,SEND_BYTE2);
+type   rx_state_t is (IDLE,GET_ADDR,GET_BYTE0,GET_BYTE1,GET_BYTE2,GET_BYTE3,DO_WRITE,DO_READ,SEND_BYTE0,SEND_BYTE1,SEND_BYTE2);
 signal state     : rx_state_t;
 signal addr      : std_logic_vector(7 downto 0) := (others => '0');
 signal word      : std_logic_vector(31 downto 0) := (others => '0');
@@ -82,7 +82,7 @@ PROC_RX : process begin
       cmd_rd <= '0';
       cmd_wr <= '0';
       if rx_ready = '1' then
-        state <= ADDR;
+        state <= GET_ADDR;
         if rx_data = x"52" then
           cmd_rd <= '1';
         elsif rx_data = x"57" then
@@ -92,7 +92,7 @@ PROC_RX : process begin
         end if;
       end if;
 
-    when ADDR  =>
+    when GET_ADDR  =>
       if rx_ready = '1' then
         addr <= rx_data;
         if cmd_wr = '1' then
diff --git a/source/uart_trans.vhd b/source/uart_trans.vhd
index c50dc0a..8b5afbb 100644
--- a/source/uart_trans.vhd
+++ b/source/uart_trans.vhd
@@ -77,10 +77,10 @@ DEBUG(3) <= '0';
   clock_division : process begin
     wait until rising_edge(CLK);
     -- scaling down the main clock to the desired baudrate
-    if clk_div_counter < CLK_DIV-1 then
-      clk_div_counter <= clk_div_counter + 1;
-    else
+    if clk_div_counter = CLK_DIV-1 then
       clk_div_counter <= x"0000";
+    else
+      clk_div_counter <= clk_div_counter + 1;
     end if;