From: hadaq <hadaq>
Date: Fri, 17 Sep 2010 10:26:32 +0000 (+0000)
Subject: large delay
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=9fafff9b6d47eee142bf1f4bf4947ea471adade0;p=daqdocu.git

large delay
---

diff --git a/cts.tex b/cts.tex
index c1b0687..e0c4db6 100644
--- a/cts.tex
+++ b/cts.tex
@@ -26,9 +26,9 @@ For all registers described in this subsection refer to the Fig.\ref{cts_logic}
   \item [0xA0C1] LVL1/LVL2 trigger settings:
     \begin{description}
      \item[Bit 7 -- 0] How many lvl1 events wait to send lvl2 trigger
-     \item[Bit 16 -- 12] Delay of MDCB trigger = value * 40 ns 
-     \item[Bit 21 -- 17] Delay of MDCA trigger = value * 40 ns 
-     \item[Bit 31 -- 28] LVL1 trigger width, when value < 7 then width = 120 + Value*10 ns else width = Value*10ns
+     \item[Bit 16 -- 12] Delay (to the fastes trigger) of MDCB trigger = value * 20 ns 
+     \item[Bit 21 -- 17] Delay of MDCA trigger = value * 20 ns 
+     \item[Bit 31 -- 28] LVL1 trigger width, when value < 7 then width = 105 + Value*5 ns else width = Value*5ns
     \end{description}
   \item [0xA0C2] Multiplexers output select:
     \begin{description}
@@ -66,6 +66,7 @@ For all registers described in this subsection refer to the Fig.\ref{cts_logic}
      \item[Bit 6 -- 0] LVL1 trigger information(6 -- 0)
      \item[Bit 13 -- 8] LVL1 trigger information(13 -- 8)
     \end{description}
+  \item [0xA0E7 -- 0xA0E5] Large delays
 
 \end{description}