From: Michael Boehmer <mboehmer@ph.tum.de>
Date: Sat, 27 Nov 2021 21:46:53 +0000 (+0100)
Subject: signal description added
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=9fbd0e4ca4e8970140d120cf0bc8daca91387459;p=daqdocu.git

signal description added
---

diff --git a/trb3/DS_LinkEstablishment.tex b/trb3/DS_LinkEstablishment.tex
index 874c62d..9d86817 100644
--- a/trb3/DS_LinkEstablishment.tex
+++ b/trb3/DS_LinkEstablishment.tex
@@ -38,10 +38,10 @@ The link establishment process is explained on a hub FPGA slave port as example:
   \item CTS MP: the toggling IDLEs are received, a RX reset sequence is performed and a lock
   to WAP=0 made. This will set LINK{\_}RX{\_}READY in the master port, and change the toggling IDLEs in the uplink
   to steady IDLEs (IDLE1).
-  \item HUB SP: The RX LSM detects a series of steady IDLEs, and switches to LINK{\_}FULL{\_}DONE internally.
+  \item HUB SP: The RX LSM detects a series of steady IDLEs, and sets LINK{\_}FULL{\_}DONE internally.
   The TX control is instructed to send steady IDLEs now. Both UP and DL are considered stable, and TrbNet
   payloads (as well as special kommas) can be sent and received now.
-  \item CTS MP: The RX LSM detects a series of steady IDLEs, and switches to LINK{\_}FULL{\_}DONE internally.
+  \item CTS MP: The RX LSM detects a series of steady IDLEs, and sets to LINK{\_}FULL{\_}DONE internally.
   Both UP and DL are considered stable, and TrbNet payloads as well as special kommas are enabled now. 
 \end{itemize*}
 
diff --git a/trb3/DS_SignalDescription.tex b/trb3/DS_SignalDescription.tex
new file mode 100644
index 0000000..aa0b883
--- /dev/null
+++ b/trb3/DS_SignalDescription.tex
@@ -0,0 +1,20 @@
+\subsection{Signal Description}
+
+In the new media interface several signals were introduced to provide
+status information and steer the state machines.
+
+The signals used in the SerDes TX and RX state machines are taken from the LatticeSemi
+example code available on the web. These state machines behave the same, but have been extended 
+to include TX channel serializer synchronization and RX channel WordAlignment.
+
+\begin{itemize*}
+  \item \texttt{LINK\_TX\_READY} is set when the TX PLLs inside \textbf{all used} QUADs are locked, 
+  the serializers are synced and kommas can be transmitted.
+  \item \texttt{LINK\_RX\_READY} is set when the RX CDR of \textbf{one specific} SerDes is locked, 
+  correct word alignment is found and kommas can be received.
+  \item \texttt{LINK\_HALF\_DONE} is set when a SerDes has received a sequence of at least 16 toggling
+  idles.
+  \item \texttt{LINK\_FULL\_DONE} is set when a SerDes has received a sequence of at least 16 steady
+  idles after having set the \texttt{LINK\_HALF\_DONE} signal.
+  \item \texttt{xxx}
+\end{itemize*}
diff --git a/trb3/main.tex b/trb3/main.tex
index 53a04d4..f5e156c 100644
--- a/trb3/main.tex
+++ b/trb3/main.tex
@@ -87,7 +87,7 @@
 
 \title{A Users Guide\\to the TRB3 \\and FPGA-TDC Based Platforms}
 \date{\today ~-~\thistime}
-\author{Grzegorz Korcyl, Ludwig Maier, Jan Michel, Andreas Neiser, Marek Palka, \\Manuel Penschuck, Pawel Strzempek, Michael Traxler, Cahit Ugur}
+\author{Michael Böhmer, Grzegorz Korcyl, Ludwig Maier, Jan Michel, \\Andreas Neiser, Marek Palka, Manuel Penschuck, \\Pawel Strzempek, Michael Traxler, Cahit Ugur}
 
 
 \newcommand{\files}[1]{\texttt{#1}}
@@ -287,6 +287,7 @@
     \input{DS_GoingSynchronous.tex}
     \input{DS_NewResets.tex}
     \input{DS_LinkEstablishment.tex}
+    \input{DS_SignalDescription.tex}
     
 \cleardoublepage
 \begin{appendices}