From: Cahit <c.ugur@gsi.de>
Date: Thu, 23 Jan 2014 15:21:51 +0000 (+0100)
Subject: Calibration trigger for the reference channel
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=a03b03f69f3b4a319f94f9e6bf0527cebcafc2a3;p=trb3.git

Calibration trigger for the reference channel
---

diff --git a/tdc_releases/tdc_v1.6/Readout.vhd b/tdc_releases/tdc_v1.6/Readout.vhd
index a155fd1..da6d8d7 100644
--- a/tdc_releases/tdc_v1.6/Readout.vhd
+++ b/tdc_releases/tdc_v1.6/Readout.vhd
@@ -5,7 +5,7 @@
 -- File       : Readout.vhd
 -- Author     : cugur@gsi.de
 -- Created    : 2012-10-25
--- Last update: 2014-01-22
+-- Last update: 2014-01-23
 -------------------------------------------------------------------------------
 -- Description: 
 -------------------------------------------------------------------------------
@@ -416,8 +416,8 @@ begin  -- behavioral
             wr_header_fsm <= '1';
             readout_fsm   <= '1';
           else                             -- the other triggers
-            data_finished_fsm <= '1';
             RD_NEXT           <= SEND_TRIG_RELEASE_A;
+            data_finished_fsm <= '1';
           end if;
         elsif INVALID_TRG_IN = '1' then    -- invalid trigger
           RD_NEXT           <= SEND_TRIG_RELEASE_A;
@@ -452,7 +452,7 @@ begin  -- behavioral
           if DEBUG_MODE_EN_IN = '1' then  -- send status after channel data
             RD_NEXT <= SEND_STATUS;
           else
-            RD_NEXT <= WAIT_FOR_DATA_FINISHED; -- WAIT_FOR_LVL1_TRIG_A;
+            RD_NEXT <= WAIT_FOR_LVL1_TRIG_A;
           end if;
         else                            -- go to the next channel
           fifo_nr_rd_fsm <= fifo_nr_rd + 1;
@@ -461,12 +461,12 @@ begin  -- behavioral
         readout_fsm      <= '1';
         rd_fsm_debug_fsm <= x"4";
 
-      when WAIT_FOR_DATA_FINISHED =>    -- wait until the end of the data transfer 
-        if finished_i = '1' then
-          RD_NEXT <= WAIT_FOR_LVL1_TRIG_A;
-        end if;
-        wait_fsm         <= '1';
-        rd_fsm_debug_fsm <= x"5";
+      --when WAIT_FOR_DATA_FINISHED =>    -- wait until the end of the data transfer 
+      --  if finished_i = '1' then
+      --    RD_NEXT <= WAIT_FOR_LVL1_TRIG_A;
+      --  end if;
+      --  wait_fsm         <= '1';
+      --  rd_fsm_debug_fsm <= x"5";
         
       when WAIT_FOR_LVL1_TRIG_A =>      -- wait for trigger data valid
         if TRG_DATA_VALID_IN = '1' then
@@ -486,18 +486,19 @@ begin  -- behavioral
         if SPURIOUS_TRG_IN = '1' then
           wrong_readout_fsm <= '1';
         end if;
-        RD_NEXT          <= SEND_TRIG_RELEASE_A;
-        wait_fsm         <= '1';
-        rd_fsm_debug_fsm <= x"8";
+        RD_NEXT           <= SEND_TRIG_RELEASE_A;
+        data_finished_fsm <= '1';
+        wait_fsm          <= '1';
+        rd_fsm_debug_fsm  <= x"8";
 
       when SEND_STATUS =>
         if stop_status_i = '1' then
           if DEBUG_MODE_EN_IN = '1' then
             RD_NEXT <= WAIT_FOR_LVL1_TRIG_A;
           else
-            RD_NEXT <= SEND_TRIG_RELEASE_A;
-          end if;
-          data_finished_fsm <= '1';
+            RD_NEXT           <= SEND_TRIG_RELEASE_A;
+            data_finished_fsm <= '1';
+          end if;          
         else
           wr_status_fsm <= '1';
         end if;
@@ -700,7 +701,7 @@ begin  -- behavioral
   DATA_OUT                    <= data_out_reg;
   DATA_WRITE_OUT              <= data_wr_reg;
   finished_i                  <= (data_finished or wr_finished_2reg) when rising_edge(CLK_100);
-  DATA_FINISHED_OUT           <= finished_i;
+  DATA_FINISHED_OUT           <= data_finished; --finished_i;
   TRG_RELEASE_OUT             <= trig_release_reg;
   TRG_STATUSBIT_OUT           <= (others => '0');
   READOUT_DEBUG(3 downto 0)   <= rd_fsm_debug;
diff --git a/tdc_releases/tdc_v1.6/TDC.vhd b/tdc_releases/tdc_v1.6/TDC.vhd
index 497b631..c376f3e 100644
--- a/tdc_releases/tdc_v1.6/TDC.vhd
+++ b/tdc_releases/tdc_v1.6/TDC.vhd
@@ -118,7 +118,7 @@ architecture TDC of TDC is
 -- Logic analyser
   signal logic_anal_data_i            : std_logic_vector(3*32-1 downto 0);
 -- Hit signals
-  signal hit_in_i                     : std_logic_vector(CHANNEL_NUMBER-1 downto 1);
+  signal hit_in_i                     : std_logic_vector(CHANNEL_NUMBER-1 downto 0);
   signal hit_latch                    : std_logic_vector(CHANNEL_NUMBER-1 downto 1) := (others => '0');
   signal hit_reg                      : std_logic_vector(CHANNEL_NUMBER-1 downto 1);
   signal hit_2reg                     : std_logic_vector(CHANNEL_NUMBER-1 downto 1);
@@ -223,6 +223,16 @@ begin
     end process;
   end generate GEN_Channel_Enable;
 
+  -- purpose: Calibration trigger for the reference channel
+  process (calibration_on, HIT_CALIBRATION) is
+  begin  -- process
+    if calibration_on = '1' then
+          hit_in_i(0) <= HIT_CALIBRATION;
+        else
+          hit_in_i(0) <= REFERENCE_TIME;
+        end if;
+  end process;
+
   CalibrationSwitch : process (CLK_READOUT)
   begin
     if rising_edge(CLK_READOUT) then
@@ -279,7 +289,7 @@ begin
         RESET_COUNTERS          => reset_counters_i,
         CLK_200                 => CLK_TDC,
         CLK_100                 => CLK_READOUT,
-        HIT_IN                  => REFERENCE_TIME,
+        HIT_IN                  => hit_in_i(0), --REFERENCE_TIME,
         TRIGGER_WIN_END_TDC     => trig_win_end_tdc,
         TRIGGER_WIN_END_RDO     => trig_win_end_rdo,
         EPOCH_COUNTER_IN        => epoch_cntr,