From: Jan Michel <j.michel@gsi.de>
Date: Thu, 23 Jul 2020 14:25:16 +0000 (+0200)
Subject: extend stretcher option in trigger logic
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=a0798a6ea564061b1b9828133e8eb92405b173f5;p=trb3.git

extend stretcher option in trigger logic
---

diff --git a/base/code/input_to_trigger_logic_record.vhd b/base/code/input_to_trigger_logic_record.vhd
index e3e25f4..8ab3b2b 100644
--- a/base/code/input_to_trigger_logic_record.vhd
+++ b/base/code/input_to_trigger_logic_record.vhd
@@ -22,6 +22,7 @@ end entity;
 
 
 architecture input_to_trigger_logic_arch of input_to_trigger_logic_record is
+constant USE_EXTENDED_STRETCHER : integer := c_YES;
 constant register_bits : integer := (INPUTS-1)/32*32+32-1;
 type reg_t is array(0 to OUTPUTS-1) of std_logic_vector(register_bits downto 0);
 signal enable : reg_t := (others => (others => '0'));
@@ -49,6 +50,7 @@ signal got_simplecoin  : std_logic;
 signal coin_enable  : std_logic  := '0';
 signal current_multiplicity0, current_multiplicity1 : unsigned(7 downto 0);
 signal current_multiplicity, set_multiplicity       : unsigned(7 downto 0);
+signal set_stretcher                                : unsigned(5 downto 0);
 signal multiplicity_trigger : std_logic := '0';
 signal multiplicity_enable  : std_logic_vector(register_bits downto 0);
 signal mult_gated           : std_logic_vector(INPUTS-1 downto 0);
@@ -60,6 +62,7 @@ type coincidence_arr is array(0 to 16) of integer range 0 to 63;
 signal coincidence_config_1, coincidence_config_2 : coincidence_arr;
 signal coincidence_enable : std_logic_vector(15 downto 0);
 
+
 begin
 THE_CONTROL : process 
   variable outchan : integer range 0 to 7;
@@ -120,6 +123,8 @@ begin
       edge_enable     <= BUS_RX.data(31 downto 24);
     elsif BUS_RX.addr(6 downto 0) = "0110101" and INPUTS > 32 then
       multiplicity_enable(63 downto 32) <= BUS_RX.data;
+    elsif BUS_RX.addr(6 downto 0) = "0110110" then
+      set_stretcher <= unsigned(BUS_RX.data(5 downto 0));
     else
       BUS_TX.nack <= '1'; 
       BUS_TX.ack  <= '0';
@@ -185,6 +190,8 @@ begin
       BUS_TX.data <= edge_enable & set_output_coin & set_output_mult & set_output_simplecoin;
     elsif BUS_RX.addr(6 downto 0) = "0110101" and INPUTS > 32 then
       BUS_TX.data                 <= multiplicity_enable(63 downto 32);
+    elsif BUS_RX.addr(6 downto 0) = "0110110" then
+      BUS_TX.data                 <= x"000000" & "00" & std_logic_vector(set_stretcher);
     else  
       BUS_TX.nack <= '1'; 
       BUS_TX.ack  <= '0';
@@ -206,9 +213,34 @@ end generate;
 ----------------------------
 inp_inv           <= INPUT xor invert(INPUTS-1 downto 0);
 inp_long          <= inp_shift(0) or inp_shift(1);
-inp_verylong      <= inp_shift(1) or inp_shift(2) or inp_shift(3) or inp_shift(4) when rising_edge(CLK);
 
 inp_edge          <= not inp_shift(1) and inp_shift(2) when rising_edge(CLK);
+
+----------------------------
+--  Extended Stretcher
+----------------------------
+gen_short_stretch : if USE_EXTENDED_STRETCHER = c_NO generate
+  inp_verylong      <= inp_shift(1) or inp_shift(2) or inp_shift(3) or inp_shift(4) when rising_edge(CLK);
+end generate;
+gen_long_stretch : if USE_EXTENDED_STRETCHER = c_YES generate
+  type stretchcnt_arr is array(0 to INPUTS-1) of unsigned(5 downto 0);
+  signal stretchcnt : stretchcnt_arr;
+begin
+  gen_long_stretchers : for i in 0 to INPUTS-1 generate
+    process begin
+      wait until rising_edge(CLK);
+      if inp_shift(1)(i) = '1' then
+        stretchcnt(i) <= set_stretcher;
+        inp_verylong(i) <= '1';
+      elsif stretchcnt(i) > 0 then
+        stretchcnt(i) <= stretchcnt(i) - 1;
+      else
+        inp_verylong(i) <= '0';
+      end if;  
+    end process;
+  end generate;
+end generate;
+
 ----------------------------
 --  Outputs
 ----------------------------