From: hadeshyp <hadeshyp>
Date: Fri, 17 Aug 2012 09:51:57 +0000 (+0000)
Subject: *** empty log message ***
X-Git-Tag: oldGBE~39
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=a0f32cc7b78a91ad8234fdea4d7b3ddd37c113b3;p=trbnet.git

*** empty log message ***
---

diff --git a/special/spi_ltc2600.vhd b/special/spi_ltc2600.vhd
index 766394b..57c3f70 100644
--- a/special/spi_ltc2600.vhd
+++ b/special/spi_ltc2600.vhd
@@ -42,6 +42,7 @@ architecture spi_ltc2600_arch of spi_ltc2600 is
   signal word_count : integer range 0 to 31;
   signal bit_count  : integer range 0 to 31;
   signal time_count : integer range 0 to 7;
+  signal readback   : std_logic_vector(31 downto 0);
   
   type fsm_t is (IDLE, WAIT_STATE, SET, FINISH);
   signal fsm_state : fsm_t;
@@ -81,6 +82,8 @@ begin
           BUS_DATA_OUT <= ram(addr);
         elsif BUS_ADDR_IN(0) = '1' then
           BUS_DATA_OUT <= ctrl_reg;
+        elsif BUS_ADDR_IN(1) = '1' then
+          BUS_DATA_OUT <= readback;
         else --if BUS_ADDR_IN(1) = '0' then
           BUS_DATA_OUT(15 downto 0) <= chipselect_reg;
           BUS_DATA_OUT(31 downto 16) <= x"0000";
@@ -139,11 +142,13 @@ begin
           end if;
         else
           fsm_state  <= WAIT_STATE;
+          readback   <= readback(30 downto 0) & SPI_SDI_IN;          
         end if;
       when FINISH =>
         if time_count = 0 and spi_sck = '0' then
           time_count <= 7;
           spi_sck    <= not spi_sck;
+          readback   <= readback(30 downto 0) & SPI_SDI_IN;          
         elsif time_count = 0 and spi_sck = '1' then
           fsm_state  <= IDLE;
         else
diff --git a/trb_net_onewire.vhd b/trb_net_onewire.vhd
index 5d66d63..8c0c801 100644
--- a/trb_net_onewire.vhd
+++ b/trb_net_onewire.vhd
@@ -49,7 +49,7 @@ architecture trb_net_onewire_arch of trb_net_onewire is
   signal recv_bit_ready, next_recv_bit_ready : std_logic;
   signal output_tmp, next_output_tmp : std_logic;
   signal word : std_logic_vector(15 downto 0);
-  signal ram_addr : std_logic_vector(2 downto 0);
+  signal ram_addr : std_logic_vector(2 downto 0) := "000";
   signal ram_wr : std_logic;
   signal send_rom, next_send_rom : std_logic;
   signal conv_temp, next_conv_temp : std_logic;