From: Michael Boehmer <mboehmer@ph.tum.de>
Date: Wed, 27 Apr 2022 09:18:31 +0000 (+0200)
Subject: on the way...
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=a0f3cdfe6a24ac2ed6c0aa5e60e11e7e784e58f8;p=trbnet.git

on the way...
---

diff --git a/special/clockbox.vhd b/special/clockbox.vhd
index 6c6f4d1..596f1e4 100644
--- a/special/clockbox.vhd
+++ b/special/clockbox.vhd
@@ -23,12 +23,6 @@ architecture clockbox_arch of clockbox is
 -- state machine signals
 
 -- Signals
-  signal ping_i         : std_logic;
-  signal pong_i         : std_logic;
-  signal ping_q         : std_logic;
-  signal pong_q         : std_logic;
-  signal ping_qq        : std_logic;
-  signal pong_qq        : std_logic;
 
   attribute HGROUP : string;
   attribute BBOX   : string;
@@ -41,21 +35,20 @@ architecture clockbox_arch of clockbox is
   
 begin
 
----------------------------------------------------------------------------
--- we want all logic in here in one PFU (defined timing)!
----------------------------------------------------------------------------
+  THE_PING_POINT: entity clockpoint
+  port map(
+    SAMPLE_CLK    => SAMPLE_CLK,
+    DATA_IN       => PING_IN,
+    CLK_DATA      => CLK_PING,
+    DATA_OUT      => PING_OUT
+  );
 
-  ping_i  <= PING_IN when rising_edge(CLK_PING);
-  pong_i  <= PONG_IN when rising_edge(CLK_PONG);
-  ping_q  <= ping_i when rising_edge(SAMPLE_CLK);
-  pong_q  <= pong_i when rising_edge(SAMPLE_CLK);
-  ping_qq <= ping_q when rising_edge(SAMPLE_CLK);
-  pong_qq <= pong_q when rising_edge(SAMPLE_CLK);
-  
----------------------------------------------------------------------------
--- outputs
----------------------------------------------------------------------------
-  PING_OUT <= ping_qq;
-  PONG_OUT <= pong_qq;
+  THE_PONG_POINT: entity clockpoint
+  port map(
+    SAMPLE_CLK    => SAMPLE_CLK,
+    DATA_IN       => PONG_IN,
+    CLK_DATA      => CLK_PONG,
+    DATA_OUT      => PONG_OUT
+  );
 
 end architecture;
diff --git a/special/clockpoint.vhd b/special/clockpoint.vhd
new file mode 100644
index 0000000..3d5bf6f
--- /dev/null
+++ b/special/clockpoint.vhd
@@ -0,0 +1,51 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+
+entity clockpoint is
+  port(
+    SAMPLE_CLK    : in  std_logic;
+    DATA_IN       : in  std_logic;
+    CLK_DATA      : in  std_logic;
+    DATA_OUT      : out std_logic
+  );
+end entity clockpoint;
+
+architecture clockpoint_arch of clockpoint is
+
+-- Components
+
+-- state machine signals
+
+-- Signals
+  signal data_i         : std_logic;
+  signal data_q         : std_logic;
+  signal data_qq        : std_logic;
+
+  attribute HGROUP : string;
+  attribute BBOX   : string;
+  attribute HGROUP of clockpoint_arch : architecture is "clockpoint_group";
+  attribute BBOX   of clockpoint_arch : architecture is "1,1";
+  attribute syn_sharing : string;
+  attribute syn_sharing of clockpoint_arch : architecture is "off";
+  attribute syn_hier : string;
+  attribute syn_hier of clockpoint_arch : architecture is "hard";
+  
+begin
+
+---------------------------------------------------------------------------
+-- we want all logic in here in one PFU (defined timing)!
+---------------------------------------------------------------------------
+
+  data_i  <= DATA_IN when rising_edge(CLK_DATA);
+  data_q  <= data_i when rising_edge(SAMPLE_CLK);
+  data_qq <= data_q when rising_edge(SAMPLE_CLK);
+  
+---------------------------------------------------------------------------
+-- outputs
+---------------------------------------------------------------------------
+  DATA_OUT <= data_qq;
+
+end architecture;