From: Jan Michel Date: Fri, 22 Nov 2019 13:52:05 +0000 (+0100) Subject: update ADC AddOn with 200 Mhz on Trb3sc X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=a123220d7dc9c3bdd6ceb1721440ee3ee4b0c11b;p=trb3.git update ADC AddOn with 200 Mhz on Trb3sc --- diff --git a/ADC/source/adc_ad9219.vhd b/ADC/source/adc_ad9219.vhd index 29b8637..54e5b01 100644 --- a/ADC/source/adc_ad9219.vhd +++ b/ADC/source/adc_ad9219.vhd @@ -71,18 +71,18 @@ begin -- LOCK => lock(0) -- ); -gen_240_to_200 : if IS_TRB3 = 0 generate - THE_ADC_PLL_0 : entity work.pll_adc10bit - port map( - CLK => CLK_ADCRAW, - CLKOP => clk_adcfast_i, - LOCK => lock(1) - ); -end generate; - -gen_no_pll : if IS_TRB3 = 1 generate +-- gen_240_to_200 : if IS_TRB3 = 0 generate +-- THE_ADC_PLL_0 : entity work.pll_adc10bit +-- port map( +-- CLK => CLK_ADCRAW, +-- CLKOP => clk_adcfast_i, +-- LOCK => lock(1) +-- ); +-- end generate; +-- +-- gen_no_pll : if IS_TRB3 = 1 generate clk_adcfast_i <= CLK_ADCRAW; -end generate; +-- end generate; restart_i <= RESTART_IN when rising_edge(clk_data); diff --git a/ADC/source/adc_handler.vhd b/ADC/source/adc_handler.vhd index 6c02ed4..6f9ece4 100644 --- a/ADC/source/adc_handler.vhd +++ b/ADC/source/adc_handler.vhd @@ -229,7 +229,7 @@ end generate; TRIGGER_FLAG_OUT <= or_all(adc_trigger); ADCSPI_CTRL <= ctrl_reg(7 downto 0); - +adc_restart <= ctrl_reg(8); adc_stop <= buffer_ctrl_reg(0); config.baseline_always_on <= buffer_ctrl_reg(4); diff --git a/ADC/source/adc_processor.vhd b/ADC/source/adc_processor.vhd index 2d30c7e..c0af59d 100644 --- a/ADC/source/adc_processor.vhd +++ b/ADC/source/adc_processor.vhd @@ -899,10 +899,10 @@ end architecture; -- block_scale : unsigned_array_8(0 to 3); -- end record; --- 0-ACVVVV -- ADC data, 16 bit data, MSN=0x0 +-- 0-ACVVVV -- ADC data, 16 bit data, MSN=0x0, A: ADC, C: channel -- vVVVvVVV -- ADC data, 2x 15 bit only after 0x0 channel header, MSB=1 -- VVVVVVVV -- ADC data 2x 16 bit, only after 0x4 channel header -- 1SSSSSSS -- Status word, MSN=0x1 --- 4-AC--LL -- ADC Header, L: number of data words that follow, MSN=0x4 +-- 4PACLLLL -- ADC Header, L: number of data words that follow, MSN=0x4, P: '3' if PSA -- 2RRVVVVV -- Configuration data -- 3-ACVVVV -- Processed values diff --git a/base/cores/pll_in240_out40.ipx b/base/cores/pll_in240_out40.ipx new file mode 100644 index 0000000..827d62e --- /dev/null +++ b/base/cores/pll_in240_out40.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/base/cores/pll_in240_out40.lpc b/base/cores/pll_in240_out40.lpc new file mode 100644 index 0000000..4e6e893 --- /dev/null +++ b/base/cores/pll_in240_out40.lpc @@ -0,0 +1,69 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-6FN1156C +SpeedGrade=6 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PLL +CoreRevision=5.8 +ModuleName=pll_in240_out40 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=06/10/2016 +Time=12:38:40 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=None +Order=None +IO=0 +Type=ehxpllb +mode=normal +IFrq=240 +Div=6 +ClkOPBp=0 +Post=16 +U_OFrq=40 +OP_Tol=0.0 +OFrq=40.000000 +DutyTrimP=Rising +DelayMultP=0 +fb_mode=CLKOP +Mult=1 +Phase=0.0 +Duty=8 +DelayMultS=0 +DPD=50% Duty +DutyTrimS=Rising +DelayMultD=0 +ClkOSDelay=0 +PhaseDuty=Static +CLKOK_INPUT=CLKOP +SecD=2 +U_KFrq=50 +OK_Tol=0.0 +KFrq= +ClkRst=0 +PCDR=0 +FINDELA=0 +VcoRate= +Bandwidth=2.191564 +;DelayControl=No +EnCLKOS=0 +ClkOSBp=0 +EnCLKOK=0 +ClkOKBp=0 +enClkOK2=0 + +[Command] +cmd_line= -w -n pll_in240_out40 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 240 -phase_cntl STATIC -fclkop 40 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw diff --git a/base/cores/pll_in240_out40.vhd b/base/cores/pll_in240_out40.vhd new file mode 100644 index 0000000..5ae78c3 --- /dev/null +++ b/base/cores/pll_in240_out40.vhd @@ -0,0 +1,95 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.7.1.502 +-- Module Version: 5.7 +--/d/jspc29/lattice/diamond/3.7_x64/ispfpga/bin/lin64/scuba -w -n pll_in240_out40 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 240 -phase_cntl STATIC -fclkop 40 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw + +-- Fri Jun 10 12:38:40 2016 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity pll_in240_out40 is + port ( + CLK: in std_logic; + CLKOP: out std_logic; + LOCK: out std_logic); +end pll_in240_out40; + +architecture Structure of pll_in240_out40 is + + -- internal signal declarations + signal CLKOP_t: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component EHXPLLF + generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; + DELAY_PWD : in String; DELAY_VAL : in Integer; + CLKOS_TRIM_DELAY : in Integer; + CLKOS_TRIM_POL : in String; + CLKOP_TRIM_DELAY : in Integer; + CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; + CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; + PHASE_DELAY_CNTL : in String; DUTY : in Integer; + PHASEADJ : in String; CLKOK_DIV : in Integer; + CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; + CLKI_DIV : in Integer; FIN : in String); + port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; + RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic; + DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; + DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; + DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic; + FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic; + CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic; + LOCK: out std_logic; CLKINTFB: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "40.000000"; + attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "240.000000"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLInst_0: EHXPLLF + generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED", + CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", + CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0, + CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING", + CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING", + PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", + CLKOK_DIV=> 2, CLKOP_DIV=> 16, CLKFB_DIV=> 1, CLKI_DIV=> 6, + FIN=> "240.000000") + port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo, + RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, + DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, + DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, + DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo, + FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t, + CLKOS=>open, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK, + CLKINTFB=>open); + + CLKOP <= CLKOP_t; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of pll_in240_out40 is + for Structure + for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on