From: Jan Michel <j.michel@gsi.de>
Date: Thu, 27 Jul 2017 12:39:58 +0000 (+0200)
Subject: Move threshold FPGA design files to new vhdlbasics repository
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=a1943b067894c8a3b0b4293908165b4f27fa75f4;p=dirich.git

Move threshold FPGA design files to new vhdlbasics repository
---

diff --git a/thresholds/compile.pl b/thresholds/compile.pl
index 3dfb1e0..8a19aa6 120000
--- a/thresholds/compile.pl
+++ b/thresholds/compile.pl
@@ -1 +1 @@
-/home/adrian/git/trb3sc/scripts/compile.pl
\ No newline at end of file
+../../trb3sc/scripts/compile.pl
\ No newline at end of file
diff --git a/thresholds/thresholds.prj b/thresholds/thresholds.prj
index 55e559c..7b41ec9 100644
--- a/thresholds/thresholds.prj
+++ b/thresholds/thresholds.prj
@@ -4,23 +4,16 @@
 
 #project files
 
-#add_file -vhdl -lib work "/d/jspc29/lattice/diamond/3.6_x64/cae_library/synthesis/vhdl/machxo3lf.vhd"
-
-#add_file -vhdl -lib work "../../trbnet/lattice/machxo3/fifo_9x2k_oreg.vhd"
-#add file -vhdl -lib work "./test/machxo3lf.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
 add_file -vhdl -lib work "../../vhdlbasics/interface/spi_slave.vhd"
 add_file -vhdl -lib work "../../vhdlbasics/machxo3/sedcheck.vhd"
 add_file -vhdl -lib work "../../vhdlbasics/io/pwm.vhd"
 add_file -vhdl -lib work "../../logicbox/UFM_control/UFM_control.vhd"
-add_file -vhdl -lib work "../../logicbox/cores/flashram.vhd"
-add_file -vhdl -lib work "../../logicbox/cores/flash.vhd"
-
 
-#add_file -vhdl -lib work "../../logicbox/cores/flashram.vhd"
-#add_file -vhdl -lib work "cores/efb.vhd"
-add_file -verilog -lib work "../../logicbox/cores/efb_define_def.v"
-add_file -verilog -lib work "../../logicbox/cores/UFM_WB.v"
+add_file -vhdl    -lib work "../../vhdlbasics/machxo3/flash/flashram.vhd"
+add_file -vhdl    -lib work "../../vhdlbasics/machxo3/flash/flash.vhd"
+add_file -verilog -lib work "../../vhdlbasics/machxo3/flash/efb_define_def.v"
+add_file -verilog -lib work "../../vhdlbasics/machxo3/flash/UFM_WB.v"
 
 add_file -vhdl -lib work "thresholds.vhd"
 
@@ -43,7 +36,7 @@ set_option -technology MACHXO3LF
 #set_option -part LCMXO3LF_6900C
 #set_option -package BG256C
 set_option -part LCMXO3LF_4300E
-set_option -package UWG81
+set_option -package UWG81CTR
 set_option -speed_grade -5
 set_option -part_companion ""
 
diff --git a/thresholds/thresholds.vhd b/thresholds/thresholds.vhd
index 1f4d8e0..ac2b97d 100644
--- a/thresholds/thresholds.vhd
+++ b/thresholds/thresholds.vhd
@@ -343,7 +343,8 @@ THE_SED : entity work.sedcheck
 ---------------------------------------------------------------------------        
 THE_PWM_GEN : entity work.pwm_generator
   generic map(
-    CHANNELS => 16
+    CHANNELS => 16,
+    DOWNSAMPLE => 16
     )
   port map(
     CLK        => clk_i,