syntmp/pll_in200_out100_srr.htm log file

From: Cahit Date: Fri, 20 Mar 2015 15:35:39 +0000 (+0100) Subject: pll IP moved to dirich X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=a1ccbb96af5c0771829373ea7b7320538a549141;p=trbnet.git pll IP moved to dirich --- diff --git a/lattice/ecp5/PLL/PLL.sbx b/lattice/ecp5/PLL/PLL.sbx deleted file mode 100644 index 5cdb2e4..0000000 --- a/lattice/ecp5/PLL/PLL.sbx +++ /dev/null @@ -1,661 +0,0 @@ - - - - LATTICE - LOCAL - PLL - 1.0 - - - Diamond_Synthesis - synthesis - - - Diamond_Simulation - simulation - - - - - - - - pll_in200_out100_CLKI - pll_in200_out100_CLKI - - in - - - - pll_in200_out100.CLKI - - - - - pll_in200_out100_CLKOP - pll_in200_out100_CLKOP - - out - - - - pll_in200_out100.CLKOP - - - - - pll_in200_out100_CLKOS - pll_in200_out100_CLKOS - - out - - - - pll_in200_out100.CLKOS - - - - - pll_in200_out100_LOCK - pll_in200_out100_LOCK - - out - - - - pll_in200_out100.LOCK - - - - - - - LFE5UM-85F-8MG285C - synplify - 2015-03-17.15:29:30 - 2015-03-17.15:44:52 - 3.4.0.80 - VHDL - - true - false - false - true - false - false - false - false - false - false - false - - - - - - - - LATTICE - LOCAL - PLL - 1.0 - - - pll_in200_out100 - - Lattice Semiconductor Corporation - LEGACY - PLL - 5.7 - - - Diamond_Simulation - simulation - - ./pll_in200_out100/pll_in200_out100.vhd - vhdlSource - - - - Diamond_Synthesis - synthesis - - ./pll_in200_out100/pll_in200_out100.vhd - vhdlSource - - - - - - Configuration - none - ${sbp_path}/${instance}/generate_core.tcl - CONFIG - - - CreateNGD - none - ${sbp_path}/${instance}/generate_ngd.tcl - CONFIG - - - Generation - none - ${sbp_path}/${instance}/generate_core.tcl - GENERATE - - - - - - - CLKI - CLKI - - in - - - - true - - - - - CLKOP - CLKOP - - out - - - - CLKOS - CLKOS - - out - - - - LOCK - LOCK - - out - - - - - - synplify - 2015-03-17.15:44:52 - - false - false - false - false - false - false - false - false - false - false - LPM - PRIMARY - PRIMARY - false - false - IO:2;PLL:1;DLL:0 - - - - CLKI - IO - - Inst1_IB - true - true - false - IO - true - - - - CLKI~ - IO - - true - false - IO - true - - - - pll_in200_out100 - GXPLL - - true - false - GXPLL - - - - - - - Family - ecp5um - - - OperatingCondition - COM - - - Package - CSFBGA285 - - - PartName - LFE5UM-85F-8MG285C - - - PartType - LFE5UM-85F - - - SpeedGrade - 8 - - - Status - C - - - - CoreName - PLL - - - CoreRevision - 5.7 - - - CoreStatus - Demo - - - CoreType - LPM - - - Date - 03/17/2015 - - - ModuleName - pll_in200_out100 - - - ParameterFileVersion - 1.0 - - - SourceFormat - VHDL - - - Time - 15:42:59 - - - VendorName - Lattice Semiconductor Corporation - - - - CLKFB_DIV - 1 - - - CLKI_DIV - 2 - - - CLKI_FREQ - 200 - - - CLKOP_ACTUAL_FREQ - 100.000000 - - - CLKOP_APHASE - 0.00 - - - CLKOP_DIV - 6 - - - CLKOP_DPHASE - 0 - - - CLKOP_FREQ - 100.00 - - - CLKOP_MUXA - DISABLED - - - CLKOP_TOL - 0.0 - - - CLKOP_TRIM_DELAY - 0 - - - CLKOP_TRIM_POL - Rising - - - CLKOS2_ACTUAL_FREQ - - - - CLKOS2_APHASE - 0.00 - - - CLKOS2_DIV - 1 - - - CLKOS2_DPHASE - 0 - - - CLKOS2_Enable - DISABLED - - - CLKOS2_FREQ - 100.00 - - - CLKOS2_MUXC - DISABLED - - - CLKOS2_TOL - 0.0 - - - CLKOS2_TRIM_DELAY - 0 - - - CLKOS2_TRIM_POL - Rising - - - CLKOS3_ACTUAL_FREQ - - - - CLKOS3_APHASE - 0.00 - - - CLKOS3_DIV - 1 - - - CLKOS3_DPHASE - 0 - - - CLKOS3_Enable - DISABLED - - - CLKOS3_FREQ - 100.00 - - - CLKOS3_MUXD - DISABLED - - - CLKOS3_TOL - 0.0 - - - CLKOS3_TRIM_DELAY - 0 - - - CLKOS3_TRIM_POL - Rising - - - CLKOS_ACTUAL_FREQ - 200.000000 - - - CLKOS_APHASE - 0.00 - - - CLKOS_DIV - 1 - - - CLKOS_DPHASE - 0 - - - CLKOS_Enable - ENABLED - - - CLKOS_FREQ - 100.00 - - - CLKOS_MUXB - ENABLED - - - CLKOS_TOL - 0.0 - - - CLKOS_TRIM_DELAY - 0 - - - CLKOS_TRIM_POL - Rising - - - CLKSEL_ENA - DISABLED - - - DPHASE_SOURCE - STATIC - - - Destination - Synplicity - - - EDIF - 1 - - - ENABLE_CLKOP - DISABLED - - - ENABLE_CLKOS - DISABLED - - - ENABLE_CLKOS2 - DISABLED - - - ENABLE_CLKOS3 - DISABLED - - - ENABLE_HBW - DISABLED - - - Expression - None - - - FEEDBK_PATH - CLKOP - - - FRACN_DIV - - - - FRACN_ENABLE - DISABLED - - - IO - 0 - - - IOBUF - LVDS - - - Order - None - - - PLLRST_ENA - DISABLED - - - PLL_BW - 8.185 - - - PLL_LOCK_MODE - ENABLED - - - PLL_LOCK_STK - DISABLED - - - PLL_USE_SMI - DISABLED - - - REFERENCE - 1 - - - STDBY_ENABLE - DISABLED - - - VCO_RATE - 600.000 - - - VHDL - 1 - - - Verilog - 0 - - - - cmd_line - -w -n pll_in200_out100 -lang vhdl -synth synplify -arch sa5p00m -type pll -fin 200 -clkibuf LVDS -fclkop 100.00 -fclkop_tol 0.0 -bypass_divs -phase_cntl STATIC -lock -fb_mode 1 - - - - - GXPLL - 1 - - true - true - GXPLL - - pll_in200_out100 - - - IO - 1 - - true - true - IO - - CLKI - CLKI~ - - - pll - 0 - - true - false - PLL - - CLKI - CLKI~ - pll_in200_out100 - - - - - - - - - pll_in200_out100_CLKI - pll_in200_out100_CLKI - - - sys_yes - - - - - - - pll_in200_out100_CLKOP - pll_in200_out100_CLKOP - - - - - pll_in200_out100_CLKOS - pll_in200_out100_CLKOS - - - - - pll_in200_out100_LOCK - pll_in200_out100_LOCK - - - - - - diff --git a/lattice/ecp5/PLL/archv/pll_in200_out100.zip b/lattice/ecp5/PLL/archv/pll_in200_out100.zip deleted file mode 100644 index c8b86e5..0000000 Binary files a/lattice/ecp5/PLL/archv/pll_in200_out100.zip and /dev/null differ diff --git a/lattice/ecp5/PLL/pll_in200_out100/licbug.txt b/lattice/ecp5/PLL/pll_in200_out100/licbug.txt deleted file mode 100644 index ecb7ba4..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/licbug.txt +++ /dev/null @@ -1,16 +0,0 @@ -main called -main 10 -main 20 -main 30 -main 40 -main 50 -main 60 -main 70 -main 80 -main 90 -main 100 -main 110 -MainAppInit 10 -MainAppInit 20 -MainAppInit 30 -MainAppInit 40 diff --git a/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100.cmd b/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100.cmd deleted file mode 100644 index 2974efe..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100.cmd +++ /dev/null @@ -1,18 +0,0 @@ -PROJECT: pll_in200_out100 - working_path: "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results" - module: pll_in200_out100 - verilog_file_list: "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd" - vlog_std_v2001: true - constraint_file_name: "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc" - suffix_name: edn - output_file_name: pll_in200_out100 - write_prf: true - disable_io_insertion: true - force_gsr: false - frequency: 100 - fanout_limit: 50 - retiming: false - pipe: false - part: LFE5UM-85F - speed_grade: 8 - diff --git a/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100.edn b/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100.edn deleted file mode 100644 index 56b4d1c..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100.edn +++ /dev/null @@ -1,234 +0,0 @@ -(edif pll_in200_out100 - (edifVersion 2 0 0) - (edifLevel 0) - (keywordMap (keywordLevel 0)) - (status - (written - (timestamp 2015 3 17 15 43 11) - (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80")))) - (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n pll_in200_out100 -lang vhdl -synth synplify -arch sa5p00m -type pll -fin 200 -clkibuf LVDS -fclkop 100.00 -fclkop_tol 0.0 -bypass_divs -phase_cntl STATIC -lock -fb_mode 1 -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc ") - (library ORCLIB - (edifLevel 0) - (technology - (numberDefinition)) - (cell EHXPLLL - (cellType GENERIC) - (view view1 - (viewType NETLIST) - (interface - (port CLKI - (direction INPUT)) - (port CLKFB - (direction INPUT)) - (port PHASESEL1 - (direction INPUT)) - (port PHASESEL0 - (direction INPUT)) - (port PHASEDIR - (direction INPUT)) - (port PHASESTEP - (direction INPUT)) - (port PHASELOADREG - (direction INPUT)) - (port STDBY - (direction INPUT)) - (port PLLWAKESYNC - (direction INPUT)) - (port RST - (direction INPUT)) - (port ENCLKOP - (direction INPUT)) - (port ENCLKOS - (direction INPUT)) - (port ENCLKOS2 - (direction INPUT)) - (port ENCLKOS3 - (direction INPUT)) - (port CLKOP - (direction OUTPUT)) - (port CLKOS - (direction OUTPUT)) - (port CLKOS2 - (direction OUTPUT)) - (port CLKOS3 - (direction OUTPUT)) - (port LOCK - (direction OUTPUT)) - (port INTLOCK - (direction OUTPUT)) - (port REFCLK - (direction OUTPUT)) - (port CLKINTFB - (direction OUTPUT))))) - (cell VHI - (cellType GENERIC) - (view view1 - (viewType NETLIST) - (interface - (port Z - (direction OUTPUT))))) - (cell VLO - (cellType GENERIC) - (view view1 - (viewType NETLIST) - (interface - (port Z - (direction OUTPUT))))) - (cell IB - (cellType GENERIC) - (view view1 - (viewType NETLIST) - (interface - (port I - (direction INPUT)) - (port O - (direction OUTPUT))))) - (cell pll_in200_out100 - (cellType GENERIC) - (view view1 - (viewType NETLIST) - (interface - (port CLKI - (direction INPUT)) - (port CLKOP - (direction OUTPUT)) - (port CLKOS - (direction OUTPUT)) - (port LOCK - (direction OUTPUT))) - (property NGD_DRC_MASK (integer 1)) - (contents - (instance Inst1_IB - (viewRef view1 - (cellRef IB)) - (property IO_TYPE - (string "LVDS"))) - (instance scuba_vhi_inst - (viewRef view1 - (cellRef VHI))) - (instance scuba_vlo_inst - (viewRef view1 - (cellRef VLO))) - (instance PLLInst_0 - (viewRef view1 - (cellRef EHXPLLL)) - (property PLLRST_ENA - (string "DISABLED")) - (property INTFB_WAKE - (string "DISABLED")) - (property STDBY_ENABLE - (string "DISABLED")) - (property DPHASE_SOURCE - (string "DISABLED")) - (property CLKOS3_FPHASE - (string "0")) - (property CLKOS3_CPHASE - (string "0")) - (property CLKOS2_FPHASE - (string "0")) - (property CLKOS2_CPHASE - (string "0")) - (property CLKOS_FPHASE - (string "0")) - (property CLKOS_CPHASE - (string "0")) - (property CLKOP_FPHASE - (string "0")) - (property CLKOP_CPHASE - (string "5")) - (property PLL_LOCK_MODE - (string "0")) - (property CLKOS_TRIM_DELAY - (string "0")) - (property CLKOS_TRIM_POL - (string "FALLING")) - (property CLKOP_TRIM_DELAY - (string "0")) - (property CLKOP_TRIM_POL - (string "FALLING")) - (property OUTDIVIDER_MUXD - (string "DIVD")) - (property CLKOS3_ENABLE - (string "DISABLED")) - (property OUTDIVIDER_MUXC - (string "DIVC")) - (property CLKOS2_ENABLE - (string "DISABLED")) - (property FREQUENCY_PIN_CLKOS - (string "200.000000")) - (property OUTDIVIDER_MUXB - (string "DIVB")) - (property CLKOS_ENABLE - (string "ENABLED")) - (property FREQUENCY_PIN_CLKOP - (string "100.000000")) - (property OUTDIVIDER_MUXA - (string "DIVA")) - (property CLKOP_ENABLE - (string "ENABLED")) - (property FREQUENCY_PIN_CLKI - (string "200.000000")) - (property ICP_CURRENT - (string "9")) - (property LPF_RESISTOR - (string "72")) - (property CLKOS3_DIV - (string "1")) - (property CLKOS2_DIV - (string "1")) - (property CLKOS_DIV - (string "1")) - (property CLKOP_DIV - (string "6")) - (property CLKFB_DIV - (string "1")) - (property CLKI_DIV - (string "2")) - (property FEEDBK_PATH - (string "CLKOP"))) - (net REFCLK - (joined - (portRef REFCLK (instanceRef PLLInst_0)))) - (net buf_CLKI - (joined - (portRef O (instanceRef Inst1_IB)) - (portRef CLKI (instanceRef PLLInst_0)))) - (net scuba_vhi - (joined - (portRef Z (instanceRef scuba_vhi_inst)))) - (net scuba_vlo - (joined - (portRef Z (instanceRef scuba_vlo_inst)) - (portRef ENCLKOS3 (instanceRef PLLInst_0)) - (portRef ENCLKOS2 (instanceRef PLLInst_0)) - (portRef ENCLKOS (instanceRef PLLInst_0)) - (portRef ENCLKOP (instanceRef PLLInst_0)) - (portRef RST (instanceRef PLLInst_0)) - (portRef PLLWAKESYNC (instanceRef PLLInst_0)) - (portRef STDBY (instanceRef PLLInst_0)) - (portRef PHASELOADREG (instanceRef PLLInst_0)) - (portRef PHASESTEP (instanceRef PLLInst_0)) - (portRef PHASEDIR (instanceRef PLLInst_0)) - (portRef PHASESEL1 (instanceRef PLLInst_0)) - (portRef PHASESEL0 (instanceRef PLLInst_0)))) - (net LOCK - (joined - (portRef LOCK) - (portRef LOCK (instanceRef PLLInst_0)))) - (net CLKOS - (joined - (portRef CLKOS) - (portRef CLKOS (instanceRef PLLInst_0)))) - (net CLKOP - (joined - (portRef CLKOP) - (portRef CLKFB (instanceRef PLLInst_0)) - (portRef CLKOP (instanceRef PLLInst_0)))) - (net CLKI - (joined - (portRef CLKI) - (portRef I (instanceRef Inst1_IB)))))))) - (design pll_in200_out100 - (cellRef pll_in200_out100 - (libraryRef ORCLIB))) -) diff --git a/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc b/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc deleted file mode 100644 index 6fbcac9..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc +++ /dev/null @@ -1,2 +0,0 @@ -###==== Start Configuration - diff --git a/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100.lpc b/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100.lpc deleted file mode 100644 index cb1b7d9..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100.lpc +++ /dev/null @@ -1,93 +0,0 @@ -[Device] -Family=ecp5um -PartType=LFE5UM-85F -PartName=LFE5UM-85F-8MG285C -SpeedGrade=8 -Package=CSFBGA285 -OperatingCondition=COM -Status=C - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=PLL -CoreRevision=5.7 -ModuleName=pll_in200_out100 -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=03/17/2015 -Time=15:42:59 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=None -Order=None -IO=0 -CLKI_FREQ=200 -CLKI_DIV=2 -ENABLE_HBW=DISABLED -REFERENCE=1 -IOBUF=LVDS -CLKOP_FREQ=100.00 -CLKOP_TOL=0.0 -CLKOP_DIV=6 -CLKOP_ACTUAL_FREQ=100.000000 -CLKOP_MUXA=DISABLED -CLKOS_Enable=ENABLED -CLKOS_FREQ=100.00 -CLKOS_TOL=0.0 -CLKOS_DIV=1 -CLKOS_ACTUAL_FREQ=200.000000 -CLKOS_MUXB=ENABLED -CLKOS2_Enable=DISABLED -CLKOS2_FREQ=100.00 -CLKOS2_TOL=0.0 -CLKOS2_DIV=1 -CLKOS2_ACTUAL_FREQ= -CLKOS2_MUXC=DISABLED -CLKOS3_Enable=DISABLED -CLKOS3_FREQ=100.00 -CLKOS3_TOL=0.0 -CLKOS3_DIV=1 -CLKOS3_ACTUAL_FREQ= -CLKOS3_MUXD=DISABLED -FEEDBK_PATH=CLKOP -CLKFB_DIV=1 -FRACN_ENABLE=DISABLED -FRACN_DIV= -VCO_RATE=600.000 -PLL_BW=8.185 -CLKOP_DPHASE=0 -CLKOP_APHASE=0.00 -CLKOP_TRIM_POL=Rising -CLKOP_TRIM_DELAY=0 -CLKOS_DPHASE=0 -CLKOS_APHASE=0.00 -CLKOS_TRIM_POL=Rising -CLKOS_TRIM_DELAY=0 -CLKOS2_DPHASE=0 -CLKOS2_APHASE=0.00 -CLKOS2_TRIM_POL=Rising -CLKOS2_TRIM_DELAY=0 -CLKOS3_DPHASE=0 -CLKOS3_APHASE=0.00 -CLKOS3_TRIM_POL=Rising -CLKOS3_TRIM_DELAY=0 -CLKSEL_ENA=DISABLED -DPHASE_SOURCE=STATIC -ENABLE_CLKOP=DISABLED -ENABLE_CLKOS=DISABLED -ENABLE_CLKOS2=DISABLED -ENABLE_CLKOS3=DISABLED -STDBY_ENABLE=DISABLED -PLLRST_ENA=DISABLED -PLL_LOCK_MODE=ENABLED -PLL_LOCK_STK=DISABLED -PLL_USE_SMI=DISABLED - -[Command] -cmd_line= -w -n pll_in200_out100 -lang vhdl -synth synplify -arch sa5p00m -type pll -fin 200 -clkibuf LVDS -fclkop 100.00 -fclkop_tol 0.0 -bypass_divs -phase_cntl STATIC -lock -fb_mode 1 diff --git a/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100.ngd b/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100.ngd deleted file mode 100644 index a8dd8bc..0000000 Binary files a/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100.ngd and /dev/null differ diff --git a/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100.ngo b/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100.ngo deleted file mode 100644 index 417aa39..0000000 Binary files a/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100.ngo and /dev/null differ diff --git a/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd b/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd deleted file mode 100644 index 0d6e70d..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd +++ /dev/null @@ -1,86 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80 --- Module Version: 5.7 ---/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n pll_in200_out100 -lang vhdl -synth synplify -arch sa5p00m -type pll -fin 200 -clkibuf LVDS -fclkop 100.00 -fclkop_tol 0.0 -bypass_divs -phase_cntl STATIC -lock -fb_mode 1 -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc - --- Tue Mar 17 15:43:11 2015 - -library IEEE; -use IEEE.std_logic_1164.all; -library ecp5um; -use ecp5um.components.all; - -entity pll_in200_out100 is - port ( - CLKI: in std_logic; - CLKOP: out std_logic; - CLKOS: out std_logic; - LOCK: out std_logic); - attribute dont_touch : boolean; - attribute dont_touch of pll_in200_out100 : entity is true; -end pll_in200_out100; - -architecture Structure of pll_in200_out100 is - - -- internal signal declarations - signal REFCLK: std_logic; - signal CLKOS_t: std_logic; - signal CLKOP_t: std_logic; - signal buf_CLKI: std_logic; - signal scuba_vhi: std_logic; - signal scuba_vlo: std_logic; - - attribute IO_TYPE : string; - attribute FREQUENCY_PIN_CLKOS : string; - attribute FREQUENCY_PIN_CLKOP : string; - attribute FREQUENCY_PIN_CLKI : string; - attribute ICP_CURRENT : string; - attribute LPF_RESISTOR : string; - attribute IO_TYPE of Inst1_IB : label is "LVDS"; - attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "200.000000"; - attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "100.000000"; - attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000"; - attribute ICP_CURRENT of PLLInst_0 : label is "9"; - attribute LPF_RESISTOR of PLLInst_0 : label is "72"; - attribute syn_keep : boolean; - attribute syn_noprune : boolean; - attribute syn_noprune of Structure : architecture is true; - attribute NGD_DRC_MASK : integer; - attribute NGD_DRC_MASK of Structure : architecture is 1; - -begin - -- component instantiation statements - Inst1_IB: IB - port map (I=>CLKI, O=>buf_CLKI); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - PLLInst_0: EHXPLLL - generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED", - STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED", - CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 0, CLKOS2_FPHASE=> 0, - CLKOS2_CPHASE=> 0, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 0, - CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 5, PLL_LOCK_MODE=> 0, - CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING", - CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING", - OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED", - OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "DISABLED", - OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "ENABLED", - OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 1, - CLKOS2_DIV=> 1, CLKOS_DIV=> 1, CLKOP_DIV=> 6, CLKFB_DIV=> 1, - CLKI_DIV=> 2, FEEDBK_PATH=> "CLKOP") - port map (CLKI=>buf_CLKI, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo, - PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo, - PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo, - STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, - ENCLKOP=>scuba_vlo, ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo, - ENCLKOS3=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t, - CLKOS2=>open, CLKOS3=>open, LOCK=>LOCK, INTLOCK=>open, - REFCLK=>REFCLK, CLKINTFB=>open); - - CLKOS <= CLKOS_t; - CLKOP <= CLKOP_t; -end Structure; diff --git a/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100_ngd.asd b/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100_ngd.asd deleted file mode 100644 index c265c78..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100_ngd.asd +++ /dev/null @@ -1 +0,0 @@ -[ActiveSupport NGD] diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/.recordref b/lattice/ecp5/PLL/pll_in200_out100/syn_results/.recordref deleted file mode 100644 index e69de29..0000000 diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/dm/layer0.xdm b/lattice/ecp5/PLL/pll_in200_out100/syn_results/dm/layer0.xdm deleted file mode 100644 index 68f68d0..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/syn_results/dm/layer0.xdm +++ /dev/null @@ -1,177 +0,0 @@ -%%% protect protected_file -@EG -- -]17p0Osk0CksRsPC#MHF=3"4j -"> -!S<-1-RFOksCHRVDRC#O0FMskHL0oHMRR0F0REC8HC#o-MR-S> -S -S -SF<1kCsOR"b=/0Fb/M#$F$b##-/K.cj43-jg1/u.D/HLP/E8##Mb_bEN# _boE3P8N"R=""4R"D=PDE8"DROH=#0""-4RHbD#"0=-/4">S -S -SF<1kCsOR"b=/0Fb/M#$F$b##-/K.cj43-jg1/u.D/HLP/E8MCkls3HOP"E8R"N=dD"R=E"P8RD"O#DH0-="4b"RD0H#=4"-" -/>S1S -SF<1kCsOR"b=/0Fb/M#$F$b##-/K.cj43-jg1/u.D/HLP/E8N0sHEE3P8N"R=""6R"D=PDE8"DROH=#0""-4RHbD#"0=-/4">S -SS1S -SF<1kCsOR"b=/lEFCk/Oo/ksu[sFC#O0/Ba7__FMad)A/L0sdN/L#OC/F#sC/bCO6p/upD/bDM_H._jjF4k0jbj/DHD_Mj.j_0Fk43jjP"E8R"N=UD"R=E"P8RD"O#DH0-="4b"RD0H#=4"-" -/>S1S - -S-< -S)0FFR"M=I Fs3DbD_.HMjFj_kj04j03#s0kOk"sC/ -> - -< -S!R--vkF8D7CRCMVHHF0HM-R->< -S7RCVMC="Okb6lA3Q3M#$_NLDOL _FRG"DP="E"8D>S -SS -S"/ -S -S"/ -S -S -SR -SR -SRS -S"/ -SqS -/S<7>CV -< -S!R--vkF8D7CRCMVHHF0HM-R->< -S7RCVMC="Okb6lp3em$3#MD_LN_O L"FGR"D=PDE8"S> -SR -SRS -SSqS -SRSqS"/ -"/ -"/ -SqS - -/S<7>CV -< -S!R--vkF8D7CRCMVHHF0HM-R->< -S7RCVMC="Okb6l]3 Xpupp$3#MD_LN_O L"FGR"D=PDE8"S> -SRR/ -SqSS -S"/ -S -SS -SS -SS -S"/ -SuSS -S"/ -"/ -"/ -S -SSuS -SR -SR -SR -SR -SR"/ -S -SSuS"/ -S -S"/ -SuSS -SSuS -SRS -SSuSS -SSuSS -S -SR -SR -SR -SRS -S"/ -SuSS -S -SR -SR -SRS -S"/ -/S<7>CV -< -S!R--vkF8D7CRCMVHHF0HM-R->< -S7RCVMI="F3s b_DDHjM.jk_F0j4j3s#0kkO0sRC"DP="E"8D>S -S -SRS -S -SR -SR"/ - -SRSqSS -SS -S -SR"/ - -SC<)V=RM"bCO63klQ#A3$LM_D NO_GLF"=RH"#QM0Q4_A -">SS -SSR -S)S)SSS -S -SC<)V=RM"bCO63kl u]Xp3pp#_$MLODN F_LGH"R=p"up#QM0"_j>S -SSRSS -SSRSS -SSRSS -SqS -SqS -SqS -SqSS"/ -SSSS -SSR -SqSS -SSR"/ -SSSS -SqS -SqS -SqSS -SSR"/ -SSS"/ -SSS"/ -SSS -SqSS -SSR"/ -SSSS -SqSS"/ -SSSS -SSR -SqS -SqS"/ -SSSSSS/S<)>CV -/S<7>CV -]sC - -@ diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/licbug.txt b/lattice/ecp5/PLL/pll_in200_out100/syn_results/licbug.txt deleted file mode 100644 index 085ef99..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/syn_results/licbug.txt +++ /dev/null @@ -1 +0,0 @@ -MainAppInit 50 diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.areasrr b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.areasrr deleted file mode 100644 index b4a79ee..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.areasrr +++ /dev/null @@ -1,16 +0,0 @@ ----------------------------------------------------------------------- -Report for cell pll_in200_out100.structure - -Register bits: 0 of 24288 (0%) -PIC Latch: 0 -I/O cells: 1 - Cell usage: - cell count Res Usage(%) - EHXPLLL 1 100.0 - GSR 1 100.0 - IB 1 100.0 - PUR 1 100.0 - VHI 1 100.0 - VLO 1 100.0 - - TOTAL 6 diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.edn b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.edn deleted file mode 100644 index e7f7754..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.edn +++ /dev/null @@ -1,236 +0,0 @@ -(edif pll_in200_out100 - (edifVersion 2 0 0) - (edifLevel 0) - (keywordMap (keywordLevel 0)) - (status - (written - (timeStamp 2015 3 17 15 43 13) - (author "Synopsys, Inc.") - (program "Synplify Pro" (version "J-2014.09-SP2, mapper maprc, Build 2453R")) - ) - ) - (library ecp5um - (edifLevel 0) - (technology (numberDefinition )) - (cell EHXPLLL (cellType GENERIC) - (view syn_black_box (viewType NETLIST) - (interface - (port CLKI (direction INPUT)) - (port CLKFB (direction INPUT)) - (port PHASESEL1 (direction INPUT)) - (port PHASESEL0 (direction INPUT)) - (port PHASEDIR (direction INPUT)) - (port PHASESTEP (direction INPUT)) - (port PHASELOADREG (direction INPUT)) - (port STDBY (direction INPUT)) - (port PLLWAKESYNC (direction INPUT)) - (port RST (direction INPUT)) - (port ENCLKOP (direction INPUT)) - (port ENCLKOS (direction INPUT)) - (port ENCLKOS2 (direction INPUT)) - (port ENCLKOS3 (direction INPUT)) - (port CLKOP (direction OUTPUT)) - (port CLKOS (direction OUTPUT)) - (port CLKOS2 (direction OUTPUT)) - (port CLKOS3 (direction OUTPUT)) - (port LOCK (direction OUTPUT)) - (port INTLOCK (direction OUTPUT)) - (port REFCLK (direction OUTPUT)) - (port CLKINTFB (direction OUTPUT)) - ) - (property CLKI_DIV (integer 1)) - (property CLKFB_DIV (integer 1)) - (property CLKOP_DIV (integer 8)) - (property CLKOS_DIV (integer 8)) - (property CLKOS2_DIV (integer 8)) - (property CLKOS3_DIV (integer 8)) - (property CLKOP_ENABLE (string "ENABLED")) - (property CLKOS_ENABLE (string "DISABLED")) - (property CLKOS2_ENABLE (string "DISABLED")) - (property CLKOS3_ENABLE (string "DISABLED")) - (property CLKOP_CPHASE (integer 0)) - (property CLKOS_CPHASE (integer 0)) - (property CLKOS2_CPHASE (integer 0)) - (property CLKOS3_CPHASE (integer 0)) - (property CLKOP_FPHASE (integer 0)) - (property CLKOS_FPHASE (integer 0)) - (property CLKOS2_FPHASE (integer 0)) - (property CLKOS3_FPHASE (integer 0)) - (property FEEDBK_PATH (string "CLKOP")) - (property CLKOP_TRIM_POL (string "RISING")) - (property CLKOP_TRIM_DELAY (integer 0)) - (property CLKOS_TRIM_POL (string "RISING")) - (property CLKOS_TRIM_DELAY (integer 0)) - (property OUTDIVIDER_MUXA (string "DIVA")) - (property OUTDIVIDER_MUXB (string "DIVB")) - (property OUTDIVIDER_MUXC (string "DIVC")) - (property OUTDIVIDER_MUXD (string "DIVD")) - (property PLL_LOCK_MODE (integer 0)) - (property PLL_LOCK_DELAY (integer 200)) - (property STDBY_ENABLE (string "DISABLED")) - (property REFIN_RESET (string "DISABLED")) - (property SYNC_ENABLE (string "DISABLED")) - (property INT_LOCK_STICKY (string "ENABLED")) - (property DPHASE_SOURCE (string "DISABLED")) - (property PLLRST_ENA (string "DISABLED")) - (property INTFB_WAKE (string "DISABLED")) - (property orig_inst_of (string "EHXPLLL")) - ) - ) - ) - (library LUCENT - (edifLevel 0) - (technology (numberDefinition )) - (cell IB (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port I (direction INPUT)) - (port O (direction OUTPUT)) - ) - ) - ) - (cell GSR (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port GSR (direction INPUT)) - ) - ) - ) - (cell VHI (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port Z (direction OUTPUT)) - ) - ) - ) - (cell VLO (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port Z (direction OUTPUT)) - ) - ) - ) - ) - (library work - (edifLevel 0) - (technology (numberDefinition )) - (cell pll_in200_out100 (cellType GENERIC) - (view structure (viewType NETLIST) - (interface - (port CLKI (direction INPUT)) - (port CLKOP (direction OUTPUT)) - (port CLKOS (direction OUTPUT)) - (port LOCK (direction OUTPUT)) - ) - (contents - (instance GND_0 (viewRef PRIM (cellRef VLO (libraryRef LUCENT))) ) - (instance VCC_0 (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) ) - (instance GSR_INST (viewRef PRIM (cellRef GSR (libraryRef LUCENT))) - ) - (instance Inst1_IB (viewRef PRIM (cellRef IB (libraryRef LUCENT))) - (property IO_TYPE (string "LVDS")) - ) - (instance PLLInst_0 (viewRef syn_black_box (cellRef EHXPLLL (libraryRef ecp5um))) - (property INTFB_WAKE (string "DISABLED")) - (property PLLRST_ENA (string "DISABLED")) - (property DPHASE_SOURCE (string "DISABLED")) - (property STDBY_ENABLE (string "DISABLED")) - (property PLL_LOCK_MODE (integer 0)) - (property OUTDIVIDER_MUXD (string "DIVD")) - (property OUTDIVIDER_MUXC (string "DIVC")) - (property OUTDIVIDER_MUXB (string "DIVB")) - (property OUTDIVIDER_MUXA (string "DIVA")) - (property CLKOS_TRIM_DELAY (integer 0)) - (property CLKOS_TRIM_POL (string "FALLING")) - (property CLKOP_TRIM_DELAY (integer 0)) - (property CLKOP_TRIM_POL (string "FALLING")) - (property FEEDBK_PATH (string "CLKOP")) - (property CLKOS3_FPHASE (integer 0)) - (property CLKOS2_FPHASE (integer 0)) - (property CLKOS_FPHASE (integer 0)) - (property CLKOP_FPHASE (integer 0)) - (property CLKOS3_CPHASE (integer 0)) - (property CLKOS2_CPHASE (integer 0)) - (property CLKOS_CPHASE (integer 0)) - (property CLKOP_CPHASE (integer 5)) - (property CLKOS3_ENABLE (string "DISABLED")) - (property CLKOS2_ENABLE (string "DISABLED")) - (property CLKOS_ENABLE (string "ENABLED")) - (property CLKOP_ENABLE (string "ENABLED")) - (property CLKOS3_DIV (integer 1)) - (property CLKOS2_DIV (integer 1)) - (property CLKOS_DIV (integer 1)) - (property CLKOP_DIV (integer 6)) - (property CLKFB_DIV (integer 1)) - (property CLKI_DIV (integer 2)) - (property LPF_RESISTOR (string "72")) - (property ICP_CURRENT (string "9")) - (property FREQUENCY_PIN_CLKI (string "200.000000")) - (property FREQUENCY_PIN_CLKOP (string "100.000000")) - (property FREQUENCY_PIN_CLKOS (string "200.000000")) - ) - (net CLKI (joined - (portRef CLKI) - (portRef I (instanceRef Inst1_IB)) - )) - (net CLKOP (joined - (portRef CLKOP (instanceRef PLLInst_0)) - (portRef CLKFB (instanceRef PLLInst_0)) - (portRef CLKOP) - )) - (net CLKOS (joined - (portRef CLKOS (instanceRef PLLInst_0)) - (portRef CLKOS) - )) - (net LOCK (joined - (portRef LOCK (instanceRef PLLInst_0)) - (portRef LOCK) - )) - (net CLKOS2 (joined - (portRef CLKOS2 (instanceRef PLLInst_0)) - )) - (net CLKOS3 (joined - (portRef CLKOS3 (instanceRef PLLInst_0)) - )) - (net INTLOCK (joined - (portRef INTLOCK (instanceRef PLLInst_0)) - )) - (net CLKINTFB (joined - (portRef CLKINTFB (instanceRef PLLInst_0)) - )) - (net buf_CLKI (joined - (portRef O (instanceRef Inst1_IB)) - (portRef CLKI (instanceRef PLLInst_0)) - )) - (net REFCLK (joined - (portRef REFCLK (instanceRef PLLInst_0)) - )) - (net GND (joined - (portRef Z (instanceRef GND_0)) - (portRef ENCLKOS3 (instanceRef PLLInst_0)) - (portRef ENCLKOS2 (instanceRef PLLInst_0)) - (portRef ENCLKOS (instanceRef PLLInst_0)) - (portRef ENCLKOP (instanceRef PLLInst_0)) - (portRef RST (instanceRef PLLInst_0)) - (portRef PLLWAKESYNC (instanceRef PLLInst_0)) - (portRef STDBY (instanceRef PLLInst_0)) - (portRef PHASELOADREG (instanceRef PLLInst_0)) - (portRef PHASESTEP (instanceRef PLLInst_0)) - (portRef PHASEDIR (instanceRef PLLInst_0)) - (portRef PHASESEL0 (instanceRef PLLInst_0)) - (portRef PHASESEL1 (instanceRef PLLInst_0)) - )) - (net VCC (joined - (portRef Z (instanceRef VCC_0)) - (portRef GSR (instanceRef GSR_INST)) - )) - ) - (property NGD_DRC_MASK (integer 1)) - (property dont_touch (integer 1)) - (property orig_inst_of (string "pll_in200_out100")) - ) - ) - ) - (design pll_in200_out100 (cellRef pll_in200_out100 (libraryRef work)) - (property PART (string "lfe5um_25f-6") )) -) diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.fse b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.fse deleted file mode 100644 index e69de29..0000000 diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.htm b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.htm deleted file mode 100644 index db9de8a..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.htm +++ /dev/null @@ -1,9 +0,0 @@ - - - syntmp/pll_in200_out100_srr.htm log file - - - - - - diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.prj b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.prj deleted file mode 100644 index 1131742..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.prj +++ /dev/null @@ -1,46 +0,0 @@ -#-- Lattice Semiconductor Corporation Ltd. -#-- Synplify OEM project file /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.prj -#-- Written on Tue Mar 17 15:43:11 2015 - - -#device options -set_option -technology ecp5um -set_option -part LFE5UM-85F -set_option -speed_grade 8 - -#use verilog 2001 standard option -set_option -vlog_std v2001 - -#map options -set_option -frequency 100 -set_option -fanout_limit 50 -set_option -disable_io_insertion true -set_option -retiming false -set_option -pipe false -set_option -pipe false -set_option -force_gsr false - -#simulation options -set_option -write_verilog true -set_option -write_vhdl true - -#timing analysis options - -#automatic place and route (vendor) options -set_option -write_apr_constraint 1 - -#-- add_file options -add_file -vhdl -lib work "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd" -add_file -constraint {"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc"} - -#-- top module name -set_option -top_module pll_in200_out100 - -#-- set result format/file last -project -result_file "pll_in200_out100.edn" - -#-- error message log file -project -log_file pll_in200_out100.srf - -#-- run Synplify with 'arrange VHDL file' -project -run diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srd b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srd deleted file mode 100644 index 979e704..0000000 Binary files a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srd and /dev/null differ diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srf b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srf deleted file mode 100644 index 15854e8..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srf +++ /dev/null @@ -1,373 +0,0 @@ -#Build: Synplify Pro J-2014.09-SP2, Build 1283R, Nov 20 2014 -#install: /opt/synopsys/J-2014.09-SP2 -#OS: Linux -#Hostname: depc363 - -#Implementation: syn_results - -Synopsys HDL Compiler, version comp201409sp2rc, Build 069R, built Nov 20 2014 -@N|Running in 64-bit mode -Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. - -Running on host :depc363 -Synopsys VHDL Compiler, version comp201409sp2rc, Build 069R, built Nov 20 2014 -@N|Running in 64-bit mode -Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. - -@N: CD720 :"/opt/synopsys/J-2014.09-SP2/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ns -@N:"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":12:7:12:22|Top entity is set to pll_in200_out100. -VHDL syntax check successful! -@N: CD630 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":12:7:12:22|Synthesizing work.pll_in200_out100.structure -@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":2081:10:2081:16|Synthesizing ecp5um.ehxplll.syn_black_box -Post processing for ecp5um.ehxplll.syn_black_box -@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":830:10:830:12|Synthesizing ecp5um.vlo.syn_black_box -Post processing for ecp5um.vlo.syn_black_box -@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":823:10:823:12|Synthesizing ecp5um.vhi.syn_black_box -Post processing for ecp5um.vhi.syn_black_box -@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":998:10:998:11|Synthesizing ecp5um.ib.syn_black_box -Post processing for ecp5um.ib.syn_black_box -Post processing for work.pll_in200_out100.structure -@W: CL168 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":55:4:55:17|Pruning instance scuba_vhi_inst -- not in use ... - -At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Tue Mar 17 15:43:11 2015 - -###########################################################] -Synopsys Netlist Linker, version comp201409sp2rc, Build 069R, built Nov 20 2014 -@N|Running in 64-bit mode - -At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Tue Mar 17 15:43:11 2015 - -###########################################################] -@END - -At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Tue Mar 17 15:43:11 2015 - -###########################################################] -Synopsys Netlist Linker, version comp201409sp2rc, Build 069R, built Nov 20 2014 -@N|Running in 64-bit mode - -At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Tue Mar 17 15:43:12 2015 - -###########################################################] -Pre-mapping Report - -Synopsys Lattice Technology Pre-mapping, Version maprc, Build 2453R, Built Nov 20 2014 09:28:55 -Copyright (C) 1994-2014, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. -Product Version J-2014.09-SP2 - -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) - -Reading constraint file: /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc -@L: /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100_scck.rpt -Printing clock summary report in "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100_scck.rpt" file -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled - -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) - - -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) - - -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB) - - -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB) - -ICG Latch Removal Summary: -Number of ICG latches removed: 0 -Number of ICG latches not removed: 0 -syn_allowed_resources : blockrams=56 set on top level netlist pll_in200_out100 - -Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) - - - -@S |Clock Summary -**************** - -Start Requested Requested Clock Clock -Clock Frequency Period Type Group ------------------------------------------------------------------ -System 100.0 MHz 10.000 system system_clkgroup -================================================================= - -Pre-mapping successful! - -At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 140MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Tue Mar 17 15:43:13 2015 - -###########################################################] -Map & Optimize Report - -Synopsys Lattice Technology Mapper, Version maprc, Build 2453R, Built Nov 20 2014 09:28:55 -Copyright (C) 1994-2014, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. -Product Version J-2014.09-SP2 - -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) - -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled - -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) - - -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) - - -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 110MB peak: 111MB) - - -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB) - - - -Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) - - -Available hyper_sources - for debug and ip models - None Found - - -Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) - - -Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) - - -Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) - - -Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) - - -Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) - - -Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) - - -Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) - - -Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) - - -Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) - -Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------- -Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------- ------------------------------------------------------------- - - -Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) - -@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. - -Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) - - - -#### START OF CLOCK OPTIMIZATION REPORT #####[ - -0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s) -0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) -0 instances converted, 0 sequential instances remain driven by gated/generated clocks - - - -##### END OF CLOCK OPTIMIZATION REPORT ######] - -Writing Analyst data base /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srm - -Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) - -Writing Analyst data base /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_m.srm - -Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) - -Writing EDIF Netlist and constraint files -J-2014.09-SP2 -@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF - -Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB) - -Writing Verilog Simulation files - -Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB) - -Writing VHDL Simulation files - -Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - - -Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB) - -@W: MT246 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":61:4:61:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) - - -@S |##### START OF TIMING REPORT #####[ -# Timing Report written on Tue Mar 17 15:43:14 2015 -# - - -Top view: pll_in200_out100 -Requested Frequency: 100.0 MHz -Wire load mode: top -Paths requested: 5 -Constraint File(s): /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc - -@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing. - -@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock. - - - -Performance Summary -******************* - - -Worst slack in design: 10.000 - -@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching. - Requested Estimated Requested Estimated Clock Clock -Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------- -System 100.0 MHz NA 10.000 0.000 10.000 system system_clkgroup -================================================================================================================ -@N: MT582 |Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack - - - - - -Clock Relationships -******************* - -Clocks | rise to rise | fall to fall | rise to fall | fall to rise ---------------------------------------------------------------------------------------------------------- -Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ---------------------------------------------------------------------------------------------------------- -System System | 10.000 10.000 | No paths - | No paths - | No paths - -========================================================================================================= - Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. - 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. - - - -Interface Information -********************* - -No IO constraint found - - - -==================================== -Detailed Report for Clock: System -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------- -PLLInst_0 System EHXPLLL CLKOP CLKOP 0.000 10.000 -============================================================================== - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock -------------------------------------------------------------------------------- -PLLInst_0 System EHXPLLL CLKFB CLKOP 10.000 10.000 -=============================================================================== - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 10.000 - - Setup time: 0.000 - + Clock delay at ending point: 0.000 (ideal) - + Estimated clock delay at ending point: 0.000 - = Required time: 10.000 - - - Propagation time: 0.000 - - Clock delay at starting point: 0.000 (ideal) - - Estimated clock delay at start point: -0.000 - = Slack (critical) : 10.000 - - Number of logic level(s): 0 - Starting point: PLLInst_0 / CLKOP - Ending point: PLLInst_0 / CLKFB - The start point is clocked by System [rising] - The end point is clocked by System [rising] - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------- -PLLInst_0 EHXPLLL CLKOP Out 0.000 0.000 - -CLKOP Net - - - - 2 -PLLInst_0 EHXPLLL CLKFB In 0.000 0.000 - -================================================================================= - - - -##### END OF TIMING REPORT #####] - - -Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB) - - -Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB) - ---------------------------------------- -Resource Usage Report -Part: lfe5um_25f-6 - -Register bits: 0 of 24288 (0%) -PIC Latch: 0 -I/O cells: 1 - - -Details: -EHXPLLL: 1 -GSR: 1 -IB: 1 -PUR: 1 -VHI: 1 -VLO: 1 -Mapper successful! - -At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 143MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Tue Mar 17 15:43:14 2015 - -###########################################################] diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srm b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srm deleted file mode 100644 index 98174c4..0000000 Binary files a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srm and /dev/null differ diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srr b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srr deleted file mode 100644 index 15854e8..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srr +++ /dev/null @@ -1,373 +0,0 @@ -#Build: Synplify Pro J-2014.09-SP2, Build 1283R, Nov 20 2014 -#install: /opt/synopsys/J-2014.09-SP2 -#OS: Linux -#Hostname: depc363 - -#Implementation: syn_results - -Synopsys HDL Compiler, version comp201409sp2rc, Build 069R, built Nov 20 2014 -@N|Running in 64-bit mode -Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. - -Running on host :depc363 -Synopsys VHDL Compiler, version comp201409sp2rc, Build 069R, built Nov 20 2014 -@N|Running in 64-bit mode -Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. - -@N: CD720 :"/opt/synopsys/J-2014.09-SP2/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ns -@N:"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":12:7:12:22|Top entity is set to pll_in200_out100. -VHDL syntax check successful! -@N: CD630 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":12:7:12:22|Synthesizing work.pll_in200_out100.structure -@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":2081:10:2081:16|Synthesizing ecp5um.ehxplll.syn_black_box -Post processing for ecp5um.ehxplll.syn_black_box -@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":830:10:830:12|Synthesizing ecp5um.vlo.syn_black_box -Post processing for ecp5um.vlo.syn_black_box -@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":823:10:823:12|Synthesizing ecp5um.vhi.syn_black_box -Post processing for ecp5um.vhi.syn_black_box -@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":998:10:998:11|Synthesizing ecp5um.ib.syn_black_box -Post processing for ecp5um.ib.syn_black_box -Post processing for work.pll_in200_out100.structure -@W: CL168 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":55:4:55:17|Pruning instance scuba_vhi_inst -- not in use ... - -At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Tue Mar 17 15:43:11 2015 - -###########################################################] -Synopsys Netlist Linker, version comp201409sp2rc, Build 069R, built Nov 20 2014 -@N|Running in 64-bit mode - -At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Tue Mar 17 15:43:11 2015 - -###########################################################] -@END - -At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Tue Mar 17 15:43:11 2015 - -###########################################################] -Synopsys Netlist Linker, version comp201409sp2rc, Build 069R, built Nov 20 2014 -@N|Running in 64-bit mode - -At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Tue Mar 17 15:43:12 2015 - -###########################################################] -Pre-mapping Report - -Synopsys Lattice Technology Pre-mapping, Version maprc, Build 2453R, Built Nov 20 2014 09:28:55 -Copyright (C) 1994-2014, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. -Product Version J-2014.09-SP2 - -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) - -Reading constraint file: /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc -@L: /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100_scck.rpt -Printing clock summary report in "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100_scck.rpt" file -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled - -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) - - -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) - - -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB) - - -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB) - -ICG Latch Removal Summary: -Number of ICG latches removed: 0 -Number of ICG latches not removed: 0 -syn_allowed_resources : blockrams=56 set on top level netlist pll_in200_out100 - -Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) - - - -@S |Clock Summary -**************** - -Start Requested Requested Clock Clock -Clock Frequency Period Type Group ------------------------------------------------------------------ -System 100.0 MHz 10.000 system system_clkgroup -================================================================= - -Pre-mapping successful! - -At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 140MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Tue Mar 17 15:43:13 2015 - -###########################################################] -Map & Optimize Report - -Synopsys Lattice Technology Mapper, Version maprc, Build 2453R, Built Nov 20 2014 09:28:55 -Copyright (C) 1994-2014, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. -Product Version J-2014.09-SP2 - -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) - -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled - -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) - - -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) - - -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 110MB peak: 111MB) - - -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB) - - - -Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) - - -Available hyper_sources - for debug and ip models - None Found - - -Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) - - -Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) - - -Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) - - -Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) - - -Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) - - -Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) - - -Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) - - -Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) - - -Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) - -Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------- -Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------- ------------------------------------------------------------- - - -Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) - -@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. - -Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) - - - -#### START OF CLOCK OPTIMIZATION REPORT #####[ - -0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s) -0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) -0 instances converted, 0 sequential instances remain driven by gated/generated clocks - - - -##### END OF CLOCK OPTIMIZATION REPORT ######] - -Writing Analyst data base /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srm - -Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) - -Writing Analyst data base /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_m.srm - -Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) - -Writing EDIF Netlist and constraint files -J-2014.09-SP2 -@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF - -Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB) - -Writing Verilog Simulation files - -Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB) - -Writing VHDL Simulation files - -Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - - -Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB) - -@W: MT246 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":61:4:61:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) - - -@S |##### START OF TIMING REPORT #####[ -# Timing Report written on Tue Mar 17 15:43:14 2015 -# - - -Top view: pll_in200_out100 -Requested Frequency: 100.0 MHz -Wire load mode: top -Paths requested: 5 -Constraint File(s): /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc - -@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing. - -@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock. - - - -Performance Summary -******************* - - -Worst slack in design: 10.000 - -@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching. - Requested Estimated Requested Estimated Clock Clock -Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------- -System 100.0 MHz NA 10.000 0.000 10.000 system system_clkgroup -================================================================================================================ -@N: MT582 |Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack - - - - - -Clock Relationships -******************* - -Clocks | rise to rise | fall to fall | rise to fall | fall to rise ---------------------------------------------------------------------------------------------------------- -Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ---------------------------------------------------------------------------------------------------------- -System System | 10.000 10.000 | No paths - | No paths - | No paths - -========================================================================================================= - Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. - 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. - - - -Interface Information -********************* - -No IO constraint found - - - -==================================== -Detailed Report for Clock: System -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------- -PLLInst_0 System EHXPLLL CLKOP CLKOP 0.000 10.000 -============================================================================== - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock -------------------------------------------------------------------------------- -PLLInst_0 System EHXPLLL CLKFB CLKOP 10.000 10.000 -=============================================================================== - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 10.000 - - Setup time: 0.000 - + Clock delay at ending point: 0.000 (ideal) - + Estimated clock delay at ending point: 0.000 - = Required time: 10.000 - - - Propagation time: 0.000 - - Clock delay at starting point: 0.000 (ideal) - - Estimated clock delay at start point: -0.000 - = Slack (critical) : 10.000 - - Number of logic level(s): 0 - Starting point: PLLInst_0 / CLKOP - Ending point: PLLInst_0 / CLKFB - The start point is clocked by System [rising] - The end point is clocked by System [rising] - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------- -PLLInst_0 EHXPLLL CLKOP Out 0.000 0.000 - -CLKOP Net - - - - 2 -PLLInst_0 EHXPLLL CLKFB In 0.000 0.000 - -================================================================================= - - - -##### END OF TIMING REPORT #####] - - -Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB) - - -Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB) - ---------------------------------------- -Resource Usage Report -Part: lfe5um_25f-6 - -Register bits: 0 of 24288 (0%) -PIC Latch: 0 -I/O cells: 1 - - -Details: -EHXPLLL: 1 -GSR: 1 -IB: 1 -PUR: 1 -VHI: 1 -VLO: 1 -Mapper successful! - -At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 143MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Tue Mar 17 15:43:14 2015 - -###########################################################] diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srs b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srs deleted file mode 100644 index 57d784a..0000000 Binary files a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srs and /dev/null differ diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.vhm b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.vhm deleted file mode 100644 index 89d3c09..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.vhm +++ /dev/null @@ -1,139 +0,0 @@ --- --- Written by Synplicity --- Product Version "J-2014.09-SP2" --- Program "Synplify Pro", Mapper "maprc, Build 2453R" --- Tue Mar 17 15:43:14 2015 --- - --- --- Written by Synplify Pro version Build 2453R --- Tue Mar 17 15:43:14 2015 --- - --- -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -library synplify; -use synplify.components.all; -library pmi; -use pmi.pmi_components.all; -library ecp5um; -use ecp5um.components.all; - -entity pll_in200_out100 is -port( - CLKI : in std_logic; - CLKOP : out std_logic; - CLKOS : out std_logic; - LOCK : out std_logic); -end pll_in200_out100; - -architecture beh of pll_in200_out100 is - signal CLKOP_0 : std_logic ; - signal CLKOS2 : std_logic ; - signal CLKOS3 : std_logic ; - signal INTLOCK : std_logic ; - signal CLKINTFB : std_logic ; - signal BUF_CLKI : std_logic ; - signal REFCLK : std_logic ; - signal GND : std_logic ; - signal VCC : std_logic ; - component EHXPLLL - port( - CLKI : in std_logic; - CLKFB : in std_logic; - PHASESEL1 : in std_logic; - PHASESEL0 : in std_logic; - PHASEDIR : in std_logic; - PHASESTEP : in std_logic; - PHASELOADREG : in std_logic; - STDBY : in std_logic; - PLLWAKESYNC : in std_logic; - RST : in std_logic; - ENCLKOP : in std_logic; - ENCLKOS : in std_logic; - ENCLKOS2 : in std_logic; - ENCLKOS3 : in std_logic; - CLKOP : out std_logic; - CLKOS : out std_logic; - CLKOS2 : out std_logic; - CLKOS3 : out std_logic; - LOCK : out std_logic; - INTLOCK : out std_logic; - REFCLK : out std_logic; - CLKINTFB : out std_logic ); - end component; -begin -GND_0: VLO port map ( - Z => GND); -VCC_0: VHI port map ( - Z => VCC); -PUR_INST: PUR port map ( - PUR => VCC); -GSR_INST: GSR port map ( - GSR => VCC); -INST1_IB: IB port map ( - I => CLKI, - O => BUF_CLKI); -PLLINST_0: EHXPLLL - generic map( - CLKI_DIV => 2, - CLKFB_DIV => 1, - CLKOP_DIV => 6, - CLKOS_DIV => 1, - CLKOS2_DIV => 1, - CLKOS3_DIV => 1, - CLKOP_ENABLE => "ENABLED", - CLKOS_ENABLE => "ENABLED", - CLKOS2_ENABLE => "DISABLED", - CLKOS3_ENABLE => "DISABLED", - CLKOP_CPHASE => 5, - CLKOS_CPHASE => 0, - CLKOS2_CPHASE => 0, - CLKOS3_CPHASE => 0, - CLKOP_FPHASE => 0, - CLKOS_FPHASE => 0, - CLKOS2_FPHASE => 0, - CLKOS3_FPHASE => 0, - FEEDBK_PATH => "CLKOP", - CLKOP_TRIM_POL => "FALLING", - CLKOP_TRIM_DELAY => 0, - CLKOS_TRIM_POL => "FALLING", - CLKOS_TRIM_DELAY => 0, - OUTDIVIDER_MUXA => "DIVA", - OUTDIVIDER_MUXB => "DIVB", - OUTDIVIDER_MUXC => "DIVC", - OUTDIVIDER_MUXD => "DIVD", - PLL_LOCK_MODE => 0, - STDBY_ENABLE => "DISABLED", - DPHASE_SOURCE => "DISABLED", - PLLRST_ENA => "DISABLED", - INTFB_WAKE => "DISABLED" - ) - port map ( - CLKI => BUF_CLKI, - CLKFB => CLKOP_0, - PHASESEL1 => GND, - PHASESEL0 => GND, - PHASEDIR => GND, - PHASESTEP => GND, - PHASELOADREG => GND, - STDBY => GND, - PLLWAKESYNC => GND, - RST => GND, - ENCLKOP => GND, - ENCLKOS => GND, - ENCLKOS2 => GND, - ENCLKOS3 => GND, - CLKOP => CLKOP_0, - CLKOS => CLKOS, - CLKOS2 => CLKOS2, - CLKOS3 => CLKOS3, - LOCK => LOCK, - INTLOCK => INTLOCK, - REFCLK => REFCLK, - CLKINTFB => CLKINTFB); -CLKOP <= CLKOP_0; -end beh; - diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.vm b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.vm deleted file mode 100644 index 2c7d22b..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.vm +++ /dev/null @@ -1,120 +0,0 @@ -// -// Written by Synplify Pro -// Product Version "J-2014.09-SP2" -// Program "Synplify Pro", Mapper "maprc, Build 2453R" -// Tue Mar 17 15:43:14 2015 -// -// Source file index table: -// Object locations will have the form : -// file 0 "\/opt/synopsys/J-2014.09-SP2/lib/vhd/std.vhd " -// file 1 "\/opt/synopsys/J-2014.09-SP2/lib/vhd/snps_haps_pkg.vhd " -// file 2 "\/opt/synopsys/J-2014.09-SP2/lib/vhd/std1164.vhd " -// file 3 "\/opt/synopsys/J-2014.09-SP2/lib/vhd/numeric.vhd " -// file 4 "\/opt/synopsys/J-2014.09-SP2/lib/vhd/umr_capim.vhd " -// file 5 "\/opt/synopsys/J-2014.09-SP2/lib/vhd/arith.vhd " -// file 6 "\/opt/synopsys/J-2014.09-SP2/lib/vhd/unsigned.vhd " -// file 7 "\/opt/synopsys/J-2014.09-SP2/lib/vhd/hyperents.vhd " -// file 8 "\/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd " -// file 9 "\/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd " -// file 10 "\/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc " - -`timescale 100 ps/100 ps -module pll_in200_out100 ( - CLKI, - CLKOP, - CLKOS, - LOCK -) -; -input CLKI ; -output CLKOP ; -output CLKOS ; -output LOCK ; -wire CLKI ; -wire CLKOP ; -wire CLKOS ; -wire LOCK ; -wire CLKOS2 ; -wire CLKOS3 ; -wire INTLOCK ; -wire CLKINTFB ; -wire buf_CLKI ; -wire REFCLK ; -wire GND ; -wire VCC ; - VLO GND_0 ( - .Z(GND) -); - VHI VCC_0 ( - .Z(VCC) -); - PUR PUR_INST ( - .PUR(VCC) -); - GSR GSR_INST ( - .GSR(VCC) -); -// @8:52 - IB Inst1_IB ( - .I(CLKI), - .O(buf_CLKI) -); -// @8:61 - EHXPLLL PLLInst_0 ( - .CLKI(buf_CLKI), - .CLKFB(CLKOP), - .PHASESEL1(GND), - .PHASESEL0(GND), - .PHASEDIR(GND), - .PHASESTEP(GND), - .PHASELOADREG(GND), - .STDBY(GND), - .PLLWAKESYNC(GND), - .RST(GND), - .ENCLKOP(GND), - .ENCLKOS(GND), - .ENCLKOS2(GND), - .ENCLKOS3(GND), - .CLKOP(CLKOP), - .CLKOS(CLKOS), - .CLKOS2(CLKOS2), - .CLKOS3(CLKOS3), - .LOCK(LOCK), - .INTLOCK(INTLOCK), - .REFCLK(REFCLK), - .CLKINTFB(CLKINTFB) -); -defparam PLLInst_0.CLKI_DIV = 2; -defparam PLLInst_0.CLKFB_DIV = 1; -defparam PLLInst_0.CLKOP_DIV = 6; -defparam PLLInst_0.CLKOS_DIV = 1; -defparam PLLInst_0.CLKOS2_DIV = 1; -defparam PLLInst_0.CLKOS3_DIV = 1; -defparam PLLInst_0.CLKOP_ENABLE = "ENABLED"; -defparam PLLInst_0.CLKOS_ENABLE = "ENABLED"; -defparam PLLInst_0.CLKOS2_ENABLE = "DISABLED"; -defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED"; -defparam PLLInst_0.CLKOP_CPHASE = 5; -defparam PLLInst_0.CLKOS_CPHASE = 0; -defparam PLLInst_0.CLKOS2_CPHASE = 0; -defparam PLLInst_0.CLKOS3_CPHASE = 0; -defparam PLLInst_0.CLKOP_FPHASE = 0; -defparam PLLInst_0.CLKOS_FPHASE = 0; -defparam PLLInst_0.CLKOS2_FPHASE = 0; -defparam PLLInst_0.CLKOS3_FPHASE = 0; -defparam PLLInst_0.FEEDBK_PATH = "CLKOP"; -defparam PLLInst_0.CLKOP_TRIM_POL = "FALLING"; -defparam PLLInst_0.CLKOP_TRIM_DELAY = 0; -defparam PLLInst_0.CLKOS_TRIM_POL = "FALLING"; -defparam PLLInst_0.CLKOS_TRIM_DELAY = 0; -defparam PLLInst_0.OUTDIVIDER_MUXA = "DIVA"; -defparam PLLInst_0.OUTDIVIDER_MUXB = "DIVB"; -defparam PLLInst_0.OUTDIVIDER_MUXC = "DIVC"; -defparam PLLInst_0.OUTDIVIDER_MUXD = "DIVD"; -defparam PLLInst_0.PLL_LOCK_MODE = 0; -defparam PLLInst_0.STDBY_ENABLE = "DISABLED"; -defparam PLLInst_0.DPHASE_SOURCE = "DISABLED"; -defparam PLLInst_0.PLLRST_ENA = "DISABLED"; -defparam PLLInst_0.INTFB_WAKE = "DISABLED"; -endmodule /* pll_in200_out100 */ - diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100_synplify.lpf b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100_synplify.lpf deleted file mode 100644 index 15716ec..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100_synplify.lpf +++ /dev/null @@ -1,20 +0,0 @@ -# -# Logical Preferences generated for Lattice by Synplify maprc, Build 2453R. -# - -# Period Constraints - - -# Output Constraints - -# Input Constraints - -# Point-to-point Delay Constraints - - - -# Block Path Constraints - -BLOCK ASYNCPATHS; - -# End of generated Logical Preferences. diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/run_options.txt b/lattice/ecp5/PLL/pll_in200_out100/syn_results/run_options.txt deleted file mode 100644 index 97483f5..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/syn_results/run_options.txt +++ /dev/null @@ -1,67 +0,0 @@ -#-- Synopsys, Inc. -#-- Version J-2014.09-SP2 -#-- Project file /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/run_options.txt -#-- Written on Tue Mar 17 15:43:11 2015 - - -#project files -add_file -vhdl -lib work "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd" -add_file -fpga_constraint "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc" - - - -#implementation: "syn_results" -impl -add syn_results -type fpga - -# -#implementation attributes - -set_option -vlog_std v2001 - -#device options -set_option -technology ecp5um -set_option -part LFE5UM_25F -set_option -package MG285C -set_option -speed_grade -6 -set_option -part_companion "" - -#compilation/mapping options -set_option -top_module "pll_in200_out100" - -# mapper_options -set_option -frequency 100 -set_option -write_verilog 1 -set_option -write_vhdl 1 -set_option -srs_instrumentation 1 - -# Lattice XP -set_option -maxfan 50 -set_option -disable_io_insertion 1 -set_option -retiming 0 -set_option -pipe 0 -set_option -forcegsr false -set_option -fix_gated_and_generated_clocks 1 -set_option -RWCheckOnRam 1 -set_option -update_models_cp 0 -set_option -syn_edif_array_rename 1 -set_option -Write_declared_clocks_only 1 - -# sequential_optimization_options -set_option -symbolic_fsm_compiler 1 - -# Compiler Options -set_option -compiler_compatible 0 -set_option -resource_sharing 1 - -# Compiler Options -set_option -auto_infer_blackbox 0 - -#automatic place and route (vendor) options -set_option -write_apr_constraint 1 - -#set result format/file last -project -result_file "./pll_in200_out100.edn" - -#set log file -set_option log_file "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srf" -impl -active "syn_results" diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/scratchproject.prs b/lattice/ecp5/PLL/pll_in200_out100/syn_results/scratchproject.prs deleted file mode 100644 index 02b31aa..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/syn_results/scratchproject.prs +++ /dev/null @@ -1,65 +0,0 @@ -#-- Synopsys, Inc. -#-- Version J-2014.09-SP2 -#-- Project file /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/scratchproject.prs - -#project files -add_file -vhdl -lib work "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd" -add_file -fpga_constraint "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc" - - - -#implementation: "syn_results" -impl -add /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results -type fpga - -# -#implementation attributes - -set_option -vlog_std v2001 - -#device options -set_option -technology ecp5um -set_option -part LFE5UM_25F -set_option -package MG285C -set_option -speed_grade -6 -set_option -part_companion "" - -#compilation/mapping options -set_option -top_module "pll_in200_out100" - -# mapper_options -set_option -frequency 100 -set_option -write_verilog 1 -set_option -write_vhdl 1 -set_option -srs_instrumentation 1 - -# Lattice XP -set_option -maxfan 50 -set_option -disable_io_insertion 1 -set_option -retiming 0 -set_option -pipe 0 -set_option -forcegsr false -set_option -fix_gated_and_generated_clocks 1 -set_option -RWCheckOnRam 1 -set_option -update_models_cp 0 -set_option -syn_edif_array_rename 1 -set_option -Write_declared_clocks_only 1 - -# sequential_optimization_options -set_option -symbolic_fsm_compiler 1 - -# Compiler Options -set_option -compiler_compatible 0 -set_option -resource_sharing 1 - -# Compiler Options -set_option -auto_infer_blackbox 0 - -#automatic place and route (vendor) options -set_option -write_apr_constraint 1 - -#set result format/file last -project -result_file "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.edn" - -#set log file -set_option log_file "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srf" -impl -active "syn_results" diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/map.srr.rptmap b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/map.srr.rptmap deleted file mode 100644 index 14f4991..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/map.srr.rptmap +++ /dev/null @@ -1 +0,0 @@ -./synlog/pll_in200_out100_fpga_mapper.srr,map.srr,Map Log diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_compiler.srr b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_compiler.srr deleted file mode 100644 index 929e022..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_compiler.srr +++ /dev/null @@ -1,47 +0,0 @@ -Synopsys HDL Compiler, version comp201409sp2rc, Build 069R, built Nov 20 2014 -@N|Running in 64-bit mode -Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. - -Running on host :depc363 -Synopsys VHDL Compiler, version comp201409sp2rc, Build 069R, built Nov 20 2014 -@N|Running in 64-bit mode -Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. - -@N: CD720 :"/opt/synopsys/J-2014.09-SP2/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ns -@N:"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":12:7:12:22|Top entity is set to pll_in200_out100. -VHDL syntax check successful! -@N: CD630 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":12:7:12:22|Synthesizing work.pll_in200_out100.structure -@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":2081:10:2081:16|Synthesizing ecp5um.ehxplll.syn_black_box -Post processing for ecp5um.ehxplll.syn_black_box -@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":830:10:830:12|Synthesizing ecp5um.vlo.syn_black_box -Post processing for ecp5um.vlo.syn_black_box -@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":823:10:823:12|Synthesizing ecp5um.vhi.syn_black_box -Post processing for ecp5um.vhi.syn_black_box -@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":998:10:998:11|Synthesizing ecp5um.ib.syn_black_box -Post processing for ecp5um.ib.syn_black_box -Post processing for work.pll_in200_out100.structure -@W: CL168 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":55:4:55:17|Pruning instance scuba_vhi_inst -- not in use ... - -At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Tue Mar 17 15:43:11 2015 - -###########################################################] -Synopsys Netlist Linker, version comp201409sp2rc, Build 069R, built Nov 20 2014 -@N|Running in 64-bit mode - -At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Tue Mar 17 15:43:11 2015 - -###########################################################] -@END - -At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Tue Mar 17 15:43:11 2015 - -###########################################################] diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_compiler.srr.rptmap b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_compiler.srr.rptmap deleted file mode 100644 index 8315622..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_compiler.srr.rptmap +++ /dev/null @@ -1 +0,0 @@ -./synlog/pll_in200_out100_compiler.srr,pll_in200_out100_compiler.srr,Compile Log diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_fpga_mapper.srr b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_fpga_mapper.srr deleted file mode 100644 index 600fb8e..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_fpga_mapper.srr +++ /dev/null @@ -1,257 +0,0 @@ -Synopsys Lattice Technology Mapper, Version maprc, Build 2453R, Built Nov 20 2014 09:28:55 -Copyright (C) 1994-2014, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. -Product Version J-2014.09-SP2 - -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) - -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled - -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) - - -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) - - -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 110MB peak: 111MB) - - -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB) - - - -Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) - - -Available hyper_sources - for debug and ip models - None Found - - -Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) - - -Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) - - -Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) - - -Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) - - -Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) - - -Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) - - -Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) - - -Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) - - -Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) - -Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------- -Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------- ------------------------------------------------------------- - - -Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) - -@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. - -Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) - - - -#### START OF CLOCK OPTIMIZATION REPORT #####[ - -0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s) -0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) -0 instances converted, 0 sequential instances remain driven by gated/generated clocks - - - -##### END OF CLOCK OPTIMIZATION REPORT ######] - -Writing Analyst data base /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srm - -Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) - -Writing Analyst data base /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_m.srm - -Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) - -Writing EDIF Netlist and constraint files -J-2014.09-SP2 -@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF - -Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB) - -Writing Verilog Simulation files - -Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB) - -Writing VHDL Simulation files - -Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - - -Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB) - -@W: MT246 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":61:4:61:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) - - -@S |##### START OF TIMING REPORT #####[ -# Timing Report written on Tue Mar 17 15:43:14 2015 -# - - -Top view: pll_in200_out100 -Requested Frequency: 100.0 MHz -Wire load mode: top -Paths requested: 5 -Constraint File(s): /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc - -@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing. - -@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock. - - - -Performance Summary -******************* - - -Worst slack in design: 10.000 - -@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching. - Requested Estimated Requested Estimated Clock Clock -Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------- -System 100.0 MHz NA 10.000 0.000 10.000 system system_clkgroup -================================================================================================================ -@N: MT582 |Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack - - - - - -Clock Relationships -******************* - -Clocks | rise to rise | fall to fall | rise to fall | fall to rise ---------------------------------------------------------------------------------------------------------- -Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ---------------------------------------------------------------------------------------------------------- -System System | 10.000 10.000 | No paths - | No paths - | No paths - -========================================================================================================= - Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. - 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. - - - -Interface Information -********************* - -No IO constraint found - - - -==================================== -Detailed Report for Clock: System -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------- -PLLInst_0 System EHXPLLL CLKOP CLKOP 0.000 10.000 -============================================================================== - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock -------------------------------------------------------------------------------- -PLLInst_0 System EHXPLLL CLKFB CLKOP 10.000 10.000 -=============================================================================== - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 10.000 - - Setup time: 0.000 - + Clock delay at ending point: 0.000 (ideal) - + Estimated clock delay at ending point: 0.000 - = Required time: 10.000 - - - Propagation time: 0.000 - - Clock delay at starting point: 0.000 (ideal) - - Estimated clock delay at start point: -0.000 - = Slack (critical) : 10.000 - - Number of logic level(s): 0 - Starting point: PLLInst_0 / CLKOP - Ending point: PLLInst_0 / CLKFB - The start point is clocked by System [rising] - The end point is clocked by System [rising] - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------- -PLLInst_0 EHXPLLL CLKOP Out 0.000 0.000 - -CLKOP Net - - - - 2 -PLLInst_0 EHXPLLL CLKFB In 0.000 0.000 - -================================================================================= - - - -##### END OF TIMING REPORT #####] - - -Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB) - - -Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB) - ---------------------------------------- -Resource Usage Report -Part: lfe5um_25f-6 - -Register bits: 0 of 24288 (0%) -PIC Latch: 0 -I/O cells: 1 - - -Details: -EHXPLLL: 1 -GSR: 1 -IB: 1 -PUR: 1 -VHI: 1 -VLO: 1 -Mapper successful! - -At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 143MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Tue Mar 17 15:43:14 2015 - -###########################################################] diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_fpga_mapper.srr_Min b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_fpga_mapper.srr_Min deleted file mode 100644 index f1b7379..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_fpga_mapper.srr_Min +++ /dev/null @@ -1,116 +0,0 @@ - - -@S |##### START OF TIMING REPORT #####[ -# Timing Report written on Tue Mar 17 15:43:14 2015 -# - - -Top view: pll_in200_out100 -Requested Frequency: 100.0 MHz -Wire load mode: top -Paths requested: 5 -Constraint File(s): /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc - -@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing. - -@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock. - - - -Performance Summary -******************* - - -Worst slack in design: 0.000 - -@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching. - Requested Estimated Requested Estimated Clock Clock -Starting Clock Frequency Frequency Period Period Slack Type Group ---------------------------------------------------------------------------------------------------------------- -System 100.0 MHz 100.0 MHz 10.000 10.000 0.000 system system_clkgroup -=============================================================================================================== - - - -Clock Relationships -******************* - -Clocks | rise to rise | fall to fall | rise to fall | fall to rise --------------------------------------------------------------------------------------------------------- -Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack --------------------------------------------------------------------------------------------------------- -System System | 0.000 0.000 | No paths - | No paths - | No paths - -======================================================================================================== - Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. - 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. - - - -Interface Information -********************* - -No IO constraint found - - - -==================================== -Detailed Report for Clock: System -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------ -PLLInst_0 System EHXPLLL CLKOP CLKOP 0.000 0.000 -============================================================================= - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------- -PLLInst_0 System EHXPLLL CLKFB CLKOP 0.000 0.000 -============================================================================== - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Propagation time: 0.000 - + Clock delay at starting point: 0.000 (ideal) --0.000 - - Requested Period: 0.000 - - Hold time: 0.000 - - Clock delay at ending point: 0.000 (ideal) -0.000 - = Slack (critical) : 0.000 - - Number of logic level(s): 0 - Starting point: PLLInst_0 / CLKOP - Ending point: PLLInst_0 / CLKFB - The start point is clocked by System [rising] - The end point is clocked by System [rising] - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------- -PLLInst_0 EHXPLLL CLKOP Out 0.000 0.000 - -CLKOP Net - - - - 2 -PLLInst_0 EHXPLLL CLKFB In 0.000 0.000 - -================================================================================= - - - -##### END OF TIMING REPORT #####] - diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_fpga_mapper.szr b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_fpga_mapper.szr deleted file mode 100644 index d632b3c..0000000 Binary files a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_fpga_mapper.szr and /dev/null differ diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_multi_srs_gen.srr b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_multi_srs_gen.srr deleted file mode 100644 index cded582..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_multi_srs_gen.srr +++ /dev/null @@ -1,9 +0,0 @@ -Synopsys Netlist Linker, version comp201409sp2rc, Build 069R, built Nov 20 2014 -@N|Running in 64-bit mode - -At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Tue Mar 17 15:43:12 2015 - -###########################################################] diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_premap.srr b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_premap.srr deleted file mode 100644 index 391303f..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_premap.srr +++ /dev/null @@ -1,49 +0,0 @@ -Synopsys Lattice Technology Pre-mapping, Version maprc, Build 2453R, Built Nov 20 2014 09:28:55 -Copyright (C) 1994-2014, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. -Product Version J-2014.09-SP2 - -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) - -Reading constraint file: /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc -@L: /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100_scck.rpt -Printing clock summary report in "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100_scck.rpt" file -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled - -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) - - -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) - - -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB) - - -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB) - -ICG Latch Removal Summary: -Number of ICG latches removed: 0 -Number of ICG latches not removed: 0 -syn_allowed_resources : blockrams=56 set on top level netlist pll_in200_out100 - -Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) - - - -@S |Clock Summary -**************** - -Start Requested Requested Clock Clock -Clock Frequency Period Type Group ------------------------------------------------------------------ -System 100.0 MHz 10.000 system system_clkgroup -================================================================= - -Pre-mapping successful! - -At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 140MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Tue Mar 17 15:43:13 2015 - -###########################################################] diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_premap.szr b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_premap.szr deleted file mode 100644 index bbfc77c..0000000 Binary files a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_premap.szr and /dev/null differ diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pre_map.srr.rptmap b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pre_map.srr.rptmap deleted file mode 100644 index d87f979..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pre_map.srr.rptmap +++ /dev/null @@ -1 +0,0 @@ -./synlog/pll_in200_out100_premap.srr,pre_map.srr,Pre_Map Log diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_compiler_notes.txt b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_compiler_notes.txt deleted file mode 100644 index 73b8299..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_compiler_notes.txt +++ /dev/null @@ -1,11 +0,0 @@ -@N|Running in 64-bit mode -@N|Running in 64-bit mode -@N: CD720 :"/opt/synopsys/J-2014.09-SP2/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ns -@N:"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":12:7:12:22|Top entity is set to pll_in200_out100. -@N: CD630 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":12:7:12:22|Synthesizing work.pll_in200_out100.structure -@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":2081:10:2081:16|Synthesizing ecp5um.ehxplll.syn_black_box -@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":830:10:830:12|Synthesizing ecp5um.vlo.syn_black_box -@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":823:10:823:12|Synthesizing ecp5um.vhi.syn_black_box -@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":998:10:998:11|Synthesizing ecp5um.ib.syn_black_box -@N|Running in 64-bit mode - diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_compiler_runstatus.xml b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_compiler_runstatus.xml deleted file mode 100644 index 26e4c2a..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_compiler_runstatus.xml +++ /dev/null @@ -1,41 +0,0 @@ - - - - - - /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_compiler.srr - Synopsys HDL Compiler - - - Completed - - - - 10 - /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_compiler_notes.txt - - - 1 - /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_compiler_warnings.txt - - - 0 - /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_compiler_errors.txt - - - - - - - 00h:00m:00s - - - - - - - 1426603391 - - - \ No newline at end of file diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_compiler_warnings.txt b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_compiler_warnings.txt deleted file mode 100644 index 46bf347..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_compiler_warnings.txt +++ /dev/null @@ -1,2 +0,0 @@ -@W: CL168 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":55:4:55:17|Pruning instance scuba_vhi_inst -- not in use ... - diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_area_report.xml b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_area_report.xml deleted file mode 100644 index 4a0f6ea..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_area_report.xml +++ /dev/null @@ -1,26 +0,0 @@ - - - - -/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_resourceusage.rpt -Resource Usage - - -0 - - -1 - - -0 - - -0 - - -0 - - diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_errors.txt b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_errors.txt deleted file mode 100644 index e69de29..0000000 diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_notes.txt b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_notes.txt deleted file mode 100644 index 0ac2949..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_notes.txt +++ /dev/null @@ -1,11 +0,0 @@ -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled -@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. -@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF -@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing. -@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock. -@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching. -@N: MT582 |Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack -@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing. -@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock. -@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching. diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_opt_report.xml b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_opt_report.xml deleted file mode 100644 index bace87f..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_opt_report.xml +++ /dev/null @@ -1,14 +0,0 @@ - - - - -0 / 0 - -/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_combined_clk.rpt -START OF CLOCK OPTIMIZATION REPORT - - - diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_runstatus.xml b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_runstatus.xml deleted file mode 100644 index aa39edd..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_runstatus.xml +++ /dev/null @@ -1,46 +0,0 @@ - - - - -/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_fpga_mapper.srr -Synopsys Lattice Technology Mapper - - -Completed - - - -11 - -/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_notes.txt - - - -1 - -/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_warnings.txt - - - -0 - -/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_errors.txt - - - -0h:00m:01s - - -0h:00m:01s - - -143MB - - -1426603394 - - - diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_timing_report.xml b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_timing_report.xml deleted file mode 100644 index 5d08600..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_timing_report.xml +++ /dev/null @@ -1,23 +0,0 @@ - - - - -/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_fpga_mapper.srr -START OF TIMING REPORT - - -Clock Name -Req Freq -Est Freq -Slack - - -System -100.0 MHz -NA -10.000 - - diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_warnings.txt b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_warnings.txt deleted file mode 100644 index 97bd277..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_warnings.txt +++ /dev/null @@ -1 +0,0 @@ -@W: MT246 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":61:4:61:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_premap_errors.txt b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_premap_errors.txt deleted file mode 100644 index e69de29..0000000 diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_premap_notes.txt b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_premap_notes.txt deleted file mode 100644 index 4081b54..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_premap_notes.txt +++ /dev/null @@ -1,2 +0,0 @@ -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_premap_runstatus.xml b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_premap_runstatus.xml deleted file mode 100644 index 2f16611..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_premap_runstatus.xml +++ /dev/null @@ -1,46 +0,0 @@ - - - - -/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_premap.srr -Synopsys Lattice Technology Pre-mapping - - -Completed - - - -2 - -/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_premap_notes.txt - - - -0 - -/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_premap_warnings.txt - - - -0 - -/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_premap_errors.txt - - - -0h:00m:00s - - -0h:00m:00s - - -140MB - - -1426603393 - - - diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_premap_warnings.txt b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_premap_warnings.txt deleted file mode 100644 index e69de29..0000000 diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/closed.png b/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/closed.png deleted file mode 100644 index 0d78634..0000000 Binary files a/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/closed.png and /dev/null differ diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/namekey.txt b/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/namekey.txt deleted file mode 100644 index e69de29..0000000 diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/open.png b/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/open.png deleted file mode 100644 index a227005..0000000 Binary files a/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/open.png and /dev/null differ diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100.plg b/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100.plg deleted file mode 100644 index c01538b..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100.plg +++ /dev/null @@ -1,14 +0,0 @@ -@P: Worst Slack : 10.000 -@P: System - Estimated Frequency : NA -@P: System - Requested Frequency : 100.0 MHz -@P: System - Estimated Period : 0.000 -@P: System - Requested Period : 10.000 -@P: System - Slack : 10.000 -@P: Worst Slack(min analysis) : 0.000 -@P: System - Estimated Frequency(min analysis) : 100.0 MHz -@P: System - Requested Frequency(min analysis) : 100.0 MHz -@P: System - Estimated Period(min analysis) : 10.000 -@P: System - Requested Period(min analysis) : 10.000 -@P: System - Slack(min analysis) : 0.000 -@P: Total Area : 0.0 -@P: CPU Time : 0h:00m:01s diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100_srr.htm b/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100_srr.htm deleted file mode 100644 index 60bcd8c..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100_srr.htm +++ /dev/null @@ -1,378 +0,0 @@ -- -#Build: Synplify Pro J-2014.09-SP2, Build 1283R, Nov 20 2014 -#install: /opt/synopsys/J-2014.09-SP2 -#OS: Linux -#Hostname: depc363 - -#Implementation: syn_results - -Synopsys HDL Compiler, version comp201409sp2rc, Build 069R, built Nov 20 2014 -@N: : | Running in 64-bit mode -Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. - -Running on host :depc363 -Synopsys VHDL Compiler, version comp201409sp2rc, Build 069R, built Nov 20 2014 -@N: : | Running in 64-bit mode -Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. - -@N:CD720 : std.vhd(123) | Setting time resolution to ns -@N: : pll_in200_out100.vhd(12) | Top entity is set to pll_in200_out100. -VHDL syntax check successful! -@N:CD630 : pll_in200_out100.vhd(12) | Synthesizing work.pll_in200_out100.structure -@N:CD630 : ecp5um.vhd(2081) | Synthesizing ecp5um.ehxplll.syn_black_box -Post processing for ecp5um.ehxplll.syn_black_box -@N:CD630 : ecp5um.vhd(830) | Synthesizing ecp5um.vlo.syn_black_box -Post processing for ecp5um.vlo.syn_black_box -@N:CD630 : ecp5um.vhd(823) | Synthesizing ecp5um.vhi.syn_black_box -Post processing for ecp5um.vhi.syn_black_box -@N:CD630 : ecp5um.vhd(998) | Synthesizing ecp5um.ib.syn_black_box -Post processing for ecp5um.ib.syn_black_box -Post processing for work.pll_in200_out100.structure -@W:CL168 : pll_in200_out100.vhd(55) | Pruning instance scuba_vhi_inst -- not in use ... - -At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Tue Mar 17 15:43:11 2015 - -###########################################################] -Synopsys Netlist Linker, version comp201409sp2rc, Build 069R, built Nov 20 2014 -@N: : | Running in 64-bit mode - -At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Tue Mar 17 15:43:11 2015 - -###########################################################] -@END - -At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Tue Mar 17 15:43:11 2015 - -###########################################################] -Synopsys Netlist Linker, version comp201409sp2rc, Build 069R, built Nov 20 2014 -@N: : | Running in 64-bit mode - -At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Tue Mar 17 15:43:12 2015 - -###########################################################] -Pre-mapping Report - -Synopsys Lattice Technology Pre-mapping, Version maprc, Build 2453R, Built Nov 20 2014 09:28:55 -Copyright (C) 1994-2014, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. -Product Version J-2014.09-SP2 - -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) - -Reading constraint file: /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc -Linked File: pll_in200_out100_scck.rpt -Printing clock summary report in "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100_scck.rpt" file -@N:MF248 : | Running in 64-bit mode. -@N:MF666 : | Clock conversion enabled - -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) - - -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) - - -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB) - - -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB) - -ICG Latch Removal Summary: -Number of ICG latches removed: 0 -Number of ICG latches not removed: 0 -syn_allowed_resources : blockrams=56 set on top level netlist pll_in200_out100 - -Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) - - - -@S |Clock Summary -**************** - -Start Requested Requested Clock Clock -Clock Frequency Period Type Group ------------------------------------------------------------------ -System 100.0 MHz 10.000 system system_clkgroup -================================================================= - -Pre-mapping successful! - -At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 140MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Tue Mar 17 15:43:13 2015 - -###########################################################] -Map & Optimize Report - -Synopsys Lattice Technology Mapper, Version maprc, Build 2453R, Built Nov 20 2014 09:28:55 -Copyright (C) 1994-2014, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. -Product Version J-2014.09-SP2 - -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) - -@N:MF248 : | Running in 64-bit mode. -@N:MF666 : | Clock conversion enabled - -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) - - -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) - - -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 110MB peak: 111MB) - - -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB) - - - -Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) - - -Available hyper_sources - for debug and ip models - None Found - - -Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) - - -Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) - - -Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) - - -Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) - - -Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) - - -Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) - - -Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) - - -Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) - - -Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) - -Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------- -Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------- ------------------------------------------------------------- - - -Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) - -@N:FX164 : | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. - -Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) - - - -#### START OF CLOCK OPTIMIZATION REPORT #####[ - -0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s) -0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) -0 instances converted, 0 sequential instances remain driven by gated/generated clocks - - - -##### END OF CLOCK OPTIMIZATION REPORT ######] - -Writing Analyst data base /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srm - -Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) - -Writing Analyst data base /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_m.srm - -Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) - -Writing EDIF Netlist and constraint files -J-2014.09-SP2 -@N:BW106 : | Synplicity Constraint File capacitance units using default value of 1pF - -Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB) - -Writing Verilog Simulation files - -Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB) - -Writing VHDL Simulation files - -Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - - -Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB) - -@W:MT246 : pll_in200_out100.vhd(61) | Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) - - -@S |##### START OF TIMING REPORT #####[ -# Timing Report written on Tue Mar 17 15:43:14 2015 -# - - -Top view: pll_in200_out100 -Requested Frequency: 100.0 MHz -Wire load mode: top -Paths requested: 5 -Constraint File(s): /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc - -@N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing. - -@N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock. - - - -Performance Summary -******************* - - -Worst slack in design: 10.000 - -@N:MT286 : | System clock period 0.000 stretches to negative invalid value -- ignoring stretching. - Requested Estimated Requested Estimated Clock Clock -Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------- -System 100.0 MHz NA 10.000 0.000 10.000 system system_clkgroup -================================================================================================================ -@N:MT582 : | Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack - - - - - -Clock Relationships -******************* - -Clocks | rise to rise | fall to fall | rise to fall | fall to rise ---------------------------------------------------------------------------------------------------------- -Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ---------------------------------------------------------------------------------------------------------- -System System | 10.000 10.000 | No paths - | No paths - | No paths - -========================================================================================================= - Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. - 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. - - - -Interface Information -********************* - -No IO constraint found - - - -==================================== -Detailed Report for Clock: System -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------- -PLLInst_0 System EHXPLLL CLKOP CLKOP 0.000 10.000 -============================================================================== - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock -------------------------------------------------------------------------------- -PLLInst_0 System EHXPLLL CLKFB CLKOP 10.000 10.000 -=============================================================================== - - - -Worst Path Information -View Worst Path in Analyst -*********************** - - -Path information for path number 1: - Requested Period: 10.000 - - Setup time: 0.000 - + Clock delay at ending point: 0.000 (ideal) - + Estimated clock delay at ending point: 0.000 - = Required time: 10.000 - - - Propagation time: 0.000 - - Clock delay at starting point: 0.000 (ideal) - - Estimated clock delay at start point: -0.000 - = Slack (critical) : 10.000 - - Number of logic level(s): 0 - Starting point: PLLInst_0 / CLKOP - Ending point: PLLInst_0 / CLKFB - The start point is clocked by System [rising] - The end point is clocked by System [rising] - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------- -PLLInst_0 EHXPLLL CLKOP Out 0.000 0.000 - -CLKOP Net - - - - 2 -PLLInst_0 EHXPLLL CLKFB In 0.000 0.000 - -================================================================================= - - - -##### END OF TIMING REPORT #####] - - -Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB) - - -Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB) - ---------------------------------------- -Resource Usage Report -Part: lfe5um_25f-6 - -Register bits: 0 of 24288 (0%) -PIC Latch: 0 -I/O cells: 1 - - -Details: -EHXPLLL: 1 -GSR: 1 -IB: 1 -PUR: 1 -VHI: 1 -VLO: 1 -Mapper successful! - -At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 143MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Tue Mar 17 15:43:14 2015 - -###########################################################] - - diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100_toc.htm b/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100_toc.htm deleted file mode 100644 index 8c7cd79..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100_toc.htm +++ /dev/null @@ -1,44 +0,0 @@ - - - - - - - - - - - - - - \ No newline at end of file diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/run_option.xml b/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/run_option.xml deleted file mode 100644 index 3addc49..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/run_option.xml +++ /dev/null @@ -1,22 +0,0 @@ - - - - - - - - - - - - - - - diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/statusReport.html b/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/statusReport.html deleted file mode 100644 index 275f5ce..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/statusReport.html +++ /dev/null @@ -1,110 +0,0 @@ - - - Project Status Summary Page - - - - - -

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Project Settings
Project Name	pll_in200_out100	Implementation Name	syn_results
Top Module	pll_in200_out100	Pipelining	0
Retiming	0	Resource Sharing	1
Fanout Guide	50	Disable I/O Insertion	1
Clock Conversion	1	FSM Compiler	1

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Run Status
Job Name	Status				CPU Time	Real Time	Memory	Date/Time
(compiler)	Complete	10	1	0	-	00m:00s	-	17.03.2015 15:43
(premap)	Complete	2	0	0	0m:00s	0m:00s	140MB	17.03.2015 15:43
(fpga_mapper)	Complete	11	1	0	0m:01s	0m:01s	143MB	17.03.2015 15:43
Multi-srs Generator	Complete				00m:00s			17.03.2015 15:43

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Area Summary

Register bits	0	I/O cells	1
Block RAMs -(v_ram)	0	DSPs -(dsp_used)	0
ORCA LUTs -(total_luts)	0

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Timing Summary

Clock Name	Req Freq	Est Freq	Slack
System	100.0 MHz	NA	10.000

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Optimizations Summary
Combined Clock Conversion	0 / 0

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- \ No newline at end of file diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/.cckTransfer b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/.cckTransfer deleted file mode 100644 index c567c7c..0000000 Binary files a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/.cckTransfer and /dev/null differ diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/_mh_info b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/_mh_info deleted file mode 100644 index 37bc105..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/_mh_info +++ /dev/null @@ -1 +0,0 @@ -|1| diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/layer0.fdep b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/layer0.fdep deleted file mode 100644 index 524f434..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/layer0.fdep +++ /dev/null @@ -1,28 +0,0 @@ -#defaultlanguage:vhdl -#OPTIONS:"|-layerid|0|-top|pll_in200_out100|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work" -#CUR:"/opt/synopsys/J-2014.09-SP2/linux_a_64/c_vhdl":1416524537 -#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/location.map":1416524427 -#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/std.vhd":1416524427 -#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/snps_haps_pkg.vhd":1416524427 -#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/std1164.vhd":1416524427 -#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/numeric.vhd":1416524427 -#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/umr_capim.vhd":1416524427 -#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/arith.vhd":1416524427 -#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/unsigned.vhd":1416524427 -#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/hyperents.vhd":1416524427 -#CUR:"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":1426603391 -#CUR:"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":1416503391 -0 "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd" vhdl - -# Dependency Lists (Uses list) -0 -1 - -# Dependency Lists (Users Of) -0 -1 - -# Design Unit to File Association -arch work pll_in200_out100 structure 0 -module work pll_in200_out100 0 - - -# Configuration files used diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/layer0.fdeporig b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/layer0.fdeporig deleted file mode 100644 index ff57353..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/layer0.fdeporig +++ /dev/null @@ -1,24 +0,0 @@ -#defaultlanguage:vhdl -#OPTIONS:"|-layerid|0|-top|pll_in200_out100|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work" -#CUR:"/opt/synopsys/J-2014.09-SP2/linux_a_64/c_vhdl":1416524537 -#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/location.map":1416524427 -#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/std.vhd":1416524427 -#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/snps_haps_pkg.vhd":1416524427 -#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/std1164.vhd":1416524427 -#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/numeric.vhd":1416524427 -#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/umr_capim.vhd":1416524427 -#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/arith.vhd":1416524427 -#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/unsigned.vhd":1416524427 -#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/hyperents.vhd":1416524427 -#CUR:"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":1426603391 -0 "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd" vhdl - -# Dependency Lists (Uses list) -0 -1 - -# Dependency Lists (Users Of) -0 -1 - -# Design Unit to File Association -arch work pll_in200_out100 structure 0 -module work pll_in200_out100 0 diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/layer0.srs b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/layer0.srs deleted file mode 100644 index 7b4c239..0000000 Binary files a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/layer0.srs and /dev/null differ diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/layer0.tlg b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/layer0.tlg deleted file mode 100644 index 7aa3ebb..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/layer0.tlg +++ /dev/null @@ -1,11 +0,0 @@ -@N: CD630 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":12:7:12:22|Synthesizing work.pll_in200_out100.structure -@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":2081:10:2081:16|Synthesizing ecp5um.ehxplll.syn_black_box -Post processing for ecp5um.ehxplll.syn_black_box -@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":830:10:830:12|Synthesizing ecp5um.vlo.syn_black_box -Post processing for ecp5um.vlo.syn_black_box -@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":823:10:823:12|Synthesizing ecp5um.vhi.syn_black_box -Post processing for ecp5um.vhi.syn_black_box -@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":998:10:998:11|Synthesizing ecp5um.ib.syn_black_box -Post processing for ecp5um.ib.syn_black_box -Post processing for work.pll_in200_out100.structure -@W: CL168 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":55:4:55:17|Pruning instance scuba_vhi_inst -- not in use ... diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_comp.fdep b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_comp.fdep deleted file mode 100644 index 0b16619..0000000 --- a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_comp.fdep +++ /dev/null @@ -1,21 +0,0 @@ -#OPTIONS:"|-layerid|0|-top|pll_in200_out100|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work" -#CUR:"/opt/synopsys/J-2014.09-SP2/linux_a_64/c_vhdl":1416524537 -#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/location.map":1416524427 -#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/std.vhd":1416524427 -#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/snps_haps_pkg.vhd":1416524427 -#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/std1164.vhd":1416524427 -#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/numeric.vhd":1416524427 -#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/umr_capim.vhd":1416524427 -#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/arith.vhd":1416524427 -#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/unsigned.vhd":1416524427 -#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/hyperents.vhd":1416524427 -#CUR:"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":1426603391 -#CUR:"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":1416503391 -0 "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd" vhdl -#Dependency Lists(Uses List) -0 -1 -#Dependency Lists(Users Of) -0 -1 -#Design Unit to File Association -module work pll_in200_out100 0 -arch work pll_in200_out100 structure 0 diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_comp.srs b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_comp.srs deleted file mode 100644 index a123472..0000000 Binary files a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_comp.srs and /dev/null differ diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_m.srm b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_m.srm deleted file mode 100644 index 98174c4..0000000 Binary files a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_m.srm and /dev/null differ diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_mult.srs b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_mult.srs deleted file mode 100644 index 57d784a..0000000 Binary files a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_mult.srs and /dev/null differ diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_mult_srs/skeleton.srs b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_mult_srs/skeleton.srs deleted file mode 100644 index 977f6ae..0000000 Binary files a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_mult_srs/skeleton.srs and /dev/null differ diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_prem.fse b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_prem.fse deleted file mode 100644 index e69de29..0000000 diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_prem.srd b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_prem.srd deleted file mode 100644 index 088c601..0000000 Binary files a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_prem.srd and /dev/null differ diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_s.srm b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_s.srm deleted file mode 100644 index ea888b6..0000000 Binary files a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_s.srm and /dev/null differ diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_s.srs b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_s.srs deleted file mode 100644 index a123472..0000000 Binary files a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_s.srs and /dev/null differ