From: Michael Boehmer Date: Fri, 5 Aug 2022 06:46:33 +0000 (+0200) Subject: first Trudy/Eve combination X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=a256e47d666642803f2b6537b794b9bf079e0ef2;p=trbnet.git first Trudy/Eve combination --- diff --git a/gbe_trb/base/inserter.vhd b/gbe_trb/base/inserter.vhd new file mode 100644 index 0000000..669ac3c --- /dev/null +++ b/gbe_trb/base/inserter.vhd @@ -0,0 +1,144 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; + +entity inserter is + port( + CLK : in std_logic; + RESET : in std_logic; + -- PHY output + PHY_D_IN : in std_logic_vector(7 downto 0); + PHY_K_IN : in std_logic; + PHY_CD_IN : in std_logic; + -- SerDes input + TX_D_OUT : out std_logic_vector(7 downto 0); + TX_K_OUT : out std_logic; + TX_CD_OUT : out std_logic; + -- DLM stuff + DLM_DATA_IN : in std_logic_vector(7 downto 0); + DLM_INJECT_IN : in std_logic + ); +end entity inserter; + +architecture inserter_arch of inserter is + +-- Components + component fifo_inserter + port( + DATA : in std_logic_vector(9 downto 0); + CLOCK : in std_logic; + WREN : in std_logic; + RDEN : in std_logic; + RESET : in std_logic; + WCNT : out std_logic_vector(4 downto 0); + Q : out std_logic_vector(9 downto 0); + EMPTY : out std_logic; + FULL : out std_logic; + ALMOSTEMPTY : out std_logic + ); + end component fifo_inserter; + +-- Signals + signal tx_cd_int : std_logic; + signal tx_k_int : std_logic; + signal tx_d_int : std_logic_vector(7 downto 0); + signal fifo_rd_x : std_logic; + signal fifo_wr_x : std_logic; + signal fifo_empty_x : std_logic; + + signal inject_k : std_logic; + signal inject_d : std_logic; + + signal phy_cd_q : std_logic; + signal phy_k_q : std_logic; + signal phy_d_q : std_logic_vector(7 downto 0); + + signal idle_x : std_logic; + signal idle_int : std_logic; + + signal remove_x : std_logic; + signal remove_int : std_logic; + + signal drop_req_x : std_logic; + + signal ins_cnt : unsigned(2 downto 0); + +begin + + -- Syncing and delaying signals for /IT recognition + THE_SYNC_PROC: process( CLK ) + begin + if( rising_edge(CLK) ) then + phy_d_q <= PHY_D_IN; + phy_k_q <= PHY_K_IN; + phy_cd_q <= PHY_CD_IN; + idle_int <= idle_x; + remove_int <= remove_x; + end if; + end process THE_SYNC_PROC; + + -- we have an /I/ candidate for dropping + idle_x <= '1' when ((phy_d_q = x"bc") and (phy_k_q = '1') and (phy_cd_q = '0') and + (PHY_D_IN = x"50") and (PHY_K_IN = '0') and (PHY_CD_IN = '0')) + else '0'; + + -- insert counter + THE_INSERT_COUNTER_PROC: process( CLK ) + begin + if( rising_edge(CLK) ) then + if ( RESET = '1' ) then + ins_cnt <= (others => '0'); + elsif( (DLM_INJECT_IN = '1') and (remove_x = '0') ) then + ins_cnt <= ins_cnt + 1; + elsif( (DLM_INJECT_IN = '0') and (remove_x = '1') ) then + ins_cnt <= ins_cnt - 1; + end if; + end if; + end process THE_INSERT_COUNTER_PROC; + + -- we need to drop at least one /I/ + drop_req_x <= '1' when (ins_cnt /= b"000") else '0'; + + remove_x <= drop_req_x and idle_int; + + fifo_wr_x <= '0' when ((remove_x = '1') or (remove_int = '1')) + else '1'; + + -- FIFO + THE_FIFO: fifo_inserter + port map( + DATA(9) => phy_cd_q, + DATA(8) => phy_k_q, + DATA(7 downto 0) => phy_d_q, + CLOCK => CLK, + WREN => fifo_wr_x, + RDEN => fifo_rd_x, + RESET => RESET, + Q(9) => tx_cd_int, + Q(8) => tx_k_int, + Q(7 downto 0) => tx_d_int, + EMPTY => open, + FULL => open, + ALMOSTEMPTY => fifo_empty_x + ); + + -- + fifo_rd_x <= '0' when ((fifo_empty_x = '1') or (DLM_INJECT_IN = '1') or (inject_k = '1')) + else '1'; + + TX_CD_OUT <= tx_cd_int; + + inject_k <= DLM_INJECT_IN when rising_edge(CLK); + inject_d <= inject_k when rising_edge(CLK); + + TX_K_OUT <= '1' when inject_k = '1' else + '0' when inject_d = '1' else + tx_k_int; + TX_D_OUT <= x"dc" when inject_k = '1' else + DLM_DATA_IN when inject_d = '1' else -- payload is here + tx_d_int; + + +end architecture; diff --git a/gbe_trb/base/remover.vhd b/gbe_trb/base/remover.vhd new file mode 100644 index 0000000..e2f272c --- /dev/null +++ b/gbe_trb/base/remover.vhd @@ -0,0 +1,181 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; + +entity remover is + port( + CLK : in std_logic; + RESET : in std_logic; + -- SerDes output + RX_D_IN : in std_logic_vector(7 downto 0); + RX_K_IN : in std_logic; + -- PHY input + PHY_D_OUT : out std_logic_vector(7 downto 0); + PHY_K_OUT : out std_logic; + -- DLM stuff + DLM_DATA_OUT : out std_logic_vector(7 downto 0); + DLM_FOUND_OUT : out std_logic + ); +end entity remover; + +architecture remover_arch of remover is + +-- Components + component fifo_remover + port( + DATA : in std_logic_vector(8 downto 0); + CLOCK : in std_logic; + WREN : in std_logic; + RDEN : in std_logic; + RESET : in std_logic; + WCNT : out std_logic_vector(4 downto 0); + Q : out std_logic_vector(8 downto 0); + FULL : out std_logic; + ALMOSTFULL : out std_logic + ); + end component fifo_remover; + +-- state machine signals + type state_t is (FILL, IDLE, ONE, TWO, THREE); + signal STATE, NEXT_STATE : state_t; + +-- Signals + signal dlm_found_x : std_logic; + signal dlm_found : std_logic; + signal fifo_wr_x : std_logic; + signal fifofull : std_logic; + signal phy_k_fifo : std_logic; + signal phy_d_fifo : std_logic_vector(7 downto 0); + signal fifo_rd_x : std_logic; + signal replace_k_x : std_logic; + signal replace_k : std_logic; + signal replace_d_x : std_logic; + signal replace_d : std_logic; + signal dlm_data_int : std_logic_vector(7 downto 0); + +begin + + -- DLM komma detected in data stream + dlm_found_x <= '1' when ((RX_K_IN = '1') and (RX_D_IN = x"dc")) else '0'; + + dlm_found <= dlm_found_x when rising_edge(CLK); + + DLM_FOUND_OUT <= dlm_found; + + THE_STORE_PROC: process( CLK ) + begin + if( rising_edge(CLK) ) then + if ( RESET = '1' ) then + dlm_data_int <= (others => '0'); + elsif( dlm_found = '1' ) then + dlm_data_int <= RX_D_IN; + end if; + end if; + end process THE_STORE_PROC; + + DLM_DATA_OUT <= dlm_data_int; + + -- write signal for FIFO + fifo_wr_x <= '0' when ((dlm_found_x = '1') or (dlm_found = '1')) else '1'; + + -- FIFO + THE_FIFO: fifo_remover + port map( + DATA(8) => RX_K_IN, + DATA(7 downto 0) => RX_D_IN, + CLOCK => CLK, + WREN => fifo_wr_x, + RDEN => fifo_rd_x, + RESET => RESET, + Q(8) => phy_k_fifo, + Q(7 downto 0) => phy_d_fifo, + WCNT => open, + FULL => open, + ALMOSTFULL => fifofull + ); + + -- read signal for FIFO + fifo_rd_x <= '0' when (STATE = FILL) or + (replace_k = '1') or + (replace_d = '1') + else '1'; + + -- K to PHY, multiplexed + PHY_K_OUT <= '1' when (replace_k = '1') else + '0' when (replace_d = '1') else + phy_k_fifo; + + -- data to PHY, multiplexed + PHY_D_OUT <= x"bc" when (replace_k = '1') else + x"50" when (replace_d = '1') else + phy_d_fifo; + + ----------------------------------------------------------- + -- statemachine: clocked process + ----------------------------------------------------------- + THE_FSM: process( CLK ) + begin + if( rising_edge(CLK) ) then + if( RESET = '1' ) then + STATE <= FILL; + replace_k <= '0'; + replace_d <= '0'; + else + STATE <= NEXT_STATE; + replace_k <= replace_k_x; + replace_d <= replace_d_x; + end if; + end if; + end process THE_FSM; + + ----------------------------------------------------------- + -- staemachine: transitions + ----------------------------------------------------------- + THE_STATE_TRANSITIONS: process( STATE, RX_D_IN, RX_K_IN, phy_k_fifo, phy_d_fifo, fifofull ) + begin + replace_k_x <= '0'; + replace_d_x <= '0'; + + case STATE is + when FILL => + if( (RX_K_IN = '1') and (RX_D_IN = x"bc") and (fifofull = '1') ) then + NEXT_STATE <= IDLE; + else + NEXT_STATE <= FILL; + end if; + + when IDLE => + if( (phy_k_fifo = '1') and (phy_d_fifo = x"bc") and (fifofull = '0')) then + NEXT_STATE <= ONE; + else + NEXT_STATE <= IDLE; + end if; + + when ONE => + if( (phy_k_fifo = '0') and (phy_d_fifo = x"50")) then + NEXT_STATE <= TWO; + replace_k_x <= '1'; + else + NEXT_STATE <= IDLE; + end if; + + when TWO => + NEXT_STATE <= THREE; + replace_d_x <= '1'; + + when THREE => + if( fifofull = '0' ) then + NEXT_STATE <= TWO; + replace_k_x <= '1'; + else + NEXT_STATE <= IDLE; + end if; + + when others => + NEXT_STATE <= IDLE; + end case; + end process THE_STATE_TRANSITIONS; + +end architecture; diff --git a/gbe_trb_ecp5/cores/fifo_inserter.vhd b/gbe_trb_ecp5/cores/fifo_inserter.vhd new file mode 100644 index 0000000..4bfb5fc --- /dev/null +++ b/gbe_trb_ecp5/cores/fifo_inserter.vhd @@ -0,0 +1,571 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 +-- Module Version: 5.1 +--C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n fifo_inserter -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00 -type ebfifo -sync_mode -pfu_fifo -depth 16 -width 10 -no_enable -pe 2 -pf -1 -reset_rel ASYNC -fill -fdc C:/VHDL_Projects/remover/damned_fifo/fifo_inserter/fifo_inserter.fdc + +-- Sat Jul 30 18:07:53 2022 + +library IEEE; +use IEEE.std_logic_1164.all; +library ECP5U; +use ECP5U.components.all; + +entity fifo_inserter is + port ( + Data: in std_logic_vector(9 downto 0); + Clock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + Q: out std_logic_vector(9 downto 0); + WCNT: out std_logic_vector(4 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostEmpty: out std_logic); +end fifo_inserter; + +architecture Structure of fifo_inserter is + + -- internal signal declarations + signal invout_2: std_logic; + signal invout_1: std_logic; + signal rden_i_inv: std_logic; + signal invout_0: std_logic; + signal r_nw_inv: std_logic; + signal r_nw: std_logic; + signal fcnt_en_inv: std_logic; + signal fcnt_en: std_logic; + signal empty_i: std_logic; + signal empty_d: std_logic; + signal full_i: std_logic; + signal full_d: std_logic; + signal ifcount_0: std_logic; + signal ifcount_1: std_logic; + signal bdcnt_bctr_ci: std_logic; + signal ifcount_2: std_logic; + signal ifcount_3: std_logic; + signal co0: std_logic; + signal ifcount_4: std_logic; + signal co2: std_logic; + signal cnt_con: std_logic; + signal co1: std_logic; + signal cmp_ci: std_logic; + signal rden_i: std_logic; + signal co0_1: std_logic; + signal co1_1: std_logic; + signal cmp_le_1: std_logic; + signal cmp_le_1_c: std_logic; + signal cmp_ci_1: std_logic; + signal co0_2: std_logic; + signal wren_i: std_logic; + signal co1_2: std_logic; + signal wren_i_inv: std_logic; + signal cmp_ge_d1: std_logic; + signal cmp_ge_d1_c: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_ctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0_3: std_logic; + signal iwcount_4: std_logic; + signal co2_1: std_logic; + signal co1_3: std_logic; + signal wcount_4: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_ctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_4: std_logic; + signal ircount_4: std_logic; + signal co2_2: std_logic; + signal co1_4: std_logic; + signal rcount_4: std_logic; + signal cmp_ci_2: std_logic; + signal fcnt_en_inv_inv: std_logic; + signal cnt_con_inv: std_logic; + signal fcount_0: std_logic; + signal fcount_1: std_logic; + signal co0_5: std_logic; + signal fcount_2: std_logic; + signal fcount_3: std_logic; + signal co1_5: std_logic; + signal fcount_4: std_logic; + signal ae_d: std_logic; + signal scuba_vlo: std_logic; + signal ae_d_c: std_logic; + signal rdataout9: std_logic; + signal rdataout8: std_logic; + signal scuba_vhi: std_logic; + signal rdataout7: std_logic; + signal rdataout6: std_logic; + signal rdataout5: std_logic; + signal rdataout4: std_logic; + signal rdataout3: std_logic; + signal rdataout2: std_logic; + signal rdataout1: std_logic; + signal rdataout0: std_logic; + signal rcount_3: std_logic; + signal rcount_2: std_logic; + signal rcount_1: std_logic; + signal rcount_0: std_logic; + signal dec0_wre3: std_logic; + signal wcount_3: std_logic; + signal wcount_2: std_logic; + signal wcount_1: std_logic; + signal wcount_0: std_logic; + + attribute GSR : string; + attribute MEM_INIT_FILE : string; + attribute MEM_LPC_FILE : string; + attribute COMP : string; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute MEM_INIT_FILE of fifo_pfu_0_0 : label is "(0-15)(0-3)"; + attribute MEM_LPC_FILE of fifo_pfu_0_0 : label is "fifo_inserter.lpc"; + attribute COMP of fifo_pfu_0_0 : label is "fifo_pfu_0_0"; + attribute MEM_INIT_FILE of fifo_pfu_0_1 : label is "(0-15)(4-7)"; + attribute MEM_LPC_FILE of fifo_pfu_0_1 : label is "fifo_inserter.lpc"; + attribute COMP of fifo_pfu_0_1 : label is "fifo_pfu_0_1"; + attribute MEM_INIT_FILE of fifo_pfu_0_2 : label is "(0-15)(8-9)"; + attribute MEM_LPC_FILE of fifo_pfu_0_2 : label is "fifo_inserter.lpc"; + attribute COMP of fifo_pfu_0_2 : label is "fifo_pfu_0_2"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t4: AND2 + port map (A=>WrEn, B=>invout_2, Z=>wren_i); + + INV_8: INV + port map (A=>full_i, Z=>invout_2); + + AND2_t3: AND2 + port map (A=>RdEn, B=>invout_1, Z=>rden_i); + + INV_7: INV + port map (A=>empty_i, Z=>invout_1); + + AND2_t2: AND2 + port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con); + + XOR2_t1: XOR2 + port map (A=>wren_i, B=>rden_i, Z=>fcnt_en); + + INV_6: INV + port map (A=>rden_i, Z=>rden_i_inv); + + INV_5: INV + port map (A=>wren_i, Z=>wren_i_inv); + + LUT4_2: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, + AD0=>empty_i, DO0=>empty_d); + + LUT4_1: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, + AD0=>full_i, DO0=>full_d); + + LUT4_0: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>scuba_vhi, AD2=>wren_i, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec0_wre3); + + AND2_t0: AND2 + port map (A=>rden_i, B=>invout_0, Z=>r_nw); + + INV_4: INV + port map (A=>wren_i, Z=>invout_0); + + INV_3: INV + port map (A=>fcnt_en, Z=>fcnt_en_inv); + + INV_2: INV + port map (A=>cnt_con, Z=>cnt_con_inv); + + INV_1: INV + port map (A=>r_nw, Z=>r_nw_inv); + + INV_0: INV + port map (A=>fcnt_en_inv, Z=>fcnt_en_inv_inv); + + FF_27: FD1P3DX + port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_0); + + FF_26: FD1P3DX + port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_1); + + FF_25: FD1P3DX + port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_2); + + FF_24: FD1P3DX + port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_3); + + FF_23: FD1P3DX + port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_4); + + FF_22: FD1S3BX + port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i); + + FF_21: FD1S3DX + port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i); + + FF_20: FD1P3DX + port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_0); + + FF_19: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_1); + + FF_18: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_2); + + FF_17: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_3); + + FF_16: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_4); + + FF_15: FD1P3DX + port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_0); + + FF_14: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_1); + + FF_13: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_2); + + FF_12: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_3); + + FF_11: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_4); + + FF_10: FD1P3DX + port map (D=>rdataout0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(0)); + + FF_9: FD1P3DX + port map (D=>rdataout1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(1)); + + FF_8: FD1P3DX + port map (D=>rdataout2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(2)); + + FF_7: FD1P3DX + port map (D=>rdataout3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(3)); + + FF_6: FD1P3DX + port map (D=>rdataout4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(4)); + + FF_5: FD1P3DX + port map (D=>rdataout5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(5)); + + FF_4: FD1P3DX + port map (D=>rdataout6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(6)); + + FF_3: FD1P3DX + port map (D=>rdataout7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(7)); + + FF_2: FD1P3DX + port map (D=>rdataout8, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(8)); + + FF_1: FD1P3DX + port map (D=>rdataout9, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(9)); + + FF_0: FD1S3BX + port map (D=>ae_d, CK=>Clock, PD=>Reset, Q=>AlmostEmpty); + + bdcnt_bctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>'X', S0=>open, S1=>open, COUT=>bdcnt_bctr_ci); + + bdcnt_bctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_0, A1=>fcount_1, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>bdcnt_bctr_ci, S0=>ifcount_0, S1=>ifcount_1, COUT=>co0); + + bdcnt_bctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0, S0=>ifcount_2, S1=>ifcount_3, COUT=>co1); + + bdcnt_bctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_4, A1=>scuba_vlo, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1, S0=>ifcount_4, S1=>open, COUT=>co2); + + e_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci); + + e_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rden_i, A1=>scuba_vlo, B0=>fcount_0, B1=>fcount_1, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>cmp_ci, S0=>open, S1=>open, COUT=>co0_1); + + e_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_2, + B1=>fcount_3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_1, S0=>open, S1=>open, COUT=>co1_1); + + e_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_4, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_1, S0=>open, S1=>open, + COUT=>cmp_le_1_c); + + a0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_le_1_c, S0=>cmp_le_1, S1=>open, + COUT=>open); + + g_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_1); + + g_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>cmp_ci_1, S0=>open, S1=>open, COUT=>co0_2); + + g_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0_2, S0=>open, S1=>open, COUT=>co1_2); + + g_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_4, A1=>scuba_vlo, B0=>wren_i_inv, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_2, S0=>open, S1=>open, + COUT=>cmp_ge_d1_c); + + a1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_ge_d1_c, S0=>cmp_ge_d1, S1=>open, + COUT=>open); + + w_ctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>w_ctr_ci); + + w_ctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>w_ctr_ci, S0=>iwcount_0, S1=>iwcount_1, + COUT=>co0_3); + + w_ctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_3, S0=>iwcount_2, S1=>iwcount_3, + COUT=>co1_3); + + w_ctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_4, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_3, S0=>iwcount_4, S1=>open, + COUT=>co2_1); + + r_ctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>r_ctr_ci); + + r_ctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>r_ctr_ci, S0=>ircount_0, S1=>ircount_1, + COUT=>co0_4); + + r_ctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_2, A1=>rcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_4, S0=>ircount_2, S1=>ircount_3, + COUT=>co1_4); + + r_ctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_4, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_4, S0=>ircount_4, S1=>open, + COUT=>co2_2); + + ae_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_2); + + ae_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcnt_en_inv_inv, A1=>cnt_con_inv, B0=>fcount_0, + B1=>fcount_1, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_ci_2, S0=>open, S1=>open, + COUT=>co0_5); + + ae_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_2, + B1=>fcount_3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_5, S0=>open, S1=>open, COUT=>co1_5); + + ae_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_4, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_5, S0=>open, S1=>open, COUT=>ae_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>ae_d_c, S0=>ae_d, S1=>open, COUT=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + fifo_pfu_0_0: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Data(8), DI1=>Data(9), DI2=>scuba_vhi, + DI3=>scuba_vhi, WCK=>Clock, WRE=>dec0_wre3, RAD0=>rcount_0, + RAD1=>rcount_1, RAD2=>rcount_2, RAD3=>rcount_3, + WAD0=>wcount_0, WAD1=>wcount_1, WAD2=>wcount_2, + WAD3=>wcount_3, DO0=>rdataout8, DO1=>rdataout9, DO2=>open, + DO3=>open); + + fifo_pfu_0_1: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Data(4), DI1=>Data(5), DI2=>Data(6), DI3=>Data(7), + WCK=>Clock, WRE=>dec0_wre3, RAD0=>rcount_0, RAD1=>rcount_1, + RAD2=>rcount_2, RAD3=>rcount_3, WAD0=>wcount_0, + WAD1=>wcount_1, WAD2=>wcount_2, WAD3=>wcount_3, + DO0=>rdataout4, DO1=>rdataout5, DO2=>rdataout6, + DO3=>rdataout7); + + fifo_pfu_0_2: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + WCK=>Clock, WRE=>dec0_wre3, RAD0=>rcount_0, RAD1=>rcount_1, + RAD2=>rcount_2, RAD3=>rcount_3, WAD0=>wcount_0, + WAD1=>wcount_1, WAD2=>wcount_2, WAD3=>wcount_3, + DO0=>rdataout0, DO1=>rdataout1, DO2=>rdataout2, + DO3=>rdataout3); + + WCNT(0) <= fcount_0; + WCNT(1) <= fcount_1; + WCNT(2) <= fcount_2; + WCNT(3) <= fcount_3; + WCNT(4) <= fcount_4; + Empty <= empty_i; + Full <= full_i; +end Structure; diff --git a/gbe_trb_ecp5/cores/fifo_remover.vhd b/gbe_trb_ecp5/cores/fifo_remover.vhd new file mode 100644 index 0000000..f586cea --- /dev/null +++ b/gbe_trb_ecp5/cores/fifo_remover.vhd @@ -0,0 +1,565 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 +-- Module Version: 5.1 +--C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n fifo_remover -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00 -type ebfifo -sync_mode -pfu_fifo -depth 16 -width 9 -no_enable -pe -1 -pf 14 -reset_rel ASYNC -fill -fdc C:/VHDL_Projects/remover/damned_fifo/fifo_remover/fifo_remover.fdc + +-- Sat Jul 30 16:36:18 2022 + +library IEEE; +use IEEE.std_logic_1164.all; +library ECP5U; +use ECP5U.components.all; + +entity fifo_remover is + port ( + Data: in std_logic_vector(8 downto 0); + Clock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + Q: out std_logic_vector(8 downto 0); + WCNT: out std_logic_vector(4 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostFull: out std_logic); +end fifo_remover; + +architecture Structure of fifo_remover is + + -- internal signal declarations + signal invout_2: std_logic; + signal invout_1: std_logic; + signal rden_i_inv: std_logic; + signal invout_0: std_logic; + signal r_nw_inv: std_logic; + signal r_nw: std_logic; + signal fcnt_en_inv: std_logic; + signal fcnt_en: std_logic; + signal empty_i: std_logic; + signal empty_d: std_logic; + signal full_i: std_logic; + signal full_d: std_logic; + signal ifcount_0: std_logic; + signal ifcount_1: std_logic; + signal bdcnt_bctr_ci: std_logic; + signal ifcount_2: std_logic; + signal ifcount_3: std_logic; + signal co0: std_logic; + signal ifcount_4: std_logic; + signal co2: std_logic; + signal cnt_con: std_logic; + signal co1: std_logic; + signal cmp_ci: std_logic; + signal rden_i: std_logic; + signal co0_1: std_logic; + signal co1_1: std_logic; + signal cmp_le_1: std_logic; + signal cmp_le_1_c: std_logic; + signal cmp_ci_1: std_logic; + signal co0_2: std_logic; + signal wren_i: std_logic; + signal co1_2: std_logic; + signal wren_i_inv: std_logic; + signal cmp_ge_d1: std_logic; + signal cmp_ge_d1_c: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_ctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0_3: std_logic; + signal iwcount_4: std_logic; + signal co2_1: std_logic; + signal co1_3: std_logic; + signal wcount_4: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_ctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_4: std_logic; + signal ircount_4: std_logic; + signal co2_2: std_logic; + signal co1_4: std_logic; + signal rcount_4: std_logic; + signal cmp_ci_2: std_logic; + signal fcnt_en_inv_inv: std_logic; + signal cnt_con_inv: std_logic; + signal fcount_0: std_logic; + signal fcount_1: std_logic; + signal co0_5: std_logic; + signal fcount_2: std_logic; + signal fcount_3: std_logic; + signal co1_5: std_logic; + signal fcount_4: std_logic; + signal af_d: std_logic; + signal scuba_vlo: std_logic; + signal af_d_c: std_logic; + signal rdataout8: std_logic; + signal scuba_vhi: std_logic; + signal rdataout7: std_logic; + signal rdataout6: std_logic; + signal rdataout5: std_logic; + signal rdataout4: std_logic; + signal rdataout3: std_logic; + signal rdataout2: std_logic; + signal rdataout1: std_logic; + signal rdataout0: std_logic; + signal rcount_3: std_logic; + signal rcount_2: std_logic; + signal rcount_1: std_logic; + signal rcount_0: std_logic; + signal dec0_wre3: std_logic; + signal wcount_3: std_logic; + signal wcount_2: std_logic; + signal wcount_1: std_logic; + signal wcount_0: std_logic; + + attribute GSR : string; + attribute MEM_INIT_FILE : string; + attribute MEM_LPC_FILE : string; + attribute COMP : string; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute MEM_INIT_FILE of fifo_pfu_0_0 : label is "(0-15)(0-3)"; + attribute MEM_LPC_FILE of fifo_pfu_0_0 : label is "fifo_remover.lpc"; + attribute COMP of fifo_pfu_0_0 : label is "fifo_pfu_0_0"; + attribute MEM_INIT_FILE of fifo_pfu_0_1 : label is "(0-15)(4-7)"; + attribute MEM_LPC_FILE of fifo_pfu_0_1 : label is "fifo_remover.lpc"; + attribute COMP of fifo_pfu_0_1 : label is "fifo_pfu_0_1"; + attribute MEM_INIT_FILE of fifo_pfu_0_2 : label is "(0-15)(8-8)"; + attribute MEM_LPC_FILE of fifo_pfu_0_2 : label is "fifo_remover.lpc"; + attribute COMP of fifo_pfu_0_2 : label is "fifo_pfu_0_2"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t4: AND2 + port map (A=>WrEn, B=>invout_2, Z=>wren_i); + + INV_8: INV + port map (A=>full_i, Z=>invout_2); + + AND2_t3: AND2 + port map (A=>RdEn, B=>invout_1, Z=>rden_i); + + INV_7: INV + port map (A=>empty_i, Z=>invout_1); + + AND2_t2: AND2 + port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con); + + XOR2_t1: XOR2 + port map (A=>wren_i, B=>rden_i, Z=>fcnt_en); + + INV_6: INV + port map (A=>rden_i, Z=>rden_i_inv); + + INV_5: INV + port map (A=>wren_i, Z=>wren_i_inv); + + LUT4_2: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, + AD0=>empty_i, DO0=>empty_d); + + LUT4_1: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, + AD0=>full_i, DO0=>full_d); + + LUT4_0: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>scuba_vhi, AD2=>wren_i, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec0_wre3); + + AND2_t0: AND2 + port map (A=>rden_i, B=>invout_0, Z=>r_nw); + + INV_4: INV + port map (A=>wren_i, Z=>invout_0); + + INV_3: INV + port map (A=>fcnt_en, Z=>fcnt_en_inv); + + INV_2: INV + port map (A=>cnt_con, Z=>cnt_con_inv); + + INV_1: INV + port map (A=>r_nw, Z=>r_nw_inv); + + INV_0: INV + port map (A=>fcnt_en_inv, Z=>fcnt_en_inv_inv); + + FF_26: FD1P3DX + port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_0); + + FF_25: FD1P3DX + port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_1); + + FF_24: FD1P3DX + port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_2); + + FF_23: FD1P3DX + port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_3); + + FF_22: FD1P3DX + port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_4); + + FF_21: FD1S3BX + port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i); + + FF_20: FD1S3DX + port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i); + + FF_19: FD1P3DX + port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_0); + + FF_18: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_1); + + FF_17: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_2); + + FF_16: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_3); + + FF_15: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_4); + + FF_14: FD1P3DX + port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_0); + + FF_13: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_1); + + FF_12: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_2); + + FF_11: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_3); + + FF_10: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_4); + + FF_9: FD1P3DX + port map (D=>rdataout0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(0)); + + FF_8: FD1P3DX + port map (D=>rdataout1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(1)); + + FF_7: FD1P3DX + port map (D=>rdataout2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(2)); + + FF_6: FD1P3DX + port map (D=>rdataout3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(3)); + + FF_5: FD1P3DX + port map (D=>rdataout4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(4)); + + FF_4: FD1P3DX + port map (D=>rdataout5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(5)); + + FF_3: FD1P3DX + port map (D=>rdataout6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(6)); + + FF_2: FD1P3DX + port map (D=>rdataout7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(7)); + + FF_1: FD1P3DX + port map (D=>rdataout8, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(8)); + + FF_0: FD1S3DX + port map (D=>af_d, CK=>Clock, CD=>Reset, Q=>AlmostFull); + + bdcnt_bctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>'X', S0=>open, S1=>open, COUT=>bdcnt_bctr_ci); + + bdcnt_bctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_0, A1=>fcount_1, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>bdcnt_bctr_ci, S0=>ifcount_0, S1=>ifcount_1, COUT=>co0); + + bdcnt_bctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0, S0=>ifcount_2, S1=>ifcount_3, COUT=>co1); + + bdcnt_bctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_4, A1=>scuba_vlo, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1, S0=>ifcount_4, S1=>open, COUT=>co2); + + e_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci); + + e_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rden_i, A1=>scuba_vlo, B0=>fcount_0, B1=>fcount_1, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>cmp_ci, S0=>open, S1=>open, COUT=>co0_1); + + e_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_2, + B1=>fcount_3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_1, S0=>open, S1=>open, COUT=>co1_1); + + e_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_4, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_1, S0=>open, S1=>open, + COUT=>cmp_le_1_c); + + a0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_le_1_c, S0=>cmp_le_1, S1=>open, + COUT=>open); + + g_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_1); + + g_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>cmp_ci_1, S0=>open, S1=>open, COUT=>co0_2); + + g_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0_2, S0=>open, S1=>open, COUT=>co1_2); + + g_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_4, A1=>scuba_vlo, B0=>wren_i_inv, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_2, S0=>open, S1=>open, + COUT=>cmp_ge_d1_c); + + a1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_ge_d1_c, S0=>cmp_ge_d1, S1=>open, + COUT=>open); + + w_ctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>w_ctr_ci); + + w_ctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>w_ctr_ci, S0=>iwcount_0, S1=>iwcount_1, + COUT=>co0_3); + + w_ctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_3, S0=>iwcount_2, S1=>iwcount_3, + COUT=>co1_3); + + w_ctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_4, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_3, S0=>iwcount_4, S1=>open, + COUT=>co2_1); + + r_ctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>r_ctr_ci); + + r_ctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>r_ctr_ci, S0=>ircount_0, S1=>ircount_1, + COUT=>co0_4); + + r_ctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_2, A1=>rcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_4, S0=>ircount_2, S1=>ircount_3, + COUT=>co1_4); + + r_ctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_4, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_4, S0=>ircount_4, S1=>open, + COUT=>co2_2); + + af_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_2); + + af_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_0, A1=>fcount_1, B0=>fcnt_en_inv_inv, + B1=>cnt_con_inv, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_ci_2, S0=>open, S1=>open, + COUT=>co0_5); + + af_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_5, S0=>open, S1=>open, COUT=>co1_5); + + af_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_4, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_5, S0=>open, S1=>open, COUT=>af_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>af_d_c, S0=>af_d, S1=>open, COUT=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + fifo_pfu_0_0: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Data(8), DI1=>scuba_vhi, DI2=>scuba_vhi, + DI3=>scuba_vhi, WCK=>Clock, WRE=>dec0_wre3, RAD0=>rcount_0, + RAD1=>rcount_1, RAD2=>rcount_2, RAD3=>rcount_3, + WAD0=>wcount_0, WAD1=>wcount_1, WAD2=>wcount_2, + WAD3=>wcount_3, DO0=>rdataout8, DO1=>open, DO2=>open, + DO3=>open); + + fifo_pfu_0_1: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Data(4), DI1=>Data(5), DI2=>Data(6), DI3=>Data(7), + WCK=>Clock, WRE=>dec0_wre3, RAD0=>rcount_0, RAD1=>rcount_1, + RAD2=>rcount_2, RAD3=>rcount_3, WAD0=>wcount_0, + WAD1=>wcount_1, WAD2=>wcount_2, WAD3=>wcount_3, + DO0=>rdataout4, DO1=>rdataout5, DO2=>rdataout6, + DO3=>rdataout7); + + fifo_pfu_0_2: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + WCK=>Clock, WRE=>dec0_wre3, RAD0=>rcount_0, RAD1=>rcount_1, + RAD2=>rcount_2, RAD3=>rcount_3, WAD0=>wcount_0, + WAD1=>wcount_1, WAD2=>wcount_2, WAD3=>wcount_3, + DO0=>rdataout0, DO1=>rdataout1, DO2=>rdataout2, + DO3=>rdataout3); + + WCNT(0) <= fcount_0; + WCNT(1) <= fcount_1; + WCNT(2) <= fcount_2; + WCNT(3) <= fcount_3; + WCNT(4) <= fcount_4; + Empty <= empty_i; + Full <= full_i; +end Structure; diff --git a/gbe_trb_ecp5/media/gbe_med_fifo.vhd b/gbe_trb_ecp5/media/gbe_med_fifo.vhd index 564f456..6dd9a9d 100644 --- a/gbe_trb_ecp5/media/gbe_med_fifo.vhd +++ b/gbe_trb_ecp5/media/gbe_med_fifo.vhd @@ -56,6 +56,11 @@ entity gbe_med_fifo is PCS_AN_READY_OUT : out std_logic; -- for internal SCTRL LINK_ACTIVE_OUT : out std_logic; -- for internal SCTRL TICK_MS_IN : in std_logic; + -- DLM + DLM_INJECT_IN : in std_logic; + DLM_DATA_IN : in std_logic_vector(7 downto 0); + DLM_FOUND_OUT : out std_logic; + DLM_DATA_OUT : out std_logic_vector(7 downto 0); -- Debug STATUS_OUT : out std_logic_vector(7 downto 0); DEBUG_OUT : out std_logic_vector(63 downto 0) @@ -174,14 +179,20 @@ architecture gbe_med_fifo_arch of gbe_med_fifo is ); end component; + signal sd_tx_kcntl_src : std_logic_vector(0 downto 0); + signal sd_tx_kcntl_dst : std_logic_vector(0 downto 0); + signal sd_tx_data_src : std_logic_vector(7 downto 0); + signal sd_tx_data_dst : std_logic_vector(7 downto 0); + signal sd_tx_correct_disp_src : std_logic_vector(0 downto 0); + signal sd_tx_correct_disp_dst : std_logic_vector(0 downto 0); + signal sd_rx_data_src : std_logic_vector(7 downto 0); + signal sd_rx_data_dst : std_logic_vector(7 downto 0); + signal sd_rx_kcntl_src : std_logic_vector(0 downto 0); + signal sd_rx_kcntl_dst : std_logic_vector(0 downto 0); + signal sd_rx_clk : std_logic; - signal sd_tx_kcntl : std_logic_vector(0 downto 0); - signal sd_tx_data : std_logic_vector(7 downto 0); signal xmit : std_logic_vector(0 downto 0); - signal sd_tx_correct_disp : std_logic_vector(0 downto 0); - signal sd_rx_data : std_logic_vector(7 downto 0); - signal sd_rx_kcntl : std_logic_vector(0 downto 0); - signal sd_rx_disp_error : std_logic_vector(0 downto 0); + signal sd_rx_disp_error : std_logic_vector(0 downto 0); signal sd_rx_cv_error : std_logic_vector(0 downto 0); signal lsm_status : std_logic; signal rx_clk_en : std_logic; @@ -285,13 +296,13 @@ begin tx_pclk => open, -- not really needed rx_pclk => sd_rx_clk, -- recovered RX clock, also used on FIFO! -- TX channel - txdata => sd_tx_data, - tx_k => sd_tx_kcntl, - tx_disp_correct => sd_tx_correct_disp, + txdata => sd_tx_data_dst, + tx_k => sd_tx_kcntl_dst, + tx_disp_correct => sd_tx_correct_disp_dst, xmit => xmit, -- not used, should not harm -- RX channel - rxdata => sd_rx_data, - rx_k => sd_rx_kcntl, + rxdata => sd_rx_data_src, + rx_k => sd_rx_kcntl_src, rx_disp_err => sd_rx_disp_error, rx_cv_err => sd_rx_cv_error, lsm_status_s => lsm_status, @@ -331,13 +342,13 @@ begin tx_pclk => open, -- not really needed rx_pclk => sd_rx_clk, -- recovered RX clock, also used on FIFO! -- TX channel - txdata => sd_tx_data, - tx_k => sd_tx_kcntl, - tx_disp_correct => sd_tx_correct_disp, + txdata => sd_tx_data_dst, + tx_k => sd_tx_kcntl_dst, + tx_disp_correct => sd_tx_correct_disp_dst, xmit => xmit, -- not used, should not harm -- RX channel - rxdata => sd_rx_data, - rx_k => sd_rx_kcntl, + rxdata => sd_rx_data_src, + rx_k => sd_rx_kcntl_src, rx_disp_err => sd_rx_disp_error, rx_cv_err => sd_rx_cv_error, lsm_status_s => lsm_status, @@ -377,17 +388,17 @@ begin tx_pclk => open, -- not really needed rx_pclk => sd_rx_clk, -- recovered RX clock, also used on FIFO! -- TX channel - txdata => sd_tx_data, - tx_k => sd_tx_kcntl, - tx_disp_correct => sd_tx_correct_disp, + txdata => sd_tx_data_dst, + tx_k => sd_tx_kcntl_dst, + tx_disp_correct => sd_tx_correct_disp_dst, xmit => xmit, -- not used, should not harm -- RX channel - rxdata => sd_rx_data, - rx_k => sd_rx_kcntl, + rxdata => sd_rx_data_src, + rx_k => sd_rx_kcntl_src, rx_disp_err => sd_rx_disp_error, rx_cv_err => sd_rx_cv_error, lsm_status_s => lsm_status, - signal_detect_c => '1', -- enable internal LSM6500933585 + signal_detect_c => '1', -- enable internal LSM -- Status signals pll_lol => pll_lol, rx_cdr_lol_s => rx_cdr_lol, @@ -423,13 +434,13 @@ begin tx_pclk => open, -- not really needed rx_pclk => sd_rx_clk, -- recovered RX clock, also used on FIFO! -- TX channel - txdata => sd_tx_data, - tx_k => sd_tx_kcntl, - tx_disp_correct => sd_tx_correct_disp, + txdata => sd_tx_data_dst, + tx_k => sd_tx_kcntl_dst, + tx_disp_correct => sd_tx_correct_disp_dst, xmit => xmit, -- not used, should not harm -- RX channel - rxdata => sd_rx_data, - rx_k => sd_rx_kcntl, + rxdata => sd_rx_data_src, + rx_k => sd_rx_kcntl_src, rx_disp_err => sd_rx_disp_error, rx_cv_err => sd_rx_cv_error, lsm_status_s => lsm_status, @@ -501,15 +512,15 @@ begin ); -- -- "Good" debugging pins - debug(7 downto 0) <= sd_tx_data; - debug(15 downto 8) <= sd_rx_data; - debug(16) <= sd_tx_kcntl(0); - debug(17) <= sd_rx_kcntl(0); - debug(18) <= sd_tx_correct_disp(0); - debug(19) <= sd_rx_disp_error(0); + debug(7 downto 0) <= sd_tx_data_src; + debug(15 downto 8) <= sd_tx_data_dst; + debug(16) <= sd_tx_kcntl_src(0); + debug(17) <= sd_tx_kcntl_dst(0); + debug(18) <= sd_tx_correct_disp_src(0); + debug(19) <= sd_tx_correct_disp_dst(0); -- "Bad" debugging pins - debug(20) <= pcs_tx_en; - debug(21) <= pcs_rx_en; + debug(20) <= DLM_INJECT_IN; + debug(21) <= '0'; debug(22) <= '0'; debug(23) <= '0'; debug(24) <= '0'; @@ -523,6 +534,44 @@ begin debug(32) <= sd_rx_clk; debug(33) <= CLK_125; + ------------------------------------------------------------ + --- Trudy and Eve ------------------------------------------ + ------------------------------------------------------------ + THE_TRUDY: entity inserter + port map( + CLK => CLK_125, + RESET => CLEAR, + -- PHY output + PHY_D_IN => sd_tx_data_src, + PHY_K_IN => sd_tx_kcntl_src(0), + PHY_CD_IN => sd_tx_correct_disp_src(0), + -- SerDes input + TX_D_OUT => sd_tx_data_dst, + TX_K_OUT => sd_tx_kcntl_dst(0), + TX_CD_OUT => sd_tx_correct_disp_dst(0), + -- DLM stuff + DLM_DATA_IN => DLM_DATA_IN, + DLM_INJECT_IN => DLM_INJECT_IN + ); + + THE_EVE: entity remover + port map( + CLK => sd_rx_clk, + RESET => CLEAR, + -- SerDes output + RX_D_IN => sd_rx_data_src, + RX_K_IN => sd_rx_kcntl_src(0), + -- PHY input + PHY_D_OUT => sd_rx_data_dst, + PHY_K_OUT => sd_rx_kcntl_dst(0), + -- DLM stuff + DLM_DATA_OUT => DLM_DATA_OUT, + DLM_FOUND_OUT => DLM_FOUND_OUT + ); + ------------------------------------------------------------ + ------------------------------------------------------------ + ------------------------------------------------------------ + -- SGMII core SGMII_GBE_PCS : sgmii_gbe_core port map( @@ -555,13 +604,13 @@ begin col => open, crs => open, -- SerDes interface - tx_data => sd_tx_data, -- TX data to SerDes - tx_kcntl => sd_tx_kcntl(0), -- TX komma control to SerDes - tx_disparity_cntl => sd_tx_correct_disp(0), -- idle parity state control in IPG (to SerDes) + tx_data => sd_tx_data_src, -- TX data to SerDes + tx_kcntl => sd_tx_kcntl_src(0), -- TX komma control to SerDes + tx_disparity_cntl => sd_tx_correct_disp_src(0), -- idle parity state control in IPG (to SerDes) xmit_autoneg => xmit(0), serdes_recovered_clk => sd_rx_clk, -- 125MHz recovered from receive bit stream - rx_data => sd_rx_data, -- RX data from SerDes - rx_kcntl => sd_rx_kcntl(0), -- RX komma control from SerDes + rx_data => sd_rx_data_dst, -- RX data from SerDes + rx_kcntl => sd_rx_kcntl_dst(0), -- RX komma control from SerDes rx_err_decode_mode => '0', -- receive error control mode fixed to normal rx_even => '0', -- unused (receive error control mode = normal, tie to GND) rx_disp_err => sd_rx_disp_error(0), -- RX disparity error from SerDes