From: Jan Michel <j.michel@gsi.de>
Date: Tue, 24 Jan 2017 17:12:37 +0000 (+0100)
Subject: Update dirich with minor changes
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=a3397424c2522f94d44bb3f71c978f28e7229660;p=dirich.git

Update dirich with minor changes
---

diff --git a/code/clock_reset_handler.vhd b/code/clock_reset_handler.vhd
index 642e7e5..6f4d296 100644
--- a/code/clock_reset_handler.vhd
+++ b/code/clock_reset_handler.vhd
@@ -34,9 +34,10 @@ attribute syn_keep     : boolean;
 attribute syn_preserve : boolean;
 signal clock_100, clock_120, clock_200, clock_240, clock_200_raw: std_logic;
 signal sys_clk_i : std_logic;
-signal timer   : unsigned(16 downto 0) := (others => '0');
+signal timer   : unsigned(24 downto 0) := (others => '0');
 signal clear_n_i : std_logic := '0';
 signal reset_i   : std_logic;
+signal debug_reset_handler : std_logic_vector(15 downto 0);
 
 signal pll_lock : std_logic;
 
@@ -71,13 +72,14 @@ gen_fast_clock : if USE_120_MHZ = 1 generate
 end generate;
 
 
-clear_n_i <= timer(16) when rising_edge(CLOCK_IN);
+clear_n_i <= timer(24) when rising_edge(CLOCK_IN);
 
 process begin
   wait until rising_edge(sys_clk_i);
-  if timer(16) = '1' then
+
+  if timer(24) = '1' then
     timer <= timer;
-  else
+  elsif pll_lock = '1' then
     timer <= timer + 1;
   end if;
 end process;
@@ -100,7 +102,7 @@ THE_RESET_HANDLER : trb_net_reset_handler
     TRB_RESET_IN    => RESET_FROM_NET,  -- TRBnet reset signal (SYSCLK)
     CLEAR_OUT       => CLEAR_OUT,       -- async reset out, USE WITH CARE!
     RESET_OUT       => reset_i,         -- synchronous reset out (SYSCLK)
-    DEBUG_OUT       => open
+    DEBUG_OUT       => debug_reset_handler
   );  
 
 RESET_OUT <= reset_i;
@@ -111,7 +113,8 @@ RESET_OUT <= reset_i;
 ---------------------------------------------------------------------------  
 DEBUG_OUT(0)  <= pll_lock;
 DEBUG_OUT(1)  <= clear_n_i;
-DEBUG_OUT(31 downto 2) <= (others => '0');
+DEBUG_OUT(15 downto 2) <= debug_reset_handler(15 downto 2);
+DEBUG_OUT(31 downto 16) <= (others => '0');
 
 BUS_TX.data <= (others => '0');
 BUS_TX.unknown <= '1';
diff --git a/dirich/diamond/dirich.ldf b/dirich/diamond/dirich.ldf
index 087c214..f98bc48 100644
--- a/dirich/diamond/dirich.ldf
+++ b/dirich/diamond/dirich.ldf
@@ -315,9 +315,6 @@
         <Source name="../../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../../trbnet/media_interfaces/ecp5/serdes_sync_0/serdes_sync_0.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
         <Source name="../tdc_release/TDC_record.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
@@ -384,10 +381,10 @@
         <Source name="../../../trbnet/optical_link/f_divider.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../../trbnet/media_interfaces/ecp5/serdes_sync_0/serdes_sync_0.sbx" type="sbx" type_short="SBX">
+        <Source name="pcs/pcs.sbx" type="sbx" type_short="SBX">
             <Options/>
         </Source>
-        <Source name="pcs/pcs.sbx" type="sbx" type_short="SBX">
+        <Source name="../../../trbnet/lattice/ecp5/FIFO/fifo_18x8k_oreg/fifo_18x8k_oreg.sbx" type="sbx" type_short="SBX">
             <Options/>
         </Source>
         <Source name="../workdir/dirich.lpf" type="Logic Preference" type_short="LPF">
diff --git a/dirich/diamond/dirich1.sty b/dirich/diamond/dirich1.sty
index 3b90160..02f8941 100644
--- a/dirich/diamond/dirich1.sty
+++ b/dirich/diamond/dirich1.sty
@@ -1,6 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <!DOCTYPE strategy>
 <Strategy version="1.0" predefined="0" description="" label="Strategy1">
+    <Property name="PROP_BD_CmdLineArgs" value="" time="0"/>
     <Property name="PROP_BD_EdfHardtimer" value="Enable" time="0"/>
     <Property name="PROP_BD_EdfInBusNameConv" value="None" time="0"/>
     <Property name="PROP_BD_EdfInLibPath" value="" time="0"/>
diff --git a/dirich/dirich.vhd b/dirich/dirich.vhd
index 06fe157..29151c5 100644
--- a/dirich/dirich.vhd
+++ b/dirich/dirich.vhd
@@ -440,19 +440,6 @@ begin
   end generate;
 
 
---   gen_chains : for i in 0 to 15 generate
---     process begin
---       wait until rising_edge(CLOCK_IN);
---       c(i)(4000 downto 1) <= c(i)(3999 downto 0);
---       c(i)(0) <= not c(i)(0) or INPUT(i+1);
---       PWM(i+1) <= c(i)(4000);
---       if reset_i = '1' then
---         c(i)(4000 downto 0) <= (others => '0');
---       end if;
---     end process;
---   
---   end generate;
-
 end architecture;
 
 
diff --git a/dirich/nodelist_frankfurt.txt b/dirich/nodelist_frankfurt.txt
new file mode 100644
index 0000000..6059303
--- /dev/null
+++ b/dirich/nodelist_frankfurt.txt
@@ -0,0 +1,13 @@
+// nodes file for parallel place&route
+
+[jspc29]
+SYSTEM = linux
+CORENUM = 3
+ENV = /d/jspc29/lattice/37_settings.sh
+WORKDIR = /d/jspc22/trb/git/dirich/dirich/workdir
+
+[jspc57]
+SYSTEM = linux
+CORENUM = 7
+ENV = /d/jspc29/lattice/37_settings.sh
+WORKDIR = /d/jspc22/trb/git/dirich/dirich/workdir