From: hadeshyp Date: Wed, 15 Jul 2009 14:57:05 +0000 (+0000) Subject: attilio: added test_data one can swith between two data type with c0 reg X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=a4d3657ee9f2bbfcf8b217e485c3b9cea19cde51;p=mdcoep.git attilio: added test_data one can swith between two data type with c0 reg --- diff --git a/design/tdc_readout.vhd b/design/tdc_readout.vhd index 9f019cc..d9e2469 100644 --- a/design/tdc_readout.vhd +++ b/design/tdc_readout.vhd @@ -24,11 +24,7 @@ entity tdc_readout is RESET : in std_logic; A_ADD_IN : in std_logic_vector(8 downto 0); --address/data line --- A_ADS_0 : in std_logic; --Motherboard address --- A_ADS_1 : in std_logic; --Motherboard address --- A_ADS_2 : in std_logic; --Motherboard address A_AOD_IN : in std_logic; --address or data --- A_ACK_IN : in std_logic; --acknowledgment A_DST_IN : in std_logic; --data strobe A_RESERV_IN : in std_logic; @@ -40,8 +36,9 @@ entity tdc_readout is DATA_VALID_OUT : out std_logic; FULL_FIFO_IN : in std_logic; INIT_TDC_READOUT_IN : in std_logic_vector(3 downto 0); --from common stop generator - DATA_TYPE_SELECT_IN : in std_logic_vector(3 downto 0); --x"0"debug, - --x"1" 2 hit in one word + +--x"0"debug, x"1" 2 hit in one word, x"2" test data, + DATA_TYPE_SELECT_IN : in std_logic_vector(3 downto 0); DEBUG_REGISTER_OUT : out std_logic_vector(3 downto 0)); end tdc_readout; @@ -116,6 +113,21 @@ signal clear_counter_check_hit_calibration,up_counter_check_hit_calibration : ST signal counter_check_hit_calibration : std_logic_vector(3 downto 0); signal clear_saved_data_new_format_hit_0_1_cal : std_logic; +--test data +type state_type_test_data is (idle_state_test_data, send_data_with_valid_test_data, + send_data_with_valid_next_test_data, + send_data_with_valid_next_test_data, + check_dataword_number_test_data, + send_token_state_test_data); + +signal current_state_test_data, next_state_test_data : state_type_test_data; +signal reg_debug_register_test_data, next_debug_register_test_data : std_logic_vector(3 downto 0); +signal reg_data_bus_out_test_data, next_data_bus_out_test_data : std_logic_vector(35 downto 0); +signal reg_data_valid_out_test_data, next_data_valid_out_test_data : std_logic; +signal up_counter_test_data, clear_counter_test_data : std_logic; +signal reg_token_tdc_readout_i_test_data, next_token_tdc_readout_i_test_data : std_logic_vector(3 downto 0); +signal counter_test_data : std_logic_vector(15 downto 0); + begin -- behavioral ------------------------------------------------------------------------------- @@ -143,7 +155,7 @@ begin -- behavioral ------------------------------------------------------------------------------ -- purpose: state machine. get TDC data and build a std_logic_vector -------------------------------------------------------------------------------- +------------------------------------------------------------------------------ process(current_state, TOKEN_IN, INIT_TDC_READOUT_IN, A_DST_IN, A_AOD_IN, FULL_FIFO_IN) @@ -256,52 +268,6 @@ begin -- behavioral next_debug_register <= "1001"; next_token_tdc_readout_i <= x"1"; next_state <= idle_state; -------------------------------------------------------------------------------- --- token + NO data => => => => OK -------------------------------------------------------------------------------- --- when send_token_state_2 => --- next_debug_register <= "1011"; --- next_token_tdc_readout_i <= x"3"; --- next_state <= idle_state; --- ------------------------------------------------------------------------------- --- -- NO token + NO data --- ------------------------------------------------------------------------------- --- when send_token_state_3 => --- next_debug_register <= "1100"; --- next_token_tdc_readout_i <= x"4"; --- next_state <= idle_state; --- ------------------------------------------------------------------------------- --- -- NO token + data --- ------------------------------------------------------------------------------- --- when send_token_state_4 => --- next_debug_register <= "1100"; --- next_token_tdc_readout_i <= x"5"; --- next_state <= idle_state; - - --- when send_data_no_valid => --- next_debug_register <= "1000"; --- next_a_dre <= '1'; --- next_data_valid_out <= '0'; --connected to WRITE_FIFO --- if A_AOD_IN = '1' and TOKEN_IN = '0' then --- next_state <= save_L_word_state; --- elsif A_AOD_IN = '0' and TOKEN_IN = '1' then --- next_state <= idle_state; --- elsif STOP_READOUT_IN = '1' then --means token not back --- next_state <= idle_state; --- else --- next_state <= send_data_no_valid; --- end if; - --- when fifo_full_state => --- next_debug_register <= "1100"; --- next_data_valid_out <= '0'; --- --I stay here if there is no space in the fifo --- if FULL_FIFO_IN = '1' then --cannot write anymore in fifo --- next_state <= fifo_full_state; --- else --- next_state <= idle_state; --- end if; when others => next_state <= idle_state; @@ -372,29 +338,35 @@ begin -- behavioral ------------------------------------------------------------------------------- -- DATA SELECT MULTIPLEXER ------------------------------------------------------------------------------- --- process (CLK, reg_data_type_select_in) --- begin --- if (rising_edge(CLK)) then --- if (reg_data_type_select_in = x"0") then --debug mode + process (CLK, reg_data_type_select_in) + begin + if (rising_edge(CLK)) then + if (reg_data_type_select_in = x"0") then --debug mode DATA_VALID_OUT <= reg_data_valid_out; DATA_BUS_OUT <= saved_data; TOKEN_TDC_READOUT_OUT <= reg_token_tdc_readout_i; DEBUG_REGISTER_OUT <= reg_debug_register; --- elsif (reg_data_type_select_in = x"1") then --2hit in one dw --- DATA_VALID_OUT <= reg_data_valid_out_new_format; --- DATA_BUS_OUT <= saved_data_new_format; --- TOKEN_TDC_READOUT_OUT <= reg_token_tdc_readout_i_new_format; --- DEBUG_REGISTER_OUT <= reg_debug_register_new_format; - --- else --debug mode --- DATA_VALID_OUT <= reg_data_valid_out; --- DATA_BUS_OUT <= saved_data; --- TOKEN_TDC_READOUT_OUT <= reg_token_tdc_readout_i; --- DEBUG_REGISTER_OUT <= reg_debug_register; --- end if; --- end if; --- end process; + elsif (reg_data_type_select_in = x"1") then --2hit in one dw + DATA_VALID_OUT <= reg_data_valid_out_new_format; + DATA_BUS_OUT <= saved_data_new_format; + TOKEN_TDC_READOUT_OUT <= reg_token_tdc_readout_i_new_format; + DEBUG_REGISTER_OUT <= reg_debug_register_new_format; + + elsif (reg_data_type_select_in = x"2") then -- test data + DATA_VALID_OUT <= reg_data_valid_out_test_data; + DATA_BUS_OUT <= reg_data_bus_out_test_data; + TOKEN_TDC_READOUT_OUT <= reg_token_tdc_readout_i_test_data; + DEBUG_REGISTER_OUT <= reg_debug_register_test_data; + + else --debug mode + DATA_VALID_OUT <= reg_data_valid_out; + DATA_BUS_OUT <= saved_data; + TOKEN_TDC_READOUT_OUT <= reg_token_tdc_readout_i; + DEBUG_REGISTER_OUT <= reg_debug_register; + end if; + end if; + end process; ------------------------------------------------------------------------------- -- @@ -1060,6 +1032,106 @@ begin -- behavioral -- 2 HITS IN ONE DATAWORD STRUCTURE : END ------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- TEST DATA: START +------------------------------------------------------------------------------- + process (CLK) + begin + if rising_edge(CLK) then + if (RESET = '1') then + current_state_test_data <= idle_state_test_data; + reg_data_bus_out_test_data <= (others => '0'); + reg_data_valid_out_test_data <= '0'; + reg_token_tdc_readout_i_test_data <= (others => '0'); + reg_debug_register_test_data <= (others => '0'); + else + current_state_test_data <= next_state_test_data; + reg_debug_register_test_data <= next_debug_register_test_data; + reg_data_bus_out_test_data <= next_data_bus_out_test_data; + reg_data_valid_out_test_data <= next_data_valid_out_test_data; + reg_token_tdc_readout_i_test_data <= next_token_tdc_readout_i_test_data; + end if; + end if; + end process ; + +----------------------------------------------------------------------------- +-- purpose: built test data and send to fifo +------------------------------------------------------------------------------- + process(current_state_test_data, INIT_TDC_READOUT_IN, counter_test_data) + + begin + + next_data_valid_out_test_data <= '0'; + next_debug_register_test_data <= (others => '0'); + next_token_tdc_readout_i_test_data <= (others => '0'); +--send constant pattern + next_data_bus_out_test_data(35 downto 32) <= x"1"; + next_data_bus_out_test_data(31 downto 0) <= x"babecafe"; + + up_counter_test_data <= '0'; + clear_counter_test_data <= '0'; + + case current_state_test_data is + + when idle_state_test_data => + next_debug_register_test_data <= x"0"; + if (INIT_TDC_READOUT_IN = x"1") then + next_state_test_data <= send_data_with_valid_test_data; + else + next_state_test_data <= idle_state_test_data; + end if; + + when send_data_with_valid_test_data => + next_debug_register_test_data <= x"1"; + up_counter_test_data <= '1'; + next_data_valid_out_test_data <= '1'; + next_state_test_data <= send_data_with_valid_next_test_data; + + + when send_data_with_valid_next_test_data => + next_debug_register_test_data <= x"2"; + next_data_valid_out_test_data <= '0'; + next_state_test_data <= check_dataword_number_test_data; + + when check_dataword_number_test_data => + next_debug_register_test_data <= x"3"; + next_data_valid_out_test_data <= '0'; + if (conv_integer(counter_test_data) >= 10) then + next_state_test_data <= send_token_state_test_data; + else + next_state_test_data <= send_data_with_valid_test_data; + end if; + +-- send token here it is simulated after a constant number of dataword + when send_token_state_test_data => + next_debug_register_test_data <= x"4"; + next_token_tdc_readout_i_test_data <= x"1"; + clear_counter_test_data <= '1'; + next_state_test_data <= idle_state_test_data; + + when others => + next_state_test_data <= idle_state_test_data; + + end case; + end process; + + --counter dataword number to send to fifo + process (CLK, RESET, up_counter_test_data, clear_counter_test_data) + begin + if (rising_edge(CLK)) then + if (RESET = '1' or clear_counter_test_data = '1') then + counter_test_data <= (others => '0'); + elsif (up_counter_test_data = '1') then + counter_test_data <= counter_test_data + 1; + else + counter_test_data <= counter_test_data; + end if; + end if; + end process; +------------------------------------------------------------------------------- +-- TEST DATA: END +------------------------------------------------------------------------------- end behavioral; diff --git a/design/tdc_readout_and_trb_interface.vhd b/design/tdc_readout_and_trb_interface.vhd index 9f4a04e..2afeb8c 100644 --- a/design/tdc_readout_and_trb_interface.vhd +++ b/design/tdc_readout_and_trb_interface.vhd @@ -7,7 +7,9 @@ -- --This code has not optimized yet. --13/02/2009 I start adapting following TRBNET standards - +-- +-- the token signal comes from send_token entity, it goes to tdc_readout +-- ------------------------------------------------------------------------------- library IEEE; @@ -20,15 +22,6 @@ library ecp2m; use ecp2m.components.all; -- synopsys translate_on ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. -------------------------------------------------------------------------------- ---fifo_0 contain maximum 600 dataword. MB sends 1 dataword in 100ns, so I wait ---the token for maximum 1usec (safety time => at the moment) -------------------------------------------------------------------------------- --- library UNISIM; --- use UNISIM.VComponents.all; - entity tdc_readout_and_trb_interface is -- generic (width : integer := 16; -- bus_number: std_logic_vector(3 downto 0)); @@ -44,7 +37,6 @@ entity tdc_readout_and_trb_interface is A_AOD : in std_logic; --address or data A_ACK : in std_logic; A_DST : in std_logic; - -- A_RDO : in std_logic; A_DRE : out std_logic; TOKEN_IN : in std_logic_vector(3 downto 0); INIT_TDC_READOUT_IN : in std_logic_vector(3 downto 0); @@ -53,30 +45,18 @@ entity tdc_readout_and_trb_interface is -- tdc_readout_and_trb_interface ------------------------------------------------------------------------------- DATA_TYPE_SELECT_IN : in std_logic_vector(3 downto 0); - -- INIT_TRB_INTERFACE_IN : in std_logic; TOKEN_TO_TRB_OUT : out std_logic; REINIT_ROC1_IN : in std_logic; REINIT_ROC1_OUT : out std_logic; SUCCESFUL_REINIT_ROC1 : in std_logic; STOP_READOUT_IN : in std_logic; - -- DATA_BUS_TO_TRB_OUT : out std_logic_vector(25 downto 0);--(18 downto 0); - -- DATA_VALID_TO_TRB_OUT : out std_logic; DEBUG_REGISTER_0 : out std_logic_vector(7 downto 0); DEBUG_REGISTER_1 : out std_logic_vector(7 downto 0); DEBUG_REGISTER_2 : out std_logic_vector(7 downto 0); - -------------------------------------------------------------------------------- --- CONNECTION TO TRBNET END POINT INTERFACE + ------------------------------------------------------------------------------- --- ACKNOWLEDGE_TRB_INTERFACE_IN : in std_logic_vector(3 downto 0); --- INIT_TRB_INTERFACE_OUT : out std_logic; --- DATA_OUT : out std_logic_vector(25 downto 0);--(18 downto 0); --- READ_FIFO_IN : in std_logic; --- DEBUG_REGISTER_TRB_INTERFACE : in std_logic_vector(3 downto 0); --- ------------------------------------------------------------------------------- --- - +-- trbnet interface ------------------------------------------------------------------------------- - -- LVL1 trigger APL LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); LVL1_TRG_RECEIVED_IN : in std_logic; LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); @@ -128,20 +108,15 @@ architecture behavioral of tdc_readout_and_trb_interface is signal current_state_fsm_multiplexer, next_state_fsm_multiplexer : state_type_fsm_multiplexer; - signal buffer_write_enable_i, reg_buffer_write_enable_i : std_logic; - -- signal reg_buffer_read_enable_i, next_buffer_read_enable_i : std_logic; - signal buffer_data_in_i, reg_buffer_data_in_i , buffer_data_in_i_32: std_logic_vector(31 downto 0); - - signal buffer_data_out_i : std_logic_vector(31 downto 0); - signal reg_fifo_data_in_i, next_fifo_data_in_i, fifo_data_in_i : std_logic_vector(31 downto 0); signal reg_fifo_data_out_i, fifo_data_out_i : std_logic_vector(31 downto 0); signal reg_fifo_write_enable_i, next_fifo_write_enable_i : std_logic; --- signal reg_fifo_read_enable_i, fifo_read_enable_i : std_logic; signal reg_lvl1_busy_i, next_lvl1_busy_i : std_logic; signal init_tdc_readout_i : std_logic_vector(3 downto 0); signal reg_debug_register_i, next_debug_register_i : std_logic_vector(7 downto 0); + signal words_in_event_test_data : std_logic_vector(15 downto 0):=(others => '0'); + signal words_in_event_first_header : std_logic_vector(15 downto 0):=(others => '0'); signal words_in_event : std_logic_vector(15 downto 0):=(others => '0'); signal lvl1_data_counter : std_logic_vector(15 downto 0):=(others => '0'); signal pulse_a_aod_i : std_logic; @@ -150,8 +125,6 @@ architecture behavioral of tdc_readout_and_trb_interface is signal token_tdc_readout_i : std_logic_vector(3 downto 0); signal first_header : std_logic_vector(51 downto 0); signal reg_first_header : std_logic_vector(51 downto 0); - --signal second_header : std_logic_vector(35 downto 0):=(others => '0'); - signal reg_token_in : std_logic_vector(3 downto 0); signal data_tdc_readout_i : std_logic_vector(35 downto 0); signal write_fee_data_fifo_i : std_logic; signal reg_LVL1_TRG_TYPE_IN : std_logic_vector(3 downto 0); @@ -179,18 +152,13 @@ architecture behavioral of tdc_readout_and_trb_interface is signal reg_lvl1_trg_information, reg_ipu_information : std_logic_vector(7 downto 0); signal reg_ipu_number : std_logic_vector (15 downto 0); - --signal reg_error_pattern : std_logic_vector (31 downto 0); signal reg_lvl1_error_pattern, next_lvl1_error_pattern : std_logic_vector (31 downto 0); signal reg_lvl1_trg_release, next_lvl1_trg_release : std_logic; signal reg_ipu_data, next_ipu_data : std_logic_vector (31 downto 0); signal reg_ipu_data_ready, next_ipu_data_ready : std_logic; signal reg_ipu_finished, next_ipu_finished : std_logic; - --signal reg_ipu_length, next_ipu_length : std_logic_vector (15 downto 0); signal how_many_complete_event_in_fifo_counter : std_logic_vector (31 downto 0); signal pulse_reg_lvl1_trg_received : std_logic; - -- signal reg_ipu_read : std_logic; --- signal reg_lvl1_trg_type : std_logic_vector(3 downto 0); --- signal reg_lvl1_trg_received : std_logic; signal reg_lvl1_trg_number : std_logic_vector(15 downto 0); signal read_header_fifo,read_fee_data_fifo : std_logic; signal counter_word_read_from_trbnet : std_logic_vector(3 downto 0); @@ -205,9 +173,6 @@ architecture behavioral of tdc_readout_and_trb_interface is signal counter_token_back : std_logic_vector(31 downto 0); signal full_flag_fee_data_fifo_i,almost_empty_flag_fee_data_fifo_i,almost_full_flag_fee_data_fifo_i : std_logic; signal full_flag_header_data_fifo_i,almost_empty_flag_header_data_fifo_i,almost_full_flag_header_data_fifo_i : std_logic; --- signal reg_lvl1_trg_code,reg_lvl1_trg_information : std_logic_vector(7 downto 0); --- signal reg_ipu_number : std_logic_vector (15 downto 0); --- signal reg_ipu_information : std_logic_vector (7 downto 0); signal reg_ipu_start_readout_in : std_logic; signal push_read_fee_data_1_i : std_logic; @@ -355,10 +320,9 @@ TDC_READOUT_INTERFACE : tdc_readout A_ADD_IN => A_ADD, A_RESERV_IN => A_RESERV, A_AOD_IN => A_AOD, - -- A_ACK_IN => A_ACK, A_DST_IN => A_DST, - TOKEN_IN => reg_token_in, --here from tld + TOKEN_IN => TOKEN_IN, --here from tld TOKEN_TDC_READOUT_OUT => token_tdc_readout_i, FLAG_EVENT_COUNTER_IN => flag_event_counter, @@ -370,21 +334,13 @@ TDC_READOUT_INTERFACE : tdc_readout FULL_FIFO_IN => '0', DATA_TYPE_SELECT_IN => DATA_TYPE_SELECT_IN, DEBUG_REGISTER_OUT => debug_register_tdc_readout_i); + ------------------------------------------------------------------------------- -- OENP point test token back ------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --- => => . DEVI DIDERE COME FARE LA CONNESSIONE DEL TOKEN TRA ENETITY <= <= -------------------------------------------------------------------------------- - --TOKEN_TO_TRB_OUT <= reg_token_in(0); - TOKEN_TO_TRB_OUT <= reg_pseudo_token; - --- TOKEN_TO_TRB_OUT <= '1' when (token_tdc_readout_i = x"1" or --- token_tdc_readout_i = x"2" or --- token_tdc_readout_i = x"3" or --- token_tdc_readout_i = x"4" or --- token_tdc_readout_i = x"5") else '0'; -------------------------------------------------------------------------------- +--data transmission to trbnet terminated + TOKEN_TO_TRB_OUT <= reg_pseudo_token; + FEE_DATA_FIFO : fifo_8192depth_36width_dual_thresh_reg_out port map ( Data => data_tdc_readout_i, @@ -416,10 +372,10 @@ TDC_READOUT_INTERFACE : tdc_readout end if; end process; - process(CLK, pulse_not_empty_flag_fee_data_fifo_i, RESET, reg_token_in(0) ) + process(CLK, pulse_not_empty_flag_fee_data_fifo_i, RESET, token_tdc_readout_i(0) ) begin if rising_edge(CLK) then - if (RESET = '1' or reg_token_in(0) = '1') then + if (RESET = '1' or token_tdc_readout_i(0) = '1') then counter_pulse_not_empty <= (others => '0'); elsif (pulse_not_empty_flag_fee_data_fifo_i = '1') then counter_pulse_not_empty <= counter_pulse_not_empty + '1'; @@ -574,12 +530,9 @@ end process; IPU_LENGTH_OUT <= reg_first_header(51 downto 36); IPU_ERROR_PATTERN_OUT <= x"AAAAAAAA"; ---to connect ---reg_debug_register_fsm_header ------------------------------------------------------------------------------- + -- Count number of dataword per event -------------------------------------------------------------------------------- a_add_data_counter : process (CLK, pulse_init_tdc_readout, pulse_a_aod_i) begin if rising_edge(CLK) then @@ -593,28 +546,42 @@ end process; end if; end process a_add_data_counter; +-- Count number of dataword in case of test data + a_add_data_counter : process (CLK, pulse_init_tdc_readout, pulse_write_fee_data_fifo_i) + begin + if rising_edge(CLK) then + if (RESET = '1' or pulse_init_tdc_readout = '1') then --reset at every trigger + words_in_event_test_data <= (others => '0'); + elsif (pulse_write_fee_data_fifo_i = '1') then + words_in_event_test_data <= words_in_event_test_data + 1; + else + words_in_event_test_data <= words_in_event_test_data; + end if; + end if; + end process a_add_data_counter; + + --register input process (CLK, RESET) begin if rising_edge(CLK) then if RESET = '1' then - reg_token_in <= (others => '0'); reg_ipu_read <= '0'; else - reg_token_in <= TOKEN_IN; reg_ipu_read <= IPU_READ_IN; end if; end if; end process; --counter number of token back - process (CLK, RESET,reg_token_in) +--reset it when the event has been transferred to trbnet + process (CLK, RESET,token_tdc_readout_i, reg_pseudo_token) begin if rising_edge(CLK) then - if RESET = '1' then + if (RESET = '1' or reg_pseudo_token ='1') then counter_token_back <= (others => '0'); - elsif (reg_token_in(0) = '1') then + elsif (token_tdc_readout_i(0) = '1') then counter_token_back <= counter_token_back + 1; else counter_token_back <= counter_token_back; @@ -645,7 +612,7 @@ end process; -- COMBINATORIAL PART: BUILD HEADER AND WRITE THEM IN THE FIFO FOR HEADER, -- MANAGES THE BUSY SIGNAL ------------------------------------------------------------------------------- - process(current_state, reg_lvl1_trg_received, reg_token_in, + process(current_state, reg_lvl1_trg_received, token_tdc_readout_i, pulse_init_tdc_readout, INIT_TDC_READOUT_IN, almost_empty_flag_fee_data_fifo_i) begin @@ -679,9 +646,9 @@ end process; next_write_header_fifo_i <= '0'; data_header_fifo_in_i <= reg_first_header; next_lvl1_busy_i <= '1'; - if (reg_token_in(0) = '1' and almost_empty_flag_fee_data_fifo_i = '0') then + if (token_tdc_readout_i(0) = '1' and almost_empty_flag_fee_data_fifo_i = '0') then next_state <= send_second_header_state; - elsif (reg_token_in(0) = '1' and almost_empty_flag_fee_data_fifo_i = '1') then + elsif (token_tdc_readout_i(0) = '1' and almost_empty_flag_fee_data_fifo_i = '1') then next_state <= busy_header_state; else next_state <= wait_for_token; @@ -815,6 +782,7 @@ end process; next_ipu_data_ready <= '0'; next_data_to_trb_net <= header_data_fifo_out_i(31 downto 0); --here I wait only when the first token from the first event is back +--in fiture I need to see there is one event at least in the header fifo if (conv_integer(counter_token_back) >= 1) then -- push_read_header_data_i <= '1'; next_state_fsm_multiplexer <= dummy_wait_4_fsm_multiplexer; @@ -978,13 +946,20 @@ end process; ------------------------------------------------------------------------------- -- Make headers 36 bit ------------------------------------------------------------------------------- -first_header <= words_in_event & --(15 downto 0) +first_header <= words_in_event_first_header & --(15 downto 0) flag_event_counter & --(3 downto 0) "0000" & --(3 downto 0) reg_lvl1_trg_type & --(3 downto 0) reg_lvl1_trg_information & --(7 downto 0) reg_lvl1_trg_number; --(15 downto 0) - process (CLK) + + +--number of dataword are counter in differet way if test data is enabled +words_in_event_first_header <= words_in_event_test_data when (DATA_TYPE_SELECT_IN = x"2") + else words_in_event; + +--register header +process (CLK) begin if rising_edge(CLK) then if RESET = '1' then @@ -995,24 +970,19 @@ first_header <= words_in_event & --(15 downto 0) end if; end process; ---second_header <= flag_event_counter & x"babe" & words_in_event; - ---DEBUG_REGISTER_0 <= received_token_number & sended_token_number; -DEBUG_REGISTER_0 <= x"0" & reg_debug_register_fsm_multiplexer(3 downto 0); ---DEBUG_REGISTER_1 <= reg_debug_register_i;--debug tdc_readout_and_trb_interface ---DEBUG_REGISTER_2 <= "0000" & debug_register_tdc_readout_i; +DEBUG_REGISTER_0 <= x"0" & reg_debug_register_fsm_multiplexer(3 downto 0); ------------------------------------------------------------------------------- -- EVENT COMPLETE in FIFO: -- the counter is used to check how many event complete are stored in the fifo. ----------------------------------------------------------------------------- -process(CLK, RESET, pulse_init_tdc_readout, reg_token_in) +process(CLK, RESET, pulse_init_tdc_readout, token_tdc_readout_i) begin if (rising_edge(CLK)) then if (RESET = '1') then how_many_complete_event_in_fifo_counter <= (others => '0'); - elsif (( not(pulse_init_tdc_readout) and reg_token_in(0)) = '1') then + elsif (( not(pulse_init_tdc_readout) and token_tdc_readout_i(0)) = '1') then how_many_complete_event_in_fifo_counter <= how_many_complete_event_in_fifo_counter + 1; --decrese by one every event is read out -- elsif then diff --git a/design/trigger_distributor.vhd b/design/trigger_distributor.vhd index df9e02b..4d19a37 100644 --- a/design/trigger_distributor.vhd +++ b/design/trigger_distributor.vhd @@ -195,7 +195,7 @@ begin -- behavioral next_LED_CNT_1_OUT <= '1'; next_LED_CNT_2_OUT <= '1'; next_LED_ERROR_OUT <= '1'; - next_LED_GOOD_OUT <= '1'; + next_LED_GOOD_OUT <= '0'; next_init_all_buses <= (others => '0'); next_token_to_trb <= '0'; up_number_of_trigger <= '0'; diff --git a/mdc_oepb.vhd b/mdc_oepb.vhd index 5b5af5a..ae9f29f 100644 --- a/mdc_oepb.vhd +++ b/mdc_oepb.vhd @@ -32,20 +32,20 @@ entity mdc_oepb is ADC_SDO : in std_logic; ADC_CONVST : out std_logic; --MB - --MRES : out std_logic; --global reset + --MRES : out std_logic; --global reset TAOD : inout std_logic; --address or data TACK : in std_logic; --MB address CMS : out std_logic; --common stop TDST : inout std_logic; --data strobe - GDE : out std_logic; --global disable - RDYI : out std_logic; --ready TO first motherboard token out to MB (on AddOn RDM) - TRDYO : in std_logic; --ready FROM first motherboard token in (respect OEP old RDO) - TRSV : in std_logic; --this is 11 bit of dataword (on AddOn A_RESERV) + GDE : out std_logic; --global disable + RDYI : out std_logic; --ready TO first motherboard token out to MB (on AddOn RDM) + TRDYO : in std_logic; --ready FROM first motherboard token in (respect OEP old RDO) + TRSV : in std_logic; --this is 11 bit of dataword (on AddOn A_RESERV) --mode lines MODD : out std_logic; -- TDC working mode RES : out std_logic; -- TDC working mode TOK : out std_logic; -- TDC working mode - WRM : out std_logic; -- TDC working mode + WRM : out std_logic; -- TDC working mode TAD : inout std_logic_vector(8 downto 0) --TAD 8 downto 0 ); end entity; @@ -155,8 +155,8 @@ architecture mdc_oepb_arch of mdc_oepb is signal direction_data_line_out_i : std_logic_vector(3 downto 0); signal motherboard_type_in_i : std_logic_vector(3 downto 0); signal pulse_begin_run_trigger_i : std_logic; - - + signal data_type_select_in_i : std_logic_vector(3 downto 0); + signal datbus_data_out : std_logic_vector(31 downto 0); signal datbus_addr_out : std_logic_vector(15 downto 0); @@ -168,6 +168,7 @@ architecture mdc_oepb_arch of mdc_oepb is signal reset_counter_led : std_logic; signal counter: std_logic_vector (3 downto 0); signal test_pseudo_signal_i : std_logic; + begin --------------------------------------------------------------------- @@ -214,8 +215,6 @@ begin CLK_FF <= '0'; DATA_FF <= '0'; - - --------------------------------------------------------------------- -- trbnet endpoint --------------------------------------------------------------------- @@ -545,74 +544,61 @@ THE_REGIO_BUS_HANDLER : trb_net16_regio_bus_handler ); --------------------------------------------------------------------- --- Transport trigger to FEE +-- Transport trigger to FEE and FEE definition --------------------------------------------------------------------- -- 0xc0 0x0011 -> send begrun trigger to 1 short -- 0xc0 0x0021 -> send begrun trigger to 1 long -- 0xc0 0x0C10 -> x"C" set calibration trigger, x"0" normal --- 0xc0 0x1000 -> send NORMAL trigger --- 0xc0 0x1C00 -> send CALIBRATION trigger +-- 0xc0 0x0000 -> select verbose mode data +-- 0xc0 0x1000 -> select compact mode data +-- 0xc0 0x2000 -> select test data PROC_GEN_TIMING : process(CLK_100) begin if rising_edge(CLK_100) then ---pulse for BEGRUN trigger - -- last_LVL1_TRG_RECEIVED_OUT <= REGIO_REGISTERS_OUT(0); - -- pulse_begin_run_trigger_i <= REGIO_REGISTERS_OUT(0) and not last_LVL1_TRG_RECEIVED_OUT; - ---FEE definition motherboard_type_in_i <= REGIO_REGISTERS_OUT(7 downto 4); cal_trigger_register_in_i <= x"000" & REGIO_REGISTERS_OUT(11 downto 8); - + data_type_select_in_i <= REGIO_REGISTERS_OUT(15 downto 12); end if; end process; -------------------------------------------------------------------------------- --- pulse for trigger (NORMAL/CAL) -------------------------------------------------------------------------------- - PULSE_TRIGGER : edge_to_pulse + PULSE_TRIGGER : edge_to_pulse port map ( CLOCK => CLK_100, ---to avoid to get a trigger while reading ENABLE_CLK_IN => '1', - SIGNAL_IN => REGIO_REGISTERS_OUT(12), + SIGNAL_IN => REGIO_COMMON_CTRL_REG_OUT(16), PULSE_OUT => pulse_pseudo_timing_trigger); - + PULSE_BEGRUN_TRIGGER : edge_to_pulse - port map ( - CLOCK => CLK_100, - ENABLE_CLK_IN => '1', - SIGNAL_IN => REGIO_REGISTERS_OUT(0), - PULSE_OUT => pulse_begin_run_trigger_i); + port map ( + CLOCK => CLK_100, + ENABLE_CLK_IN => '1', + SIGNAL_IN => REGIO_REGISTERS_OUT(0), + PULSE_OUT => pulse_begin_run_trigger_i); - test_pseudo_signal_i <= (pulse_pseudo_timing_trigger and LVL1_TRG_RELEASE_IN) - when (debug_trigger_distributor_i(3 downto 0) = x"1") else '0'; - - THE_TRIG_DISTR : trigger_distributor + THE_TRIG_DISTR : trigger_distributor port map ( CLK => CLK_100, RESET => reset_internal, INTERNAL_RESET_IN => pulse_begin_run_trigger_i, A_RDO_IN => token_to_mux_out_i, - TRIGGER_IN => test_pseudo_signal_i,--pulse_pseudo_timing_trigger, + TRIGGER_IN => pulse_pseudo_timing_trigger, TRIGGER_TYPE_IN => LVL1_TRG_TYPE_OUT, INIT_ALL_BUSES_OUT => init_all_buses_i, ROC1_WRITTEN_IN => roc1_written_i, TOKEN_TO_TRB_OUT => open,--LVL1_TRG_RELEASE_IN, CAL_TRIGGER_REGISTER_IN => cal_trigger_register_in_i, DEBUG_REGISTER_OUT => debug_trigger_distributor_i, - LED_CNT_1_OUT => open,--D(4), - LED_CNT_2_OUT => open,--D(3), - LED_ERROR_OUT => open,--D(2), - LED_GOOD_OUT => open--D(1) + LED_CNT_1_OUT => D(4), + LED_CNT_2_OUT => D(3), + LED_ERROR_OUT => D(2), + LED_GOOD_OUT => D(1) ); - - --------------------------------------------------------------------- -- FEE Readout --------------------------------------------------------------------- - THE_MDC_OEP_READOUT : mdc_addon_daq_bus_0 + THE_MDC_OEP_READOUT : mdc_addon_daq_bus_0 --generic map (bus_number => bus_number) port map ( CLK => CLK_100, @@ -646,7 +632,7 @@ THE_REGIO_BUS_HANDLER : trb_net16_regio_bus_handler D => open, A_RDO_OUT => open, ROC1_WRITTEN_OUT => roc1_written_i, - DATA_TYPE_SELECT_IN => x"0",-- x"0",debug, "1" tow hit in one + DATA_TYPE_SELECT_IN => data_type_select_in_i, DIRECTION_DATA_LINE_OUT => direction_data_line_out_i, MOTHERBOARD_TYPE_IN => motherboard_type_in_i, @@ -657,7 +643,7 @@ THE_REGIO_BUS_HANDLER : trb_net16_regio_bus_handler DEBUG_REGISTER_TRB_INTERFACE => (others => '0'), RAM_ADDRESS_IN => thresh_mem_addr,-- (others => '0'), --8 to 0 - RAM_DATA_IN => thresh_mem_data, --15 to 0 + RAM_DATA_IN => thresh_mem_data,--15 to 0 RAM_DATA_OUT => thresh_mem_data_out, RAM_READ_ENABLE_IN => '0', RAM_WRITE_ENABLE_IN => thresh_mem_write, @@ -770,7 +756,7 @@ THE_REGIO_BUS_HANDLER : trb_net16_regio_bus_handler end if; end process; - D <= "1010" when (counter_led < x"00002710") else "0101"; +-- D <= "1010" when (counter_led < x"00002710") else "0101"; ---------------------------------------------------------------------