From: hadaq <hadaq>
Date: Thu, 30 Jul 2009 12:57:46 +0000 (+0000)
Subject: i hate module generators.
X-Git-Tag: oldGBE~409
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=a5e9bcb52ae07f03423d304618f29b4cca6ae786;p=trbnet.git

i hate module generators.
---

diff --git a/media_interfaces/ecp2m_sfp/serdes_gbe_all.vhd b/media_interfaces/ecp2m_sfp/serdes_gbe_all.vhd
index fbd4315..5c6d933 100755
--- a/media_interfaces/ecp2m_sfp/serdes_gbe_all.vhd
+++ b/media_interfaces/ecp2m_sfp/serdes_gbe_all.vhd
@@ -9,7 +9,7 @@ use IEEE.std_logic_1164.all;
 
 entity PCSC is
 GENERIC(
-  CONFIG_FILE : String  := "serdes_gbe_2.txt"
+  CONFIG_FILE : String  := "serdes_gbe_all.txt"
   );
 port (
   HDINN0             : in std_logic;
@@ -1272,8 +1272,8 @@ library IEEE, STD;
 use IEEE.std_logic_1164.all;
 use STD.TEXTIO.all;
 
-entity serdes_gbe_2 is
-   GENERIC (USER_CONFIG_FILE    :  String := "serdes_gbe_2.txt");
+entity serdes_gbe_all is
+   GENERIC (USER_CONFIG_FILE    :  String := "serdes_gbe_all.txt");
  port (
    core_txrefclk : in std_logic;
    core_rxrefclk : in std_logic;
@@ -1389,9 +1389,9 @@ entity serdes_gbe_2 is
    refck2core : out std_logic;
    ffs_plol : out std_logic);
 
-end serdes_gbe_2;
+end serdes_gbe_all;
 
-architecture serdes_gbe_2_arch of serdes_gbe_2 is
+architecture serdes_gbe_all_arch of serdes_gbe_all is
 
 component VLO
 port (
@@ -2263,4 +2263,4 @@ BEGIN
 END PROCESS;
 --synopsys translate_on
 
-end serdes_gbe_2_arch ;
+end serdes_gbe_all_arch ;