From: Jan Michel Date: Mon, 27 Jan 2014 09:33:57 +0000 (+0100) Subject: added project for 32PinAddOn, make TDC 1.5.1 compiling with it. X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=a5f27382804b971f0ab2c9b9263bdaad0efec6d0;p=trb3.git added project for 32PinAddOn, make TDC 1.5.1 compiling with it. --- diff --git a/32PinAddOn/compile_periph_frankfurt.pl b/32PinAddOn/compile_periph_frankfurt.pl new file mode 100755 index 0000000..5af3b47 --- /dev/null +++ b/32PinAddOn/compile_periph_frankfurt.pl @@ -0,0 +1,153 @@ +#!/usr/bin/perl +use Data::Dumper; +use warnings; +use strict; + + + + +################################################################################### +#Settings for this project +my $TOPNAME = "trb3_periph_32PinAddOn"; #Name of top-level entity +my $lattice_path = '/d/jspc29/lattice/diamond/2.1_x64'; +my $synplify_path = '/d/jspc29/lattice/synplify/F-2012.03-SP1/'; +my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de"; +my $lm_license_file_for_par = "1702\@hadeb05.gsi.de"; +################################################################################### + + +$ENV{'PAR_DESIGN_NAME'}=$TOPNAME; + + +use FileHandle; + +$ENV{'SYNPLIFY'}=$synplify_path; +$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1; +$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify; + + + +my $FAMILYNAME="LatticeECP3"; +my $DEVICENAME="LFE3-150EA"; +my $PACKAGE="FPBGA672"; +my $SPEEDGRADE="8"; + + +#create full lpf file +system("cp ../base/trb3_periph_32PinAddOn.lpf workdir/$TOPNAME.lpf"); +system("cat currentRelease/trbnet_constraints.lpf >> workdir/$TOPNAME.lpf"); +system("cat currentRelease/tdc_constraints.lpf >> workdir/$TOPNAME.lpf"); + + +#set -e +#set -o errexit + +#generate timestamp +my $t=time; +my $fh = new FileHandle(">version.vhd"); +die "could not open file" if (! defined $fh); +print $fh <close; + +system("env| grep LM_"); +my $r = ""; + +my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj"; +$r=execute($c, "do_not_exit" ); + + +chdir "workdir"; +$fh = new FileHandle("<$TOPNAME".".srr"); +my @a = <$fh>; +$fh -> close; + + + +foreach (@a) +{ + if(/\@E:/) + { + print "\n"; + $c="cat $TOPNAME.srr | grep \"\@E\""; + system($c); + print "\n\n"; + exit 129; + } +} + + +$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par; + + +$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|; +execute($c); + +my $tpmap = $TOPNAME . "_map" ; + +$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; +execute($c); + +system("rm $TOPNAME.ncd"); + +#$c=qq|mpartrce -p "../$TOPNAME.p2t" -log "$TOPNAME.log" -o "$TOPNAME.rpt" -pr "$TOPNAME.prf" -tf "$TOPNAME.pt" "|.$TOPNAME.qq|_map.ncd" "$TOPNAME.ncd"|; +# $c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|; +$c=qq|$lattice_path/ispfpga/bin/lin/par -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF $tpmap.ncd $TOPNAME.ncd $TOPNAME.prf|; +execute($c); +# IOR IO Timing Report +# $c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; +# execute($c); + +# TWR Timing Report +$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $TOPNAME.ncd $TOPNAME.bit $TOPNAME.prf|; +# $c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + +chdir ".."; + +exit; + +sub execute { + my ($c, $op) = @_; + #print "option: $op \n"; + $op = "" if(!$op); + print "\n\ncommand to execute: $c \n"; + $r=system($c); + if($r) { + print "$!"; + if($op ne "do_not_exit") { + exit; + } + } + + return $r; + +} diff --git a/32PinAddOn/config.vhd b/32PinAddOn/config.vhd new file mode 100644 index 0000000..4ab7d48 --- /dev/null +++ b/32PinAddOn/config.vhd @@ -0,0 +1,70 @@ +library ieee; +USE IEEE.std_logic_1164.ALL; +use ieee.numeric_std.all; +use work.trb_net_std.all; + +package config is + + +------------------------------------------------------------------------------ +--Begin of design configuration +------------------------------------------------------------------------------ + +--Include GbE logic + constant NUM_TDC_CHANNELS : integer range 1 to 65 := 7; + constant NUM_TDC_CHANNELS_POWER2: integer range 0 to 6 := 3; --the nearest power of two, for convenience reasons + constant USE_DOUBLE_EDGE : integer := c_YES; + +--Include SPI on AddOn connector + constant INCLUDE_SPI : integer := c_NO; + +--Add logic to generate configurable trigger signal from input signals. + constant INCLUDE_TRIGGER_LOGIC : integer := c_YES; + +--Run wih 125 MHz instead of 100 MHz + constant USE_125_MHZ : integer := c_NO; --not implemented yet! + +--Use sync mode, RX clock for all parts of the FPGA + constant USE_RXCLOCK : integer := c_NO; --not implemented yet! + + +--Address settings + constant INIT_ADDRESS : std_logic_vector := x"F305"; + constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"40"; + +------------------------------------------------------------------------------ +--End of design configuration +------------------------------------------------------------------------------ + + +------------------------------------------------------------------------------ +--Select settings by configuration +------------------------------------------------------------------------------ + type intlist_t is array(0 to 7) of integer; + type hw_info_t is array(0 to 7) of unsigned(31 downto 0); + constant HW_INFO_BASE : unsigned(31 downto 0) := x"91007000"; + constant HW_INFO_SPI : hw_info_t := (x"00000000",x"00000400", others => x"00000000"); + constant HW_INFO_DOUBLE_EDGE : hw_info_t := (x"00000000",x"00000800", others => x"00000000"); + constant HW_INFO_NUM_CHANS : hw_info_t := (x"00000000",x"00000010",x"00000020",x"00000030", + x"00000040",x"00000050",x"00000060",x"00000070", others => x"00000000"); + + constant CLOCK_FREQUENCY_ARR : intlist_t := (100,125, others => 0); + constant MEDIA_FREQUENCY_ARR : intlist_t := (200,125, others => 0); + + --declare constants, filled in body + constant HARDWARE_INFO : std_logic_vector(31 downto 0); + constant CLOCK_FREQUENCY : integer; + constant MEDIA_FREQUENCY : integer; + +end; + +package body config is +--compute correct configuration mode + + constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( + HW_INFO_BASE + HW_INFO_SPI(INCLUDE_SPI) + HW_INFO_DOUBLE_EDGE(USE_DOUBLE_EDGE) + + HW_INFO_NUM_CHANS(NUM_TDC_CHANNELS_POWER2)); + constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_125_MHZ); + constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_125_MHZ); + +end package body; \ No newline at end of file diff --git a/32PinAddOn/currentRelease b/32PinAddOn/currentRelease new file mode 120000 index 0000000..1ed173f --- /dev/null +++ b/32PinAddOn/currentRelease @@ -0,0 +1 @@ +../tdc_releases/tdc_v1.5.1 \ No newline at end of file diff --git a/32PinAddOn/trb3_periph_32PinAddOn.prj b/32PinAddOn/trb3_periph_32PinAddOn.prj new file mode 100644 index 0000000..aa1d81c --- /dev/null +++ b/32PinAddOn/trb3_periph_32PinAddOn.prj @@ -0,0 +1,174 @@ + +# implementation: "workdir" +impl -add workdir -type fpga + +# device options +set_option -technology LATTICE-ECP3 +set_option -part LFE3_150EA +set_option -package FN672C +set_option -speed_grade -8 +set_option -part_companion "" + +# compilation/mapping options +set_option -default_enum_encoding sequential +set_option -symbolic_fsm_compiler 1 +set_option -top_module "trb3_periph_32PinAddOn" +set_option -resource_sharing true + +# map options +set_option -frequency 200 +set_option -fanout_limit 100 +set_option -disable_io_insertion 0 +set_option -retiming 0 +set_option -pipe 0 +#set_option -force_gsr +set_option -force_gsr false +set_option -fixgatedclocks false #3 +set_option -fixgeneratedclocks false #3 +set_option -compiler_compatible true + + +# simulation options +set_option -write_verilog 0 +set_option -write_vhdl 1 + +# automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +# set result format/file last +project -result_format "edif" +project -result_file "workdir/trb3_periph_32PinAddOn.edf" + +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 +impl -active "workdir" + +#################### + + + +#add_file options + +add_file -vhdl -lib work "version.vhd" +add_file -vhdl -lib work "config.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" +add_file -vhdl -lib "work" "../base/trb3_components.vhd" + +add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" + +add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" +add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" + +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" + +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" + +add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" +add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" + +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" + +add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd" + + + + +############### +#Change path to tdc release also in compile script! +############### +#add_file -vhdl -lib "work" "currentRelease/Adder_304.vhd" +add_file -vhdl -lib "work" "currentRelease/bit_sync.vhd" +add_file -vhdl -lib "work" "currentRelease/BusHandler.vhd" +add_file -vhdl -lib "work" "currentRelease/Channel.vhd" +add_file -vhdl -lib "work" "currentRelease/Channel_200.vhd" +add_file -vhdl -lib "work" "currentRelease/Encoder_304_Bit.vhd" +add_file -vhdl -lib "work" "currentRelease/FIFO_36x128_OutReg_Counter.vhd" +add_file -vhdl -lib "work" "currentRelease/LogicAnalyser.vhd" +add_file -vhdl -lib "work" "currentRelease/Readout.vhd" +add_file -vhdl -lib "work" "currentRelease/ROM4_Encoder.vhd" +add_file -vhdl -lib "work" "currentRelease/ROM_encoder_3.vhd" +add_file -vhdl -lib "work" "currentRelease/ShiftRegisterSISO.vhd" +add_file -vhdl -lib "work" "currentRelease/TDC.vhd" +#add_file -vhdl -lib "work" "currentRelease/TriggerHandler.vhd" +add_file -vhdl -lib "work" "currentRelease/up_counter.vhd" +add_file -vhdl -lib "work" "currentRelease/fallingEdgeDetect.vhd" +add_file -vhdl -lib "work" "currentRelease/risingEdgeDetect.vhd" +add_file -vhdl -lib "work" "../base/cores/FIFO_36x128_OutReg.vhd" +add_file -vhdl -lib "work" "../base/cores/FIFO_DC_36x128_OutReg.vhd" +add_file -vhdl -lib "work" "currentRelease/Reference_Channel_200.vhd" +add_file -vhdl -lib "work" "currentRelease/Reference_Channel.vhd" + +add_file -vhdl -lib "work" "../base/code/input_to_trigger_logic.vhd" + +add_file -vhdl -lib "work" "trb3_periph_32PinAddOn.vhd" + diff --git a/32PinAddOn/trb3_periph_32PinAddOn.vhd b/32PinAddOn/trb3_periph_32PinAddOn.vhd index 0a2eb9b..ae0dc5d 100644 --- a/32PinAddOn/trb3_periph_32PinAddOn.vhd +++ b/32PinAddOn/trb3_periph_32PinAddOn.vhd @@ -6,6 +6,7 @@ library work; use work.trb_net_std.all; use work.trb_net_components.all; use work.trb3_components.all; +use work.config.all; use work.version.all; @@ -89,8 +90,8 @@ end entity; architecture trb3_periph_32PinAddOn_arch of trb3_periph_32PinAddOn is --Constants - constant REGIO_NUM_STAT_REGS : integer := 3; - constant REGIO_NUM_CTRL_REGS : integer := 3; + constant REGIO_NUM_STAT_REGS : integer := 0; + constant REGIO_NUM_CTRL_REGS : integer := 0; attribute syn_keep : boolean; attribute syn_preserve : boolean; @@ -248,6 +249,15 @@ architecture trb3_periph_32PinAddOn_arch of trb3_periph_32PinAddOn is signal spi_bram_rd_d : std_logic_vector(7 downto 0); signal spi_bram_we : std_logic; + signal trig_out : std_logic_vector(3 downto 0); + signal trig_din : std_logic_vector(31 downto 0); + signal trig_dout : std_logic_vector(31 downto 0); + signal trig_write : std_logic := '0'; + signal trig_read : std_logic := '0'; + signal trig_ack : std_logic := '0'; + signal trig_nack : std_logic := '0'; + signal trig_addr : std_logic_vector(15 downto 0) := (others => '0'); + --TDC signal hit_in_i : std_logic_vector(64 downto 1); signal logic_analyser_i : std_logic_vector(15 downto 0); @@ -348,34 +358,19 @@ begin --------------------------------------------------------------------------- -- Endpoint --------------------------------------------------------------------------- - --regio_hardware_version_i <= x"9100" & addOn_type_i & edge_type_i & tdc_channel_no_i & x"0"; - - --addOn_type_i <= x"0"; -- x"0" - ADA AddOn version 1 - -- -- x"1" - ADA AddOn version 2 - -- -- x"2" - multi purpose test AddOn - -- -- x"3" - SFP hub AddOn - -- -- x"4" - Wasa AddOn - -- -- x"5" - GeneralPurpose AddOn - -- -- x"6" - Nxyter - -- -- x"7" - 32PinAddOn - --edge_type_i <= x"0"; -- x"0" - single edge - -- -- x"1" - double edge - -- -- x"4" - has spi interface - -- -- x"8" - double edge on consecutive channels - --tdc_channel_no_i <= x"6"; -- 2^n channels - + THE_ENDPOINT : trb_net16_endpoint_hades_full_handler generic map( - REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, --4, --16 stat reg - REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, --3, --8 cotrol reg + REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, + REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, ADDRESS_MASK => x"FFFF", BROADCAST_BITMASK => x"FF", - BROADCAST_SPECIAL_ADDR => x"48", + BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR, REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)), - REGIO_HARDWARE_VERSION => x"91007C60", -- regio_hardware_version_i, - REGIO_INIT_ADDRESS => x"f305", + REGIO_HARDWARE_VERSION => HARDWARE_INFO, + REGIO_INIT_ADDRESS => INIT_ADDRESS, REGIO_USE_VAR_ENDPOINT_ID => c_YES, - CLOCK_FREQUENCY => 100, + CLOCK_FREQUENCY => CLOCK_FREQUENCY, TIMING_TRIGGER_RAW => c_YES, --Configure data handler DATA_INTERFACE_NUMBER => 1, @@ -486,9 +481,9 @@ begin --------------------------------------------------------------------------- THE_BUS_HANDLER : trb_net16_regio_bus_handler generic map( - PORT_NUMBER => 9, - PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"d400", 3 => x"c000", 4 => x"c100", 5 => x"c200", 6 => x"c300", 7 => x"c400", 8 => x"c800", others => x"0000"), - PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 5, 3 => 7, 4 => 5, 5 => 7, 6 => 7, 7 => 7, 8 => 3, others => 0) + PORT_NUMBER => 10, + PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"d400", 3 => x"c000", 4 => x"c100", 5 => x"c200", 6 => x"c300", 7 => x"c400", 8 => x"c800", 9 => x"a000", others => x"0000"), + PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 5, 3 => 7, 4 => 5, 5 => 7, 6 => 7, 7 => 7, 8 => 3, 9 => 4, others => 0) ) port map( CLK => clk_100_i, @@ -613,7 +608,17 @@ begin BUS_WRITE_ACK_IN(8) => tdc_ctrl_write, BUS_NO_MORE_DATA_IN(8) => '0', BUS_UNKNOWN_ADDR_IN(8) => '0', - + --Trigger logic registers + BUS_READ_ENABLE_OUT(9) => trig_read, + BUS_WRITE_ENABLE_OUT(9) => trig_write, + BUS_DATA_OUT(9*32+31 downto 9*32) => trig_din, + BUS_ADDR_OUT(9*16+15 downto 9*16) => trig_addr, + BUS_TIMEOUT_OUT(9) => open, + BUS_DATA_IN(9*32+31 downto 9*32) => trig_dout, + BUS_DATAREADY_IN(9) => trig_ack, + BUS_WRITE_ACK_IN(9) => trig_ack, + BUS_NO_MORE_DATA_IN(9) => '0', + BUS_UNKNOWN_ADDR_IN(9) => trig_nack, STAT_DEBUG => open ); @@ -681,8 +686,9 @@ begin ); ------------------------------------------------------------------------------- --- DAC +-- SPI ------------------------------------------------------------------------------- +gen_SPI : if INCLUDE_SPI = 1 generate DAC_SPI : spi_ltc2600 generic map ( BITS => 14, @@ -705,6 +711,41 @@ begin SPI_SCK_OUT => DAC_OUT_SCK, SPI_CLR_OUT(0) => DAC_OUT_CLR ); +end generate; + + +gen_NO_SPI : if INCLUDE_SPI = 0 generate + DAC_OUT_SDO <= trig_out(0); + DAC_OUT_SCK <= trig_out(1); + DAC_OUT_CS <= trig_out(2); + DAC_OUT_CLR <= trig_out(3); +end generate; + + +--------------------------------------------------------------------------- +-- Trigger logic +--------------------------------------------------------------------------- +gen_TRIGGER_LOGIC : if INCLUDE_TRIGGER_LOGIC = 1 generate + THE_TRIG_LOGIC : input_to_trigger_logic + generic map( + INPUTS => 24, + OUTPUTS => 4 + ) + port map( + CLK => clk_100_i, + + INPUT => INP(24 downto 1), + OUTPUT => trig_out, + + DATA_IN => trig_din, + DATA_OUT => trig_dout, + WRITE_IN => trig_write, + READ_IN => trig_read, + ACK_OUT => trig_ack, + NACK_OUT => trig_nack, + ADDR_IN => trig_addr + ); +end generate; --------------------------------------------------------------------------- -- Reboot FPGA @@ -737,10 +778,10 @@ begin THE_TDC : TDC generic map ( - CHANNEL_NUMBER => 5, -- Number of TDC channels - STATUS_REG_NR => 20, -- Number of status regs - CONTROL_REG_NR => 6, -- Number of control regs - higher than 8 check tdc_ctrl_addr - TDC_VERSION => x"160", -- TDC version number + CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels + STATUS_REG_NR => 20, -- Number of status regs + CONTROL_REG_NR => 6, -- Number of control regs - higher than 8 check tdc_ctrl_addr + TDC_VERSION => x"160", -- TDC version number DEBUG => c_YES, SIMULATION => c_NO) port map ( @@ -748,7 +789,7 @@ begin CLK_TDC => CLK_PCLK_LEFT, -- Clock used for the time measurement CLK_READOUT => clk_100_i, -- Clock for the readout REFERENCE_TIME => timing_trg_received_i, -- Reference time input - HIT_IN => hit_in_i(4 downto 1), -- Channel start signals + HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals HIT_CALIBRATION => osc_int, --clk_20_i, -- Hits for calibrating the TDC TRG_WIN_PRE => tdc_ctrl_reg(42 downto 32), -- Pre-Trigger window width TRG_WIN_POST => tdc_ctrl_reg(58 downto 48), -- Post-Trigger window width @@ -815,17 +856,20 @@ begin CONTROL_REG_IN => tdc_ctrl_reg); -- For single edge measurements - --hit_in_i <= INP; - --hit_in_i <= (others => timing_trg_received_i); + gen_single : if USE_DOUBLE_EDGE = 0 generate + hit_in_i <= INP; +-- hit_in_i <= (others => timing_trg_received_i); + end generate; -- For ToT Measurements - Gen_Hit_In_Signals : for i in 1 to 32 generate - hit_in_i(i*2-1) <= INP(i-1); - hit_in_i(i*2) <= not INP(i-1); - end generate Gen_Hit_In_Signals; + gen_double : if USE_DOUBLE_EDGE = 1 generate + Gen_Hit_In_Signals : for i in 1 to 32 generate + hit_in_i(i*2-1) <= INP(i-1); + hit_in_i(i*2) <= not INP(i-1); + end generate Gen_Hit_In_Signals; + end generate; -- Trigger on a TDC Channel FPGA5_COMM(10) <= hit_in_i(to_integer(unsigned(tdc_ctrl_reg(5*32+7 downto 5*32)))); --- !!!!! IMPORTANT !!!!! Don't forget to set the REGIO_HARDWARE_VERSION !!!!! end architecture; diff --git a/base/code/input_to_trigger_logic.vhd b/base/code/input_to_trigger_logic.vhd new file mode 100644 index 0000000..d37ee77 --- /dev/null +++ b/base/code/input_to_trigger_logic.vhd @@ -0,0 +1,46 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + + +entity input_to_trigger_logic is + generic( + INPUTS : integer range 1 to 32 := 24; + OUTPUTS : integer range 1 to 16 := 4 + ); + port( + CLK : in std_logic; + + INPUT : in std_logic_vector(INPUTS-1 downto 0); + OUTPUT : out std_logic_vector(OUTPUTS-1 downto 0); + + DATA_IN : in std_logic_vector(31 downto 0) := (others => '0'); + DATA_OUT : out std_logic_vector(31 downto 0); + WRITE_IN : in std_logic := '0'; + READ_IN : in std_logic := '0'; + ACK_OUT : out std_logic; + NACK_OUT : out std_logic; + ADDR_IN : in std_logic_vector(15 downto 0) := (others => '0') + + ); +end entity; + + + +architecture input_to_trigger_logic_arch of input_to_trigger_logic is + + + +begin + +OUTPUT <= INPUT(OUTPUTS-1 downto 0); + +THE_CONTROL : process begin + wait until rising_edge(CLK); + + +end process; + + +end architecture; \ No newline at end of file diff --git a/base/trb3_components.vhd b/base/trb3_components.vhd index 52656d9..9bd15c0 100644 --- a/base/trb3_components.vhd +++ b/base/trb3_components.vhd @@ -713,5 +713,26 @@ package trb3_components is ); end component; + component input_to_trigger_logic is + generic( + INPUTS : integer range 1 to 32 := 24; + OUTPUTS : integer range 1 to 16 := 4 + ); + port( + CLK : in std_logic; + + INPUT : in std_logic_vector(INPUTS-1 downto 0); + OUTPUT : out std_logic_vector(OUTPUTS-1 downto 0); + + DATA_IN : in std_logic_vector(31 downto 0) := (others => '0'); + DATA_OUT : out std_logic_vector(31 downto 0); + WRITE_IN : in std_logic := '0'; + READ_IN : in std_logic := '0'; + ACK_OUT : out std_logic; + NACK_OUT : out std_logic; + ADDR_IN : in std_logic_vector(15 downto 0) := (others => '0') + + ); + end component; end package; diff --git a/tdc_releases/tdc_v1.5.1/Channel.vhd b/tdc_releases/tdc_v1.5.1/Channel.vhd index 1f6d6df..14dadf1 100644 --- a/tdc_releases/tdc_v1.5.1/Channel.vhd +++ b/tdc_releases/tdc_v1.5.1/Channel.vhd @@ -88,7 +88,7 @@ begin hit_in_i <= HIT_IN; hit_buf <= not hit_in_i; - Channel_200_1 : Channel_200 + Channel_200_1 : entity work.Channel_200 generic map ( CHANNEL_ID => CHANNEL_ID) port map ( diff --git a/tdc_releases/tdc_v1.5.1/TDC.vhd b/tdc_releases/tdc_v1.5.1/TDC.vhd index f749f95..7957e75 100644 --- a/tdc_releases/tdc_v1.5.1/TDC.vhd +++ b/tdc_releases/tdc_v1.5.1/TDC.vhd @@ -13,7 +13,7 @@ entity TDC is generic ( CHANNEL_NUMBER : integer range 2 to 65; CONTROL_REG_NR : integer range 0 to 6; - TDC_VERSION : std_logic_vector(10 downto 0)); + TDC_VERSION : std_logic_vector(11 downto 0)); port ( RESET : in std_logic; CLK_TDC : in std_logic; @@ -244,7 +244,7 @@ begin -- Channels GEN_Channels : for i in 1 to CHANNEL_NUMBER - 1 generate - Channels : Channel + Channels : entity work.Channel generic map ( CHANNEL_ID => i) port map ( @@ -276,7 +276,7 @@ begin TheReadout : Readout generic map ( CHANNEL_NUMBER => CHANNEL_NUMBER, - TDC_VERSION => TDC_VERSION) + TDC_VERSION => TDC_VERSION(10 downto 0)) port map ( CLK_200 => CLK_TDC, RESET_200 => reset_tdc,