From: Michael Boehmer Date: Fri, 11 Feb 2022 16:51:27 +0000 (+0100) Subject: TDC in CTS included X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=a60c55df8928287ac658c9bcddaa673e263c6c9d;p=trb3sc.git TDC in CTS included --- diff --git a/cts/config_compile_gsi.pl b/cts/config_compile_gsi.pl index 676238c..fb49b71 100644 --- a/cts/config_compile_gsi.pl +++ b/cts/config_compile_gsi.pl @@ -10,7 +10,7 @@ pinout_file => 'trb3sc_hub_kelpadiwa', par_options => '../par.p2t', #mapper_options => ' ', -include_TDC => 0, +include_TDC => 1, include_GBE => 1, firefox_open => 0, diff --git a/cts/trb3sc_cts.lpf b/cts/trb3sc_cts.lpf index b90464c..e8eaaa2 100644 --- a/cts/trb3sc_cts.lpf +++ b/cts/trb3sc_cts.lpf @@ -7,10 +7,18 @@ REGION "MEDIA_LEFT" "R102C17D" 13 75; # LEFT is for PCSD/PCSB REGION "MEDIA_RIGHT" "R102C92D" 13 75; # RIGHT is for PCSA/PCSC LOCATE UGROUP "gen_PCSB.THE_MEDIA_PCSB/media_interface_group" REGION "MEDIA_LEFT"; -#LOCATE UGROUP "gen_PCSB.THE_MEDIA_PCSB/gen_control.3.gen_phaser.THE_PHASER/THE_PHASER_CORE/phaser_core_group" SITE "R111C77D"; # +# read from SCI can be delayed due to long read strobe +MULTICYCLE FROM ASIC gen_PCSB.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns; +# write strobe can be delayed due to A/D being stable after access +MULTICYCLE TO ASIC gen_PCSB.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns; -#LOCATE UGROUP "gen_PCSB.THE_MEDIA_PCSB/gen_control.3.gen_phaser.THE_PHASER/THE_PHASER_CORE/phaser_core_group" SITE "R101C87D"; # +# SCI write signal problem... +#BLOCK NET gen_PCSB.THE_MEDIA_PCSB/sci_write_i; +#BLOCK INTERCLOCKDOMAIN PATHS; +################################################################################################################### +################################################################################################################### +#### OLD constraints BLOCK PATH FROM CELL THE_TDC/calibration_o*; BLOCK PATH FROM CELL THE_CTS/TIME_REFERENCE_OUT TO CELL THE_TDC/ReferenceChannel/Channel200/SimAdderNo.FC/FF*; BLOCK PATH FROM CELL THE_CTS/TIME_REFERENCE_OUT TO CELL THE_TDC/TheTriggerHandler/trg_in_r[0]; @@ -18,6 +26,10 @@ BLOCK PATH FROM CELL THE_CTS/TIME_REFERENCE_OUT TO CELL THE_TDC/TheTriggerHandle FREQUENCY NET "GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/clk_int.SERDES_GBE/sd_rx_clk_1" 125.0 MHz; FREQUENCY NET "GBE/clk_125_rx_from_pcs[3]" 125 MHz; +PROHIBIT SECONDARY NET "THE_TOOLS/gen_STATISTICS.THE_STAT_LOGIC/reset_cnt" ; + +### DUMPING AREA + #MULTICYCLE TO CELL "gen_PCSB.THE_MEDIA_PCSB/sci*" 20 ns; #MULTICYCLE FROM CELL "gen_PCSB.THE_MEDIA_PCSB/sci*" 20 ns; #MULTICYCLE TO CELL "gen_PCSB.THE_MEDIA_PCSB/PROC_SCI_CTRL.wa*" 20 ns; @@ -50,5 +62,3 @@ FREQUENCY NET "GBE/clk_125_rx_from_pcs[3]" 125 MHz; #MULTICYCLE TO ASIC gen_PCSC.THE_MEDIA_PCSC/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; #MAXDELAY TO ASIC gen_PCSC.THE_MEDIA_PCSC/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; - -PROHIBIT SECONDARY NET "THE_TOOLS/gen_STATISTICS.THE_STAT_LOGIC/reset_cnt" ; diff --git a/cts/trb3sc_cts.prj b/cts/trb3sc_cts.prj index b190322..e271d83 100644 --- a/cts/trb3sc_cts.prj +++ b/cts/trb3sc_cts.prj @@ -139,9 +139,6 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control_RS add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_all_RS.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd" -add_file -vhdl -lib work "../../trbnet/special/phaser.vhd" -add_file -vhdl -lib work "../../trbnet/special/phaser_core.vhd" - #TrbNet Endpoint add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" diff --git a/cts/trb3sc_cts.vhd b/cts/trb3sc_cts.vhd index 992850c..38258f5 100644 --- a/cts/trb3sc_cts.vhd +++ b/cts/trb3sc_cts.vhd @@ -255,11 +255,6 @@ architecture trb3sc_arch of trb3sc_cts is signal tx_rst_x : std_logic; signal wap_requested_i : std_logic_vector(3 downto 0); - signal rx_index_i : std_logic_vector(3 downto 0); - signal phaser_data : std_logic_vector(31 downto 0); - signal phaser_update : std_logic; - signal coarse_counter : unsigned(15 downto 0); - signal coarse_delay : std_logic_vector(15 downto 0); signal slv_act_cnt : unsigned(7 downto 0); signal slave_active_fake : std_logic; @@ -410,11 +405,6 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate DESTROY_LINK_IN(2) => '0', DESTROY_LINK_IN(3) => destroy_link_i, WAP_REQUESTED_IN => wap_requested_i, - RX_INDEX_OUT => rx_index_i, - DLM_RESULT_OUT(0*32+31 downto 0*32) => open, - DLM_RESULT_OUT(1*32+31 downto 1*32) => open, - DLM_RESULT_OUT(2*32+31 downto 2*32) => open, - DLM_RESULT_OUT(3*32+31 downto 3*32) => phaser_data, --SFP Connection SD_PRSNT_N_IN(0) => '1', SD_LOS_IN(0) => '1', @@ -531,6 +521,7 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate end if; end process THE_RST_SEND_PROC; + -- send on rising edge of signal tx_rst_x <= not pulse_detect(7) and pulse_detect(6); end generate; @@ -538,15 +529,17 @@ end generate; --------------------------------------------------------------------------- -- PCSC: not used --------------------------------------------------------------------------- - bussci3_tx.data <= phaser_data; - bussci3_tx.ack <= bussci3_rx.read or bussci3_rx.write when rising_edge(clk_sys); + bussci3_tx.data <= (others => '0'); + bussci3_tx.ack <= '0'; bussci3_tx.nack <= '0'; - bussci3_tx.unknown <= '0'; + bussci3_tx.unknown <= bussci3_rx.read or bussci3_rx.write when rising_edge(clk_sys); --- bussci3_tx.data <= (others => '0'); --- bussci3_tx.ack <= '0'; +-- can be used for simple readback on debugging +-- bussci3_tx.data <= phaser_data; +-- bussci3_tx.ack <= bussci3_rx.read or bussci3_rx.write when rising_edge(clk_sys); -- bussci3_tx.nack <= '0'; --- bussci3_tx.unknown <= bussci3_rx.read or bussci3_rx.write when rising_edge(clk_sys); +-- bussci3_tx.unknown <= '0'; + --------------------------------------------------------------------------- -- PCSD: GbE