From: Hades DAQ <hadaq@hadesp69.hades.gsi.de>
Date: Mon, 13 Jun 2022 08:46:20 +0000 (+0200)
Subject: trb5sc_template.prj
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=a61de656c281e13d235e33a934eea025d86c05ec;p=trb5sc.git

trb5sc_template.prj
---

diff --git a/cbmrich/trb5sc_cbmrich.prj b/cbmrich/trb5sc_cbmrich.prj
index 11a145b..61b81c3 100644
--- a/cbmrich/trb5sc_cbmrich.prj
+++ b/cbmrich/trb5sc_cbmrich.prj
@@ -66,9 +66,11 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_components.vhd"
 
 #Basic Infrastructure
 add_file -vhdl -lib work "../../dirich/cores/pll_240_100/pll_240_100.vhd"
+add_file -vhdl -lib work "../../dirich/cores/pll_200_100.vhd"
 add_file -vhdl -lib work "../../dirich/cores/ecp5/pll_200_240.vhd"
-#add_file -vhdl -lib work "../../dirich/code/clock_reset_handler.vhd"
-add_file -vhdl -lib work "../../dirich/code/clock_reset_handler_240.vhd"
+#add_file -vhdl -lib work "../../dirich/cores/ecp5/pll_200_240.vhd"
+add_file -vhdl -lib work "../../dirich/code/clock_reset_handler.vhd"
+#add_file -vhdl -lib work "../../dirich/code/clock_reset_handler_240.vhd"
 add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
 add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd"
 add_file -vhdl -lib work "../../vhdlbasics/ecp5/sedcheck.vhd"
@@ -177,12 +179,17 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync_240.vh
 
 #channel 1, SFP
 add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/240MHz/chan0_1/serdes_sync_0.vhd"
+#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_1/serdes_sync_0.vhd"
 ##########################################
 
-add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/240MHz/pcs_240.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/240MHz/pcs2_240.vhd"
-add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/240MHz/serdes_sync_0_softlogic.v"
+#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/240MHz/pcs_240.vhd"
+#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/240MHz/pcs2_240.vhd"
+
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs2.vhd"
 
+#add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/240MHz/serdes_sync_0_softlogic.v"
+add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_softlogic.v"
 
 #TrbNet Endpoint
 add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"
diff --git a/template/README b/template/README
new file mode 100644
index 0000000..ce23de4
--- /dev/null
+++ b/template/README
@@ -0,0 +1,4 @@
+The tdc branch has to be
+sep17
+
+$ git checkout sep17
diff --git a/template/trb5sc_template.prj b/template/trb5sc_template.prj
index af55465..1212a85 100644
--- a/template/trb5sc_template.prj
+++ b/template/trb5sc_template.prj
@@ -66,7 +66,7 @@ add_file -vhdl -lib work "../../dirich/cores/pll_240_100/pll_240_100.vhd"
 add_file -vhdl -lib work "../../dirich/code/clock_reset_handler.vhd"
 add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
 add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd"
-add_file -vhdl -lib work "../../dirich/code/sedcheck.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/ecp5/sedcheck.vhd"
 
 
 #Fifos
@@ -153,6 +153,7 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_1/serdes_sync
 ##########################################
 
 add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs2.vhd"
 add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_softlogic.v"
 
 
@@ -187,6 +188,7 @@ add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_gbe.vhd"
 add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd"
 add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd"
 add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd"