From: Manuel Penschuck <manuel.penschuck@stud.uni-frankfurt.de>
Date: Wed, 18 Jun 2014 16:41:01 +0000 (+0200)
Subject: Data transport works in the straight-forward case
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=a64313cc9684a6a2718741366c54709684c93454;p=trb3.git

Data transport works in the straight-forward case
---

diff --git a/cbmnet/code/cbmnet_interface_pkg.vhd b/cbmnet/code/cbmnet_interface_pkg.vhd
index 7931d1f..4d0111a 100644
--- a/cbmnet/code/cbmnet_interface_pkg.vhd
+++ b/cbmnet/code/cbmnet_interface_pkg.vhd
@@ -187,6 +187,19 @@ package cbmnet_interface_pkg is
       );
    end component;
 
+   component dlm_reflect is 
+   port
+   (
+      clk            : in std_logic;
+      res_n          : in std_logic;
+      dlm_rec_in     : in std_logic_vector(3 downto 0);
+      dlm_rec_va_in  : in std_logic;
+      dlm_rec_out    : out std_logic_vector(3 downto 0);
+      dlm_rec_va_out : out std_logic;
+      dlm2send_va    : out std_logic;
+      dlm2send       : out std_logic_vector(3 downto 0)
+   );
+   end component;
    
    component link_tester_be is
       generic (
diff --git a/cbmnet/code/cbmnet_phy_ecp3.vhd b/cbmnet/code/cbmnet_phy_ecp3.vhd
index b08328b..5bd00a0 100755
--- a/cbmnet/code/cbmnet_phy_ecp3.vhd
+++ b/cbmnet/code/cbmnet_phy_ecp3.vhd
@@ -13,7 +13,8 @@ use work.cbmnet_phy_pkg.all;
 
 entity cbmnet_phy_ecp3 is
    generic(
-      IS_SYNC_SLAVE   : integer := c_NO;       --select slave mode
+      IS_SYNC_SLAVE   : integer := c_YES;       --select slave mode
+      DETERMINISTIC_LATENCY : integer := c_NO; -- if selected proper alignment of barrel shifter and word alignment is enforced (link may come up slower)
       IS_SIMULATED    : integer := c_NO;
       INCL_DEBUG_AIDS : integer := c_YES
    );
@@ -54,7 +55,7 @@ entity cbmnet_phy_ecp3 is
       -- Status and control port
       STAT_OP            : out std_logic_vector ( 15 downto 0) := (others => '0');
       CTRL_OP            : in  std_logic_vector ( 15 downto 0) := (others => '0');
-      DEBUG_OUT          : out std_logic_vector (255 downto 0) := (others => '0')
+      DEBUG_OUT          : out std_logic_vector (511 downto 0) := (others => '0')
    );
 end entity;
 
@@ -72,6 +73,7 @@ architecture cbmnet_phy_ecp3_arch of cbmnet_phy_ecp3 is
    attribute syn_sharing of cbmnet_phy_ecp3_arch : architecture is "off";
 
    constant WA_FIXATION : integer := c_YES;
+   signal DETERMINISTIC_LATENCY_C : std_logic;
 
 -- Clocks and global resets   
    signal clk_125_local     : std_logic;  -- local 125 MHz reference clock driven by clock generators
@@ -95,7 +97,9 @@ architecture cbmnet_phy_ecp3_arch of cbmnet_phy_ecp3 is
    signal tx_pll_lol_i  : std_logic;
    signal lsm_status_i : std_logic;
 
-   signal rx_dec_error_i: std_logic;
+   signal rx_dec_error_i:     std_logic;
+   signal rx_dec_error_125_i, rx_dec_error_125_buf_i: std_logic_vector(1 downto 0);
+
    signal rx_error_delay : std_logic_vector(3 downto 0); -- shift register to detect a "stable error condition"
    
    -- resets
@@ -212,6 +216,8 @@ architecture cbmnet_phy_ecp3_arch of cbmnet_phy_ecp3 is
 -- Stats
    signal stat_reconnect_counter_i : unsigned(15 downto 0); -- counts the number of RX-serdes resets since last external reset
    signal stat_last_reconnect_duration_i : unsigned(31 downto 0);
+   signal stat_decode_error_counter_i : unsigned(31 downto 0);
+   
    
    signal stat_wa_int_i : std_logic_vector(15 downto 0) := (others => '0');
    
@@ -223,9 +229,23 @@ architecture cbmnet_phy_ecp3_arch of cbmnet_phy_ecp3 is
    signal low_level_tx_see_dlm0_125 : std_logic;
    
    signal stat_dlm_counter_i : unsigned(15 downto 0);
+   signal stat_init_ack_counter_i : unsigned(15 downto 0);
+   
+   signal test_line_i : std_logic_vector(15 downto 0) := x"0001";
+   
+   signal rx_stab_i, tx_stab_i : unsigned(15 downto 0);
+   
+   signal rx_data_sp_i0, rx_data_sp_i1, rx_data_sp_i2, rx_data_sp_i3 : std_logic_vector(17 downto 0);
+   
 begin
+   assert IS_SYNC_SLAVE = c_YES 
+      report "Support of clock master PHY is not tested anymore and probably broken"
+      severity failure;
+	  
+   DETERMINISTIC_LATENCY_C <= '1' when DETERMINISTIC_LATENCY = c_YES else '0';
+
    clk_125_local <= CLK;
-   CLK_RX_HALF_OUT <= rclk_125_i when IS_SYNC_SLAVE = c_YES or 1=1 else clk_tx_half_i;
+   CLK_RX_HALF_OUT <= rclk_125_i when IS_SYNC_SLAVE = c_YES else clk_tx_half_i;
    CLK_RX_FULL_OUT <= rclk_250_i;
 
    SD_TXDIS_OUT <= '0';
@@ -338,9 +358,26 @@ begin
       RX_PCS_RST_CH_C     => rx_pcs_rst_i,
       STATE_OUT           => rx_rst_fsm_state_i
    );
-   byte_alignment_to_fsm_i <= (not barrel_shifter_misaligned_i) or CTRL_OP(3);
-   word_alignment_to_fsm_i <= not (gear_to_fsm_rst_i or AND_ALL(rx_error_delay));
-   rx_error_delay <= rx_error_delay(rx_error_delay'high - 1 downto 0) & rx_dec_error_i when rising_edge(clk_125_local);
+   byte_alignment_to_fsm_i <= not (DETERMINISTIC_LATENCY_C and barrel_shifter_misaligned_i) or CTRL_OP(3);
+   word_alignment_to_fsm_i <= not (gear_to_fsm_rst_i or AND_ALL(rx_error_delay)) or CTRL_OP(5);
+   
+   
+   -- decode error
+   rx_dec_error_125_i <= rx_dec_error_125_i(0) & rx_dec_error_i when rising_edge(rclk_250_i);
+   rx_dec_error_125_buf_i <= rx_dec_error_125_i when rising_edge(clk_125_local);
+   
+   rx_error_delay <= rx_error_delay(rx_error_delay'high - 2 downto 0) & rx_dec_error_125_buf_i when rising_edge(clk_125_local);
+   process is 
+   begin
+      wait until rising_edge(clk_125_i);
+      if RESET='1' then
+         stat_decode_error_counter_i <= (others => '0');
+      elsif rx_dec_error_125_buf_i = "11" then
+         stat_decode_error_counter_i <= stat_decode_error_counter_i + 2;
+      elsif rx_dec_error_125_buf_i = "10" or rx_dec_error_125_buf_i = "01" then
+         stat_decode_error_counter_i <= stat_decode_error_counter_i + 1;
+      end if;
+   end process;
    
       
    THE_TX_FSM : cbmnet_phy_ecp3_tx_reset_fsm
@@ -425,24 +462,24 @@ begin
       DATA_OUT    => tx_data_to_serdes_i -- out std_logic_vector(8 downto 0);
    );
    tx_gear_reset_i <= not tx_rst_fsm_ready_i;
-   tx_gear_allow_relock_i <= ((not tx_rst_fsm_ready_i) and not CTRL_OP(1)) or CTRL_OP(2);
-   
-   process is
-   begin
-      wait until rising_edge(clk_tx_full_i);
-      
-      tx_data_debug_state_i <= not tx_data_debug_state_i;
-      
-      if tx_data_debug_state_i = '1' then
-         tx_data_debug_i(7 downto 0) <= tx_data_to_serdes_i(7 downto 0);
-         tx_data_debug_i(16) <= tx_data_to_serdes_i(8);
-         
-      else
-         tx_data_debug_i(15 downto 8) <= tx_data_to_serdes_i(7 downto 0);
-         tx_data_debug_i(17) <= tx_data_to_serdes_i(8);
-      
-      end if;
-   end process;
+   tx_gear_allow_relock_i <= (not tx_rst_fsm_ready_i and not CTRL_OP(1) and DETERMINISTIC_LATENCY_C) or CTRL_OP(2);
+   
+--    process is
+--    begin
+--       wait until rising_edge(clk_tx_full_i);
+--       
+--       tx_data_debug_state_i <= not tx_data_debug_state_i;
+--       
+--       if tx_data_debug_state_i = '1' then
+--          tx_data_debug_i(7 downto 0) <= tx_data_to_serdes_i(7 downto 0);
+--          tx_data_debug_i(16) <= tx_data_to_serdes_i(8);
+--          
+--       else
+--          tx_data_debug_i(15 downto 8) <= tx_data_to_serdes_i(7 downto 0);
+--          tx_data_debug_i(17) <= tx_data_to_serdes_i(8);
+--       
+--       end if;
+--    end process;
          
    -------------------------------------------------      
    -- CBMNet Ready Modules
@@ -469,16 +506,16 @@ begin
       ebtb_detect             => rm_rx_ebtb_detect_i,   -- out std_logic;                    -- Depends on the FSM state, alignment done
       
       --diagnostics
-      ebtb_code_err_cntr_clr  => rm_rx_ebtb_code_err_cntr_clr_i, -- in std_logic;
-      ebtb_disp_err_cntr_clr  => rm_rx_ebtb_disp_err_cntr_clr_i, -- in std_logic;
-      ebtb_code_err_cntr      => rm_rx_ebtb_code_err_cntr_i,     -- out std_logic_vector(15 downto 0); -- Counts for code errors if ebtb_detect is true
-      ebtb_disp_err_cntr      => rm_rx_ebtb_disp_err_cntr_i,     -- out std_logic_vector(15 downto 0); -- Counts for disparity errors if ebtb_detect is true
-      ebtb_code_err_cntr_flag => rm_rx_ebtb_code_err_cntr_flag_i,-- out std_logic;
-      ebtb_disp_err_cntr_flag => rm_rx_ebtb_disp_err_cntr_flag_i -- out std_logic
+      ebtb_code_err_cntr_clr  => '0', -- in std_logic;
+      ebtb_disp_err_cntr_clr  => '0', -- in std_logic;
+      ebtb_code_err_cntr      => open,     -- out std_logic_vector(15 downto 0); -- Counts for code errors if ebtb_detect is true
+      ebtb_disp_err_cntr      => open,     -- out std_logic_vector(15 downto 0); -- Counts for disparity errors if ebtb_detect is true
+      ebtb_code_err_cntr_flag => open,-- out std_logic;
+      ebtb_disp_err_cntr_flag => open -- out std_logic
    );
 
-   PHY_RXDATA_OUT   <= rm_rx_data_buf_i(15 downto 0);
-   PHY_RXDATA_K_OUT <= rm_rx_data_buf_i(1 downto 0);
+   PHY_RXDATA_OUT   <= rx_data_i(15 downto 0);
+   PHY_RXDATA_K_OUT <= rx_data_i(17 downto 16);
    gear_to_rm_n_rst_i <= not gear_to_rm_rst_i when rising_edge(clk_125_i);
    
    
@@ -596,36 +633,6 @@ begin
       end if;
    end process;
    
-   
-   -- RX/TX leds are on as soon as the correspondent pll is locked and data
-   -- other than the idle word is transmitted
-   PROC_LEDS: process is
-   begin
-      wait until rising_edge(CLK);
-
-      led_rx_i <= not gear_to_rm_rst_i;
-      led_tx_i <= tx_rst_fsm_ready_i;
-      
-      if (led_timer_i(20) = '1') or (rx_data_i(17 downto 16) = "10" and rx_data_i(15 downto 0) = x"fcce") then
-         led_rx_i <= '0';
-      end if;
-      
-      if (led_timer_i(20) = '1') or (tx_data_i(17 downto 16) = "10" and tx_data_i(15 downto 0) = x"fcce") then
-         led_tx_i <= '0';
-      end if;
-
-      led_timer_i <= led_timer_i + 1 ;
-      if led_timer_i(20) = '1' then
-         led_timer_i <= (others => '0');
-         last_led_rx_i <= led_rx_i ;
-         last_led_tx_i <= led_tx_i;
-      end if;      
-   end process;
-   
-   LED_OK_OUT <= led_ok_i;
-   LED_RX_OUT <= led_rx_i;
-   LED_TX_OUT <= led_tx_i;
-   
    -- Produce 1us reset pulse for external logic
    PROC_CLK_RESET: process is
       variable counter : unsigned(8 downto 0) := (others => '0');
@@ -671,45 +678,45 @@ begin
          last_rx_serdes_rst_i := rx_serdes_rst_i;
       end process;
       
-      PROC_SENSE_RX_DLM0: process is 
-         variable detected_first_word_v : std_logic := '0';
-      begin
-         wait until rising_edge(rclk_250_i);
-         low_level_rx_see_dlm0 <= '0';
-         
-         if detected_first_word_v = '0' then
-            if rx_data_from_serdes_i = "1" & x"fb" then
-               detected_first_word_v := '1';
-            end if;
-            
-         else
-            detected_first_word_v := '0';
-            if rx_data_from_serdes_i = "001101010" then
-               low_level_rx_see_dlm0 <= '1';
-            end if;
-            
-         end if;
-      end process;
+--       PROC_SENSE_RX_DLM0: process is 
+--          variable detected_first_word_v : std_logic := '0';
+--       begin
+--          wait until rising_edge(rclk_250_i);
+--          low_level_rx_see_dlm0 <= '0';
+--          
+--          if detected_first_word_v = '0' then
+--             if rx_data_from_serdes_i = "1" & x"fb" then
+--                detected_first_word_v := '1';
+--             end if;
+--             
+--          else
+--             detected_first_word_v := '0';
+--             if rx_data_from_serdes_i = "001101010" then
+--                low_level_rx_see_dlm0 <= '1';
+--             end if;
+--             
+--          end if;
+--       end process;
                   
-      PROC_SENSE_TX_DLM0: process is 
-         variable detected_first_word_v : std_logic := '0';
-      begin
-         wait until rising_edge(clk_tx_full_i);
-         low_level_tx_see_dlm0 <= '0';
-         
-         if detected_first_word_v = '0' then
-            if tx_data_to_serdes_i = "1" & x"fb" then
-               detected_first_word_v := '1';
-            end if;
-            
-         else
-            detected_first_word_v := '0';
-            if tx_data_to_serdes_i = "001101010" then
-               low_level_tx_see_dlm0 <= '1';
-            end if;
-            
-         end if;
-      end process;
+--       PROC_SENSE_TX_DLM0: process is 
+--          variable detected_first_word_v : std_logic := '0';
+--       begin
+--          wait until rising_edge(clk_tx_full_i);
+--          low_level_tx_see_dlm0 <= '0';
+--          
+--          if detected_first_word_v = '0' then
+--             if tx_data_to_serdes_i = "1" & x"fb" then
+--                detected_first_word_v := '1';
+--             end if;
+--             
+--          else
+--             detected_first_word_v := '0';
+--             if tx_data_to_serdes_i = "001101010" then
+--                low_level_tx_see_dlm0 <= '1';
+--             end if;
+--             
+--          end if;
+--       end process;
       
       PROC_SENSE_TX_DLM125: process is
       begin
@@ -720,7 +727,33 @@ begin
             low_level_tx_see_dlm0_125 <= '1';
          end if;
       end process;
-	  
+      
+      proc_sense_init_ack: process is 
+      begin
+         wait until rising_edge(clk_125_i);
+         if reset = '1' then
+            stat_init_ack_counter_i <= (others => '0');
+         elsif rx_data_i = "11" & K297 & K283 then 
+            stat_init_ack_counter_i <= stat_init_ack_counter_i + 1;
+         end if;
+      end process;
+      
+	  process is
+      variable rx_v, tx_v : std_logic_vector(17 downto 0);
+	  begin
+      wait until rising_edge(clk_125_i);
+      
+      if reset = '1' or rx_v /= rx_data_i then rx_stab_i <= (others => '0');
+	   else                                     rx_stab_i <= rx_stab_i + 1; end if;
+
+      if reset = '1' or tx_v /= tx_data_i then tx_stab_i <= (others => '0');
+      else                                     tx_stab_i <= tx_stab_i + 1; end if;
+	   
+	   rx_v := rx_data_i;
+	   tx_v := tx_data_i;
+	  end process;
+	   
+	   
 	  PROC_SENSE_DLMS: process begin
 		wait until rising_edge(clk_125_i);
 		
@@ -733,7 +766,6 @@ begin
 
 -- DEBUG_OUT_BEGIN      
       DEBUG_OUT(19 downto  0) <= "00" & tx_data_i(17 downto 0);
-      
       DEBUG_OUT(23 downto 20) <= "0" & tx_pll_lol_i & rx_los_low_i & rx_cdr_lol_i;
 
       DEBUG_OUT(27 downto 24) <= gear_to_fsm_rst_i & barrel_shifter_misaligned_i & SD_PRSNT_N_IN & SD_LOS_IN;
@@ -749,26 +781,55 @@ begin
       
       DEBUG_OUT( 99 downto 96) <= rm_rx_almost_ready_i & rm_rx_rxpcs_ready_i & rm_rx_see_reinit & rm_rx_ebtb_detect_i;
       DEBUG_OUT(103 downto 100) <= wa_position_i(3 downto 0);
-      DEBUG_OUT(107 downto 104) <= "00" & rm_rx_to_gear_reset_i & gear_to_rm_rst_i;
-      
-      DEBUG_OUT(127 downto 108) <= "00" & tx_data_debug_i(17 downto 0);
-      DEBUG_OUT(147 downto 128) <= "00" & rx_data_debug_i(17 downto 0) when rising_edge(clk_125_local);
+      DEBUG_OUT(107 downto 104) <= word_alignment_to_fsm_i & byte_alignment_to_fsm_i & rm_rx_to_gear_reset_i & gear_to_rm_rst_i;
+
+      DEBUG_OUT(123 downto 108) <= tx_stab_i(15 downto 0);
+
+      DEBUG_OUT(139 downto 124) <= rx_stab_i(15 downto 0);
+      DEBUG_OUT(147 downto 140) <= stat_init_ack_counter_i(7 downto 0);
       DEBUG_OUT(179 downto 148) <= stat_last_reconnect_duration_i(31 downto 0);
+
       DEBUG_OUT(195 downto 180) <= stat_reconnect_counter_i(15 downto 0);
       DEBUG_OUT(211 downto 196) <= stat_dlm_counter_i(15 downto 0);
 	   DEBUG_OUT(243 downto 212) <= rm_rx_ebtb_code_err_cntr_i(15 downto 0) & rm_rx_ebtb_disp_err_cntr_i(15 downto 0);
-	  --DEBUG_OUT(255 downto 170) <= (others => '0');
+
+	   DEBUG_OUT(315 downto 244) <= rx_data_sp_i3(17 downto 0) & rx_data_sp_i2(17 downto 0) & rx_data_sp_i1(17 downto 0) & rx_data_sp_i0(17 downto 0);
+	   
+	   DEBUG_OUT(333 downto 316) <= PHY_TXDATA_K_IN(1 downto 0) & PHY_TXDATA_IN(15 downto 0);
+	   
+	   --DEBUG_OUT(255 downto 170) <= (others => '0');
       
 -- DEBUG_OUT_END
+   
+   process is
+   begin
+      wait until rising_edge(rclk_125_i);
+      if rx_data_i /= "10" & x"fcc3" then
+         rx_data_sp_i0 <= rx_data_i;
+         rx_data_sp_i1 <= rx_data_sp_i0;
+         rx_data_sp_i2 <= rx_data_sp_i1;
+         rx_data_sp_i3 <= rx_data_sp_i2;
+      end if;
+   end process;
+      
+      
+--      DEBUG_OUT(127 downto 108) <= "00" & tx_data_debug_i(17 downto 0);
+--      DEBUG_OUT(147 downto 128) <= "00" & rx_data_debug_i(17 downto 0) when rising_edge(clk_125_local);
 
       -- STAT_OP REGISTER
-      STAT_OP(6 downto 0) <= tx_data_to_serdes_i(6 downto 0);
-      STAT_OP( 7) <= low_level_rx_see_dlm0;
-      STAT_OP( 8) <= clk_125_local;
-      STAT_OP( 9) <= rclk_250_i;
-      STAT_OP(10) <= rclk_125_i;
-      STAT_OP(11) <= clk_tx_full_i;
-      STAT_OP(12) <= clk_tx_half_i;
-      STAT_OP(13) <= low_level_tx_see_dlm0;
+-- STAT_OP <= tx_data_i(15 downto 0) when CTRL_OP(9 downto 8) = "01" else 
+--            rx_data_i(15 downto 0) when CTRL_OP(9 downto 8) = "10" else
+--            test_line_i;
+--            
+-- test_line_i <= test_line_i(14 downto 0) & test_line_i(15) when rising_edge(clk_125_local);
+      
+--       STAT_OP(6 downto 0) <= tx_data_to_serdes_i(6 downto 0);
+--       STAT_OP( 7) <= low_level_rx_see_dlm0;
+--       STAT_OP( 8) <= clk_125_local;
+--       STAT_OP( 9) <= rclk_250_i;
+--       STAT_OP(10) <= rclk_125_i;
+--       STAT_OP(11) <= clk_tx_full_i;
+--       STAT_OP(12) <= clk_tx_half_i;
+--       STAT_OP(13) <= low_level_tx_see_dlm0;
    end generate;
 end architecture;
\ No newline at end of file
diff --git a/cbmnet/code/cbmnet_phy_pkg.vhd b/cbmnet/code/cbmnet_phy_pkg.vhd
index 27df297..4a2ef6e 100644
--- a/cbmnet/code/cbmnet_phy_pkg.vhd
+++ b/cbmnet/code/cbmnet_phy_pkg.vhd
@@ -49,7 +49,7 @@ package cbmnet_phy_pkg is
          -- Status and control port
          STAT_OP            : out std_logic_vector (15 downto 0);
          CTRL_OP            : in  std_logic_vector (15 downto 0) := (others => '0');
-         DEBUG_OUT          : out std_logic_vector (255 downto 0) := (others => '0')
+         DEBUG_OUT          : out std_logic_vector (511 downto 0) := (others => '0')
       );
    end component;
    
diff --git a/cbmnet/code/cbmnet_phy_rx_gear.vhd b/cbmnet/code/cbmnet_phy_rx_gear.vhd
index 92dd294..4e67460 100644
--- a/cbmnet/code/cbmnet_phy_rx_gear.vhd
+++ b/cbmnet/code/cbmnet_phy_rx_gear.vhd
@@ -1,192 +1,198 @@
-LIBRARY IEEE;
-   USE IEEE.std_logic_1164.ALL;
-   USE IEEE.numeric_std.all;
-
-library work;
-   use work.trb_net_std.all;
---   use work.trb_net_components.all;
---   use work.med_sync_define.all;
-   use work.cbmnet_interface_pkg.all;
-   use work.cbmnet_phy_pkg.all;
-
-entity CBMNET_PHY_RX_GEAR is
-   generic(
-      IS_SYNC_SLAVE   : integer := c_NO       --select slave mode
-   );
-   port (
-   -- SERDES PORT
-      CLK_250_IN  : in std_logic;
-      PCS_READY_IN: in std_logic;
-      SERDES_RESET_OUT : out std_logic;
-      DATA_IN     : in  std_logic_vector( 8 downto 0);
-
-   -- RM PORT
-      RM_RESET_IN : in std_logic;
-      CLK_125_OUT : out std_logic;
-      RESET_OUT   : out std_logic;
-      DATA_OUT    : out std_logic_vector(17 downto 0);
-      
-   -- DEBUG
-      DEBUG_OUT   : out std_logic_vector(31 downto 0) := (others => '0')
-   );
-end entity;
-
-architecture CBMNET_PHY_RX_GEAR_ARCH of CBMNET_PHY_RX_GEAR is
-   type FSM_STATES_T is (FSM_START, FSM_WAIT_FOR_LOCK, FSM_RESET, FSM_LOCKED);
-   signal fsm_i : FSM_STATES_T;
-   signal fsm_state_i : std_logic_vector(3 downto 0);
-   
+LIBRARY IEEE;
+   USE IEEE.std_logic_1164.ALL;
+   USE IEEE.numeric_std.all;
+
+library work;
+   use work.trb_net_std.all;
+--   use work.trb_net_components.all;
+--   use work.med_sync_define.all;
+   use work.cbmnet_interface_pkg.all;
+   use work.cbmnet_phy_pkg.all;
+
+entity CBMNET_PHY_RX_GEAR is
+   generic(
+      IS_SYNC_SLAVE   : integer := c_NO       --select slave mode
+   );
+   port (
+   -- SERDES PORT
+      CLK_250_IN  : in std_logic;
+      PCS_READY_IN: in std_logic;
+      SERDES_RESET_OUT : out std_logic;
+      DATA_IN     : in  std_logic_vector( 8 downto 0);
+
+   -- RM PORT
+      RM_RESET_IN : in std_logic;
+      CLK_125_OUT : out std_logic;
+      RESET_OUT   : out std_logic;
+      DATA_OUT    : out std_logic_vector(17 downto 0);
+      
+   -- DEBUG
+      DEBUG_OUT   : out std_logic_vector(31 downto 0) := (others => '0')
+   );
+end entity;
+
+architecture CBMNET_PHY_RX_GEAR_ARCH of CBMNET_PHY_RX_GEAR is
+   attribute HGROUP : string;
+   attribute HGROUP of CBMNET_PHY_RX_GEAR_ARCH : architecture  is "cbmnet_phy_rx_gear";
+
+
+   type FSM_STATES_T is (FSM_START, FSM_WAIT_FOR_LOCK, FSM_RESET, FSM_LOCKED);
+   signal fsm_i : FSM_STATES_T;
+   signal fsm_state_i : std_logic_vector(3 downto 0);
+   
    signal delay_clock_i : std_logic;
    
-   signal indi_alignment_i    : std_logic;
-   signal indi_misalignment_i : std_logic;
-   
-   signal data_delay_i   : std_logic_vector(8 downto 0);
-   signal data_out_buf_i : std_logic_vector(17 downto 0);
-   signal clk_125_i : std_logic;
-   
-   signal reset_timer_i : std_logic;
-   signal timeout_i : std_logic;
-   
+   signal indi_alignment_i    : std_logic;
+   signal indi_misalignment_i : std_logic;
+   
+   signal data_delay_i   : std_logic_vector(8 downto 0);
+   signal data_out_buf_i : std_logic_vector(17 downto 0);
+   signal clk_125_i : std_logic;
+   
+   signal reset_timer_i : std_logic;
+   signal timeout_i : std_logic;
+   
    signal data_in_buf_i : std_logic_vector( 8 downto 0); 
    
    
-   signal delay_clock_buf_i : std_logic;
-   signal delay_clock_buf1_i : std_logic;
-   signal last_delay_clock_i : std_logic := '0';
-   signal word_idx_i : std_logic := '0';   
-begin
-   data_in_buf_i <= DATA_IN when rising_edge(CLK_250_IN);
-
--- FSM sync part
-   process is begin
-      wait until rising_edge(clk_125_i);
-      
-      if PCS_READY_IN = '0' then
-         fsm_i <= FSM_START;
-         
-         RESET_OUT <= '1';
-         delay_clock_i <= '0';
-         fsm_state_i <= x"0";
-         
-      elsif rising_edge(clk_125_i) then
-         SERDES_RESET_OUT <= '0';
-         RESET_OUT <= '1';
-         reset_timer_i <= '0';
-         delay_clock_i <= '0';
-         
-         case (fsm_i) is
-            when FSM_START =>
-               fsm_state_i <= x"0";
-               reset_timer_i <= '1';
-               fsm_i <= FSM_WAIT_FOR_LOCK;
-               
-            when FSM_WAIT_FOR_LOCK =>
-               fsm_state_i <= x"1";
-               if indi_alignment_i = '1' then
-                  -- already correctly aligned, so just fix current state
-                  fsm_i <= FSM_LOCKED;
-                  
-               elsif indi_misalignment_i = '1' then
-                  -- we're off by one word. just wait a single frame
-                  delay_clock_i <= '1';
-   --               fsm_i <= FSM_LOCKED;
-               
-               elsif timeout_i = '1' then
-                  fsm_i <= FSM_RESET;
-                  
-               end if;
-
-            when FSM_LOCKED =>
-               fsm_state_i <= x"2";
-               RESET_OUT <= '0';
-               
-               if RM_RESET_IN = '1' then
-                  fsm_i <= FSM_RESET;
-               
-               elsif indi_misalignment_i = '1' then
-                  -- in this state we should already have a stable and correct lock. 
-                  -- if we, however, detect a missalignment, something is terribly wrong.
-                  -- in this case, will perform a resychronisation
-                  
-                  fsm_i <= FSM_RESET;
-               end if;
-            
-            
-            when FSM_RESET =>
-               fsm_state_i <= x"3";
-               SERDES_RESET_OUT <= '1';
-            
-         end case;
-      end if;
-   end process;
-   
--- Timeout (approx. 2ms)
-   proc_timeout: process is 
-      variable timer_v : unsigned(19 downto 0) := (others => '0');
-      variable idx : integer := 18;
-   begin
-      wait until rising_edge(clk_125_i);
-      
-      if IS_SYNC_SLAVE = 0 then
-         idx := timer_v'high;
-      end if;
-      
-      if reset_timer_i = '1' then
-         timer_v := TO_UNSIGNED(0, timer_v'length);
-         
-      elsif timer_v(idx) = '0' then
-         timer_v := timer_v + TO_UNSIGNED(1,1);
-         
-      end if;
-
-      timeout_i <= timer_v(idx);
-   end process;
-
+   signal delay_clock_buf_i : std_logic;
+   signal delay_clock_buf1_i : std_logic;
+   signal last_delay_clock_i : std_logic := '0';
+   signal word_idx_i : std_logic := '0';   
+begin
+   data_in_buf_i <= DATA_IN when rising_edge(CLK_250_IN);
+
+-- FSM sync part
+   process is begin
+      wait until rising_edge(clk_125_i);
+      
+      if PCS_READY_IN = '0' then
+         fsm_i <= FSM_START;
+         
+         RESET_OUT <= '1';
+         delay_clock_i <= '0';
+         fsm_state_i <= x"0";
+         
+      elsif rising_edge(clk_125_i) then
+         SERDES_RESET_OUT <= '0';
+         RESET_OUT <= '1';
+         reset_timer_i <= '0';
+         delay_clock_i <= '0';
+         
+         case (fsm_i) is
+            when FSM_START =>
+               fsm_state_i <= x"0";
+               reset_timer_i <= '1';
+               fsm_i <= FSM_WAIT_FOR_LOCK;
+               
+            when FSM_WAIT_FOR_LOCK =>
+               fsm_state_i <= x"1";
+               if indi_alignment_i = '1' then
+                  -- already correctly aligned, so just fix current state
+                  fsm_i <= FSM_LOCKED;
+                  
+               elsif indi_misalignment_i = '1' then
+                  -- we're off by one word. just wait a single frame
+                  delay_clock_i <= '1';
+   --               fsm_i <= FSM_LOCKED;
+               
+               elsif timeout_i = '1' then
+                  fsm_i <= FSM_RESET;
+                  
+               end if;
+
+            when FSM_LOCKED =>
+               fsm_state_i <= x"2";
+               RESET_OUT <= '0';
+               
+               if RM_RESET_IN = '1' then
+                  fsm_i <= FSM_RESET;
+               
+               elsif indi_misalignment_i = '1' then
+                  -- in this state we should already have a stable and correct lock. 
+                  -- if we, however, detect a missalignment, something is terribly wrong.
+                  -- in this case, will perform a resychronisation
+                  
+                  fsm_i <= FSM_RESET;
+               end if;
+            
+            
+            when FSM_RESET =>
+               fsm_state_i <= x"3";
+               SERDES_RESET_OUT <= '1';
+            
+         end case;
+      end if;
+   end process;
+   
+-- Timeout (approx. 2ms)
+   proc_timeout: process is 
+      variable timer_v : unsigned(19 downto 0) := (others => '0');
+      variable idx : integer := 18;
+   begin
+      wait until rising_edge(clk_125_i);
+      
+      if IS_SYNC_SLAVE = 0 then
+         idx := timer_v'high;
+      end if;
+      
+      if reset_timer_i = '1' then
+         timer_v := TO_UNSIGNED(0, timer_v'length);
+         
+      elsif timer_v(idx) = '0' then
+         timer_v := timer_v + TO_UNSIGNED(1,1);
+         
+      end if;
+
+      timeout_i <= timer_v(idx);
+   end process;
+
 -- Implement the 2:1 gearing and clock down-sampling
-   delay_clock_buf1_i <= delay_clock_i when rising_edge(CLK_250_IN);
-   delay_clock_buf_i <= delay_clock_buf1_i when rising_edge(CLK_250_IN);
 
+   delay_clock_buf1_i <= delay_clock_i when rising_edge(CLK_250_IN);
+   delay_clock_buf_i <= delay_clock_buf1_i when rising_edge(CLK_250_IN);
+ 
+
+   proc_ctrl_gear: process
+   begin
+      wait until rising_edge(CLK_250_IN);
+
+      if not (delay_clock_buf_i = '1' and last_delay_clock_i = '0') then
+         word_idx_i <= not word_idx_i;
+      end if;
+      
+      last_delay_clock_i <= delay_clock_buf_i;
+   end process;
+   
+   proc_gear: process
+   begin
+      wait until rising_edge(CLK_250_IN);
+
+      if word_idx_i = '0' then
+         data_delay_i <= data_in_buf_i;
+         clk_125_i <= '1';
+      else
+--         data_out_buf_i <= data_delay_i(8) & data_in_buf_i(8) & data_delay_i(7 downto 0) & data_in_buf_i(7 downto 0);
+         data_out_buf_i <=  data_in_buf_i(8) & data_delay_i(8)  & data_in_buf_i(7 downto 0) & data_delay_i(7 downto 0);
+         clk_125_i <= '0';
+      end if;      
 
-   proc_ctrl_gear: process
-   begin
-      wait until rising_edge(CLK_250_IN);
-
-      if not (delay_clock_buf_i = '1' and last_delay_clock_i = '0') then
-         word_idx_i <= not word_idx_i;
-      end if;
-      
-      last_delay_clock_i <= delay_clock_buf_i;
-   end process;
-   
-   proc_gear: process
-   begin
-      wait until rising_edge(CLK_250_IN);
-
-      if word_idx_i = '0' then
-         data_delay_i <= data_in_buf_i;
-         clk_125_i <= '0';
-      else
-         data_out_buf_i <= data_delay_i(8) & data_in_buf_i(8) & data_delay_i(7 downto 0) & data_in_buf_i(7 downto 0);
-         clk_125_i <= '1';
-      end if;      
-
    end process;
    
-   
-   
-   DATA_OUT <= data_out_buf_i;
-   CLK_125_OUT <= clk_125_i;
-   
-   DEBUG_OUT(3 downto 0) <= STD_LOGIC_VECTOR(fsm_state_i);
-   DEBUG_OUT(4) <= delay_clock_i;
-   DEBUG_OUT(5) <= indi_alignment_i;
-   DEBUG_OUT(6) <= indi_misalignment_i;
-   
--- Detect Indications for correct or wrong alignment   
-   indi_alignment_i <= '1' when data_out_buf_i(17 downto 16) = "01" and data_out_buf_i(15 downto 8) = x"00" and
-      (data_out_buf_i(7 downto 0) = CBMNET_READY_CHAR0 or data_out_buf_i(7 downto 0) = CBMNET_READY_CHAR1 or data_out_buf_i(7 downto 0) = CBMNET_ALIGN_CHAR) else '0';
-   
-   indi_misalignment_i <= '1' when data_out_buf_i(17 downto 16) = "10" and data_out_buf_i(7 downto 0) = x"00" and
-      (data_out_buf_i(15 downto 8) = CBMNET_READY_CHAR0 or data_out_buf_i(15 downto 8) = CBMNET_READY_CHAR1 or data_out_buf_i(15 downto 8) = CBMNET_ALIGN_CHAR) else '0';
-   
+   
+   
+   DATA_OUT <= data_out_buf_i when rising_edge(clk_125_i);
+   CLK_125_OUT <= clk_125_i;
+   
+   DEBUG_OUT(3 downto 0) <= STD_LOGIC_VECTOR(fsm_state_i);
+   DEBUG_OUT(4) <= delay_clock_i;
+   DEBUG_OUT(5) <= indi_alignment_i;
+   DEBUG_OUT(6) <= indi_misalignment_i;
+   
+-- Detect Indications for correct or wrong alignment   
+   indi_alignment_i <= '1' when data_out_buf_i(17 downto 16) = "01" and data_out_buf_i(15 downto 8) = x"00" and
+      (data_out_buf_i(7 downto 0) = CBMNET_READY_CHAR0 or data_out_buf_i(7 downto 0) = CBMNET_READY_CHAR1 or data_out_buf_i(7 downto 0) = CBMNET_ALIGN_CHAR) else '0';
+   
+   indi_misalignment_i <= '1' when data_out_buf_i(17 downto 16) = "10" and data_out_buf_i(7 downto 0) = x"00" and
+      (data_out_buf_i(15 downto 8) = CBMNET_READY_CHAR0 or data_out_buf_i(15 downto 8) = CBMNET_READY_CHAR1 or data_out_buf_i(15 downto 8) = CBMNET_ALIGN_CHAR) else '0';
+   
 end architecture CBMNET_PHY_RX_GEAR_ARCH;  
\ No newline at end of file
diff --git a/cbmnet/code/cbmnet_phy_tx_gear.vhd b/cbmnet/code/cbmnet_phy_tx_gear.vhd
index 13cd151..a552f69 100644
--- a/cbmnet/code/cbmnet_phy_tx_gear.vhd
+++ b/cbmnet/code/cbmnet_phy_tx_gear.vhd
@@ -32,10 +32,15 @@ entity CBMNET_PHY_TX_GEAR is
 end entity;
 
 architecture CBMNET_PHY_TX_GEAR_ARCH of CBMNET_PHY_TX_GEAR is
+   attribute HGROUP : string;
+   attribute HGROUP of CBMNET_PHY_TX_GEAR_ARCH : architecture  is "cbmnet_phy_tx_gear";
+
    type   FSM_STATES is (FSM_HIGH, FSM_LOW);
    signal fsm_i : FSM_STATES;
    
    signal data_in_buf125_i : std_logic_vector(17 downto 0);
+   signal data_in_buf250_i : std_logic_vector(17 downto 0);
+   
    signal low_data_i : std_logic_vector(8 downto 0);
    
    signal clk_125_xfer_i     : std_logic := '0';
@@ -51,6 +56,8 @@ begin
          delay_counter_i <= TO_UNSIGNED(0,16);
       end if;
       
+      data_in_buf250_i <= data_in_buf125_i;
+      
       clk_125_xfer_buf_i <= clk_125_xfer_i;
       clk_125_xfer_del_i <= clk_125_xfer_buf_i;
       CLK_125_OUT <= '0';
@@ -59,8 +66,8 @@ begin
          when FSM_HIGH =>
             CLK_125_OUT <= '1';
             
-            DATA_OUT   <= data_in_buf125_i(17) & data_in_buf125_i(15 downto 8);
-            low_data_i <= data_in_buf125_i(16) & data_in_buf125_i( 7 downto 0);
+            low_data_i   <= data_in_buf250_i(17) & data_in_buf250_i(15 downto 8);
+            DATA_OUT <= data_in_buf250_i(16) & data_in_buf250_i( 7 downto 0);
             fsm_i <= FSM_LOW;
 
             if clk_125_xfer_buf_i /= clk_125_xfer_del_i and ALLOW_RELOCK_IN = '1' then
diff --git a/cbmnet/compile_periph_frankfurt.pl b/cbmnet/compile_periph_frankfurt.pl
index d4b145c..d6ae4cf 100755
--- a/cbmnet/compile_periph_frankfurt.pl
+++ b/cbmnet/compile_periph_frankfurt.pl
@@ -19,8 +19,8 @@ my $lattice_path                 = '/d/jspc29/lattice/diamond/2.2_x64/';
 #my $synplify_path                = '/d/jspc29/lattice/synplify/F-2012.03-SP1/';
 my $synplify_path                = '/d/jspc29/lattice/synplify/G-2012.09-SP1/';
 
-#my $lattice_path                 = '/d/jspc29/lattice/diamond/3.0_x64';
 #my $synplify_path              = '/d/jspc29/lattice/synplify/I-2013.09-SP1/'; 
+#my $lattice_path                 = '/d/jspc29/lattice/diamond/3.1/';
 ###################################################################################
 
 my $btype = 'slave';
diff --git a/cbmnet/test/info.pl b/cbmnet/test/info.pl
index a3e25c6..c6d4019 100755
--- a/cbmnet/test/info.pl
+++ b/cbmnet/test/info.pl
@@ -60,7 +60,7 @@ sub interpretLine {
 sub readRegs {
    my $endpoint = shift;
    my $length = shift;
-   my $firstReg = 0xa008;
+   my $firstReg = 0xa020;
    my $res = `trbcmd rm $endpoint $firstReg $length 0`;
    
    my $reg = 0;
@@ -114,7 +114,7 @@ sub show8b10b {
          253, "K.29.7",
          254, "K.30.7");
    
-      return $codes{$data};
+      return exists $codes{$data} ? $codes{$data} : "E.EE.E";
    } else {
       return sprintf("D.%02d.%d", $data & 0x1f, ($data >> 5) & 0x7);
    }
@@ -134,7 +134,7 @@ while (1) {
    my @results = ();
 
    for my $i (1 .. 1) {
-      my $reg = readRegs 0x8000 + $i, 8;
+      my $reg = readRegs 0x8000 + $i, 0x10;
       my @slices = ();
       for my $def (@defs) {
          my $idx = $def->[1];
@@ -169,7 +169,7 @@ while (1) {
    @old_results = @results;
    
    
-   sleep 1;
-print $first_one ? `reset` : chr(27) . "[1;1H";
+sleep 1;
+print $first_one ? `clear` : chr(27) . "[1;1H";
 $first_one = 0;
 }
diff --git a/cbmnet/test/reboot b/cbmnet/test/reboot
index 1889888..a8cebd0 100755
--- a/cbmnet/test/reboot
+++ b/cbmnet/test/reboot
@@ -1,4 +1,5 @@
 #!/bin/bash
-rebootfpga.sh 0x8000
+#rebootfpga.sh 0x8000
 rebootfpga.sh 0x8001
+sleep 1
 test/start
\ No newline at end of file
diff --git a/cbmnet/test/start b/cbmnet/test/start
index f27f1a2..8947198 100755
--- a/cbmnet/test/start
+++ b/cbmnet/test/start
@@ -10,9 +10,9 @@ system "trbcmd i 0xffff";
 
 print "Checks\n";
 my $ver_reg = "0xa006";
-print "\nWRONG VERSION IN MASTER\n" unless(`trbcmd r 0x8000 $ver_reg` =~ m/0x00000000/);
+#print "\nWRONG VERSION IN MASTER\n" unless(`trbcmd r 0x8000 $ver_reg` =~ m/0x00000000/);
 print "\nWRONG VERSION IN SLAVE\n"  unless(`trbcmd r 0x8001 $ver_reg` =~ m/0x00000001/);
 
-system "compiletime.pl 0x8000";
+#system "compiletime.pl 0x8000";
 system "compiletime.pl 0x8001";
 
diff --git a/cbmnet/trb3_periph_cbmnet.prj b/cbmnet/trb3_periph_cbmnet.prj
index f6ad15a..99c84ce 100644
--- a/cbmnet/trb3_periph_cbmnet.prj
+++ b/cbmnet/trb3_periph_cbmnet.prj
@@ -41,6 +41,8 @@ add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/pcs_init/cn_tx_pcs_init
 add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/pcs_init/cn_tx_pcs_wrapper.v"
 add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/pcs_init/cn_async_input_sync.v"
 
+add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/dlm_reflect.v"
+
 
 add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_top.v"
 add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_arbiter_fsm.v"
diff --git a/cbmnet/trb3_periph_cbmnet.vhd b/cbmnet/trb3_periph_cbmnet.vhd
index 6105663..78e5513 100755
--- a/cbmnet/trb3_periph_cbmnet.vhd
+++ b/cbmnet/trb3_periph_cbmnet.vhd
@@ -280,8 +280,8 @@ architecture trb3_periph_arch of trb3_periph_cbmnet is
    signal phy_stat_op,    phy_ctrl_op    : std_logic_vector(15 downto 0) := (others => '0');
    signal phy_stat_debug, phy_ctrl_debug : std_logic_vector(63 downto 0) := (others => '0');
    
-   signal phy_debug_i : std_logic_vector (255 downto 0) := (others => '0');
-   signal phy_debug_i_buf : std_logic_vector (255 downto 0);
+   signal phy_debug_i : std_logic_vector (511 downto 0) := (others => '0');
+   signal phy_debug_i_buf : std_logic_vector (511 downto 0);
    
 
 -- Link Tester
@@ -302,15 +302,15 @@ architecture trb3_periph_arch of trb3_periph_cbmnet is
    
    signal dummy : std_logic;
    
-   type SEND_FSM_T is (IDLE, WAITc, SEND);
+   type SEND_FSM_T is (START, SEND_HEADER, SEND_LENGTH, SEND_DATA, SEND_FOOTER, AFTER_SEND_WAIT);
    signal send_fsm_i : SEND_FSM_T;
-   signal send_wait_counter_i : unsigned(16 downto 0);
-   signal send_pack_counter_i : unsigned( 4 downto 0);
-   
-   signal send_num_pack_counter_i : unsigned(15 downto 0);
-   
+   signal send_length_i : unsigned(4 downto 0);
+   signal send_num_pack_counter_i : unsigned(15 downto 0); 
    signal send_enabled_i : std_logic := '0';
    
+   signal send_wait_counter_i : std_logic_vector(31 downto 0);
+   signal send_wait_threshold_i : std_logic_vector(31 downto 0);
+   
    signal dlm_counter_i : unsigned(31 downto 0);
    signal dlm_glob_counter_i : unsigned(31 downto 0);
    
@@ -411,27 +411,28 @@ begin
       DEBUG_OUT          => phy_debug_i
    );
 
+   TEST_LINE <= phy_stat_op;
    
    SFP_RATESEL   <= (others => '1');
    
    --TEST_LINE(1 downto 0) <= cbm_dlm2send_va & cbm_dlm_rec_va;
 
-   process is
-      variable counter_v : unsigned(20 downto 0); 
-   begin
-      wait until rising_edge(rclk_125_i);
-      counter_v := counter_v + to_unsigned(1,1);
-      cbm_dlm2send_va <= '0';
-      if counter_v = 0 then
-         cbm_dlm2send_va <= '1';
-      end if;
-   end process;
-   
+--    process is
+--       variable counter_v : unsigned(20 downto 0); 
+--    begin
+--       wait until rising_edge(rclk_125_i);
+--       counter_v := counter_v + to_unsigned(1,1);
+--       cbm_dlm2send_va <= '0';
+--       if counter_v = 0 then
+--          cbm_dlm2send_va <= '1';
+--       end if;
+--    end process;
+--    
    
 -- cbm_data2link <= "00" & x"dead";
    THE_CBM_ENDPOINT: lp_top 
    generic map (
-      NUM_LANES => NUM_LANES,
+      NUM_LANES => 1,
       TX_SLAVE  => 1
    )
    port map (
@@ -535,46 +536,72 @@ begin
    cbm_retrans_cntr_clr_3       <= reset_i;
    cbm_retrans_error_cntr_clr_3 <= reset_i;
    
+   THE_DLM_REFLECT: dlm_reflect port map (
+      clk            => rclk_125_i,       -- in std_logic;
+      res_n          => cbm_res_n,        -- in std_logic;
+      dlm_rec_in     => cbm_dlm_rec_type, -- in std_logic_vector(3 downto 0);
+      dlm_rec_va_in  => cbm_dlm_rec_va,   -- in std_logic;
+      dlm_rec_out    => open,             -- out std_logic_vector(3 downto 0);
+      dlm_rec_va_out => open,             -- out std_logic;
+      dlm2send_va    => cbm_dlm2send_va,  -- out std_logic;
+      dlm2send       => cbm_dlm2send      -- out std_logic_vector(3 downto 0)
+   );
+   
+   
    PROC_DATA_SEND: process begin
       wait until rising_edge(rclk_125_i);
       
-      send_wait_counter_i <= send_wait_counter_i + TO_UNSIGNED(1,1);
-      
-      if cbm_data2send_stop = "0" then
-         send_pack_counter_i <= send_pack_counter_i + TO_UNSIGNED(1,1);
-      end if;
-
       cbm_data2send <= (others => '0');
-      cbm_data2send(send_pack_counter_i'HIGH downto 0)     <= STD_LOGIC_VECTOR(send_pack_counter_i);
-      cbm_data2send(send_pack_counter_i'HIGH + 9 downto 9) <= STD_LOGIC_VECTOR(send_pack_counter_i);
-
       cbm_data2send_start <= "0";
       cbm_data2send_end <= "0";
 
       if reset_i = '1' or send_enabled_i = '0' then
-         send_fsm_i <= IDLE;
+         send_fsm_i <= START;
          send_num_pack_counter_i <= (others => '0');
          
       else
          case(send_fsm_i) is
-            when IDLE =>
+            when START =>
                if cbm_link_active='1' and cbm_data2send_stop = "0" then
-                  send_fsm_i <= WAITc;
-                  send_wait_counter_i <= (others => '0');
-                  send_num_pack_counter_i <= send_num_pack_counter_i + TO_UNSIGNED(1, 1);
+                  send_fsm_i <= SEND_HEADER;
+                  send_num_pack_counter_i <= send_num_pack_counter_i + 1;
+                  send_length_i <= "1" & send_num_pack_counter_i(3 downto 0);
                end if;
+            
+            when SEND_HEADER =>
+               cbm_data2send <= x"f123";
+               cbm_data2send_start <= "1";
+               send_fsm_i <= SEND_LENGTH;
+            
+            when SEND_LENGTH =>
+               cbm_data2send(send_length_i'range) <= send_length_i;
+               send_fsm_i <= SEND_DATA;
                
-            when WAITc =>
-               if send_wait_counter_i(send_pack_counter_i'HIGH) = '1' then
-                  send_fsm_i <= SEND;
-                  cbm_data2send_start <= "1";
+            when SEND_DATA =>
+               send_length_i <= send_length_i - 1;
+               cbm_data2send(15 downto 8) <= "0" & std_logic_vector(send_length_i(2 downto 0)) & std_logic_vector(send_length_i(3 downto 0));
+               cbm_data2send(send_length_i'high + 0 downto 0) <= send_length_i;
+               
+               if send_length_i = TO_UNSIGNED(1, send_length_i'length) then
+                  send_fsm_i <= SEND_FOOTER;
                end if;
                
-            when SEND =>
-               if send_wait_counter_i(send_pack_counter_i'HIGH) = '1' then
-                  cbm_data2send_end <= "1";
-                  send_fsm_i <= IDLE;
+            when SEND_FOOTER =>
+               cbm_data2send <= x"f321";
+               cbm_data2send_end <= "1";
+               
+               send_wait_counter_i <= (others => '0');
+               send_fsm_i <= AFTER_SEND_WAIT;
+
+            when AFTER_SEND_WAIT =>
+               send_wait_counter_i <= STD_LOGIC_VECTOR( UNSIGNED(send_wait_counter_i) + 1 );
+               if send_wait_counter_i = send_wait_threshold_i then
+                  send_fsm_i <= START;
                end if;
+               
+            when others =>
+               send_fsm_i <= START;
+               
          end case;
       end if;
    end process;
@@ -620,17 +647,26 @@ begin
          when 16#5# => debug_data_out <= phy_ctrl_debug(63 downto 32);
          when 16#6# => debug_data_out <= STD_LOGIC_VECTOR(TO_UNSIGNED(CBM_FEE_MODE, 32));
          
-         when 16#8# => debug_data_out <= phy_debug_i_buf(31+32*0 downto 32*0);
-         when 16#9# => debug_data_out <= phy_debug_i_buf(31+32*1 downto 32*1);
-         when 16#a# => debug_data_out <= phy_debug_i_buf(31+32*2 downto 32*2);
-         when 16#b# => debug_data_out <= phy_debug_i_buf(31+32*3 downto 32*3);         
-         when 16#c# => debug_data_out <= phy_debug_i_buf(31+32*4 downto 32*4);
-         when 16#d# => debug_data_out <= phy_debug_i_buf(31+32*5 downto 32*5);
-         when 16#e# => debug_data_out <= phy_debug_i_buf(31+32*6 downto 32*6);
-         when 16#f# => debug_data_out <= phy_debug_i_buf(31+32*7 downto 32*7);  
+         when 16#20# => debug_data_out <= phy_debug_i_buf(31+32*0 downto 32*0);
+         when 16#21# => debug_data_out <= phy_debug_i_buf(31+32*1 downto 32*1);
+         when 16#22# => debug_data_out <= phy_debug_i_buf(31+32*2 downto 32*2);
+         when 16#23# => debug_data_out <= phy_debug_i_buf(31+32*3 downto 32*3);         
+         when 16#24# => debug_data_out <= phy_debug_i_buf(31+32*4 downto 32*4);
+         when 16#25# => debug_data_out <= phy_debug_i_buf(31+32*5 downto 32*5);
+         when 16#26# => debug_data_out <= phy_debug_i_buf(31+32*6 downto 32*6);
+         when 16#27# => debug_data_out <= phy_debug_i_buf(31+32*7 downto 32*7);  
+         when 16#28# => debug_data_out <= phy_debug_i_buf(31+32*8 downto 32*8);
+         when 16#29# => debug_data_out <= phy_debug_i_buf(31+32*9 downto 32*9);
+         when 16#2a# => debug_data_out <= phy_debug_i_buf(31+32*10 downto 32*10);
+         when 16#2b# => debug_data_out <= phy_debug_i_buf(31+32*11 downto 32*11);         
+         when 16#2c# => debug_data_out <= phy_debug_i_buf(31+32*12 downto 32*12);
+         when 16#2d# => debug_data_out <= phy_debug_i_buf(31+32*13 downto 32*13);
+         when 16#2e# => debug_data_out <= phy_debug_i_buf(31+32*14 downto 32*14);
+         when 16#2f# => debug_data_out <= phy_debug_i_buf(31+32*15 downto 32*15);  
+         
          
---         when 16#10# => debug_data_out <= link_tester_stat;
---        when 16#11# => debug_data_out <= link_tester_ctrl;
+         when 16#10# => debug_data_out <= send_wait_threshold_i;
+         when 16#11# => debug_data_out(20 downto 0) <= cbm_res_n & "00" & cbm_data_from_link;
          
          when 16#12# => debug_data_out <= STD_LOGIC_VECTOR(dlm_counter_i);
          when 16#13# => debug_data_out <= STD_LOGIC_VECTOR(dlm_glob_counter_i);
@@ -657,12 +693,12 @@ begin
             when 16#1# => phy_ctrl_op <= debug_data_in(15 downto 0);
             when 16#4# => phy_ctrl_debug(31 downto  0) <= debug_data_in;
             when 16#5# => phy_ctrl_debug(63 downto 32) <= debug_data_in;
-            
+            when 16#10# => send_wait_threshold_i <= debug_data_in;
             when 16#14# => 
 				send_enabled_i <= debug_data_in(18);
 				cbm_debug_overrides_i <= debug_data_in(21 downto 20);
             
---            when 16#11# => link_tester_ctrl <= debug_data_in;   
+
             when others => debug_ack <= '0';
          end case;
       end if;
@@ -1012,12 +1048,4 @@ begin
 --   end generate;
 
 
------- DUMMY to check integrity of TEST_LINE connection
---    process is 
---       variable test_line_v : std_logic_vector(15 downto 0) := x"0001";
---    begin
---       wait until rising_edge(rclk_125_i);
---       test_line_v := test_line_v(14 downto 0) & test_line_v(15);
---       TEST_LINE <= test_line_v;
---    end process;
 end architecture;
\ No newline at end of file
diff --git a/cbmnet/trb3_periph_cbmnet_constraints.lpf b/cbmnet/trb3_periph_cbmnet_constraints.lpf
index 8c7b738..e4d52a5 100644
--- a/cbmnet/trb3_periph_cbmnet_constraints.lpf
+++ b/cbmnet/trb3_periph_cbmnet_constraints.lpf
@@ -36,9 +36,25 @@ LOCATE COMP   "THE_CBM_PHY/THE_SERDES/PCSD_INST" SITE "PCSB" ;
 REGION "CBM_PHY" "R102C49D" 13 25;
 LOCATE UGROUP "THE_CBM_PHY/cbmnet_phy_group" REGION "CBM_PHY";
 
+REGION "CBM_PHY_RX_GEAR" "R102C50D" 13 15;
+LOCATE UGROUP "THE_CBM_PHY/THE_RX_GEAR/cbmnet_phy_rx_gear" REGION "CBM_PHY_RX_GEAR";
+
+REGION "CBM_PHY_TX_GEAR" "R102C50D" 13 15;
+LOCATE UGROUP "THE_CBM_PHY/THE_TX_GEAR/cbmnet_phy_tx_gear" REGION "CBM_PHY_TX_GEAR";
+
+
 
 #################################################################
 # Relax some of the timing constraints
 #################################################################
 MULTICYCLE TO CELL "THE_MEDIA_DOWNLINK/SCI_DATA_OUT*" 50 ns;
-MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;
\ No newline at end of file
+MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;
+
+FREQUENCY NET "rclk_125_i" 125.000000 MHz ;
+FREQUENCY NET "phy_stat_op[11]" 250.000000 MHz ;
+FREQUENCY PORT "CLK_GPLL_LEFT" 200.000000 MHz ;
+FREQUENCY NET "clk_200_i" 200.000000 MHz ;
+FREQUENCY NET "clk_100_i_c" 100.000000 MHz ;
+FREQUENCY NET "CLK_RX_FULL_OUT" 250.000000 MHz ;
+
+MULTICYCLE FROM CLKNET "CLK_RX_FULL_OUT" TO CLKNET "rclk_125_i" 2.000000 X_DEST ;
\ No newline at end of file