From: hadeshyp Date: Wed, 27 Mar 2013 17:22:36 +0000 (+0000) Subject: *** empty log message *** X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=a66f3fc9a507ec40885ad35d8cc9b0de5f0dd091;p=trb3.git *** empty log message *** --- diff --git a/base/cores/dqsinput1x4.ipx b/base/cores/dqsinput1x4.ipx new file mode 100644 index 0000000..7b9f89c --- /dev/null +++ b/base/cores/dqsinput1x4.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/base/cores/dqsinput1x4.lpc b/base/cores/dqsinput1x4.lpc new file mode 100644 index 0000000..7a10cfc --- /dev/null +++ b/base/cores/dqsinput1x4.lpc @@ -0,0 +1,60 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN672C +SpeedGrade=8 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=DDR_GENERIC +CoreRevision=5.3 +ModuleName=dqsinput1x4 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=03/27/2013 +Time=18:21:05 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +mode=Receive +io_type=LVDS25 +num_int=2 +width=5 +freq_in=120 +bandwidth=1920 +aligned=Centered +pre-configuration=DISABLED +mode2=Receive +io_type2=LVDS25 +freq_in2=192 +gear=2x +aligned2=Centered +num_int2=1 +width2=5 +Interface=GDDRX2_RX.ECLK.Centered +Delay=Fixed +Number= +dqs1= +dqs2= +dqs3= +dqs4= +dqs5= +dqs6= +dqs7= +dqs8= +val= +Phase=TRDLLB/DLLDELB +Divider=CLKDIVB +Multiplier=2 +PllFreq=96 diff --git a/base/cores/dqsinput1x4.vhd b/base/cores/dqsinput1x4.vhd new file mode 100644 index 0000000..dd3fbb9 --- /dev/null +++ b/base/cores/dqsinput1x4.vhd @@ -0,0 +1,210 @@ +-- VHDL netlist generated by SCUBA Diamond_2.0_Production (151) +-- Module Version: 5.3 +--/d/jspc29/lattice/diamond/2.01/ispfpga/bin/lin/scuba -w -n dqsinput1x4 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type iol -mode in -io_type LVDS25 -width 5 -freq_in 192 -gear 2 -clk eclk -e + +-- Wed Mar 27 18:21:05 2013 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity dqsinput1x4 is + port ( + clk: in std_logic; + clkdiv_reset: in std_logic; + eclk: out std_logic; + sclk: out std_logic; + datain: in std_logic_vector(4 downto 0); + q: out std_logic_vector(19 downto 0)); + attribute dont_touch : boolean; + attribute dont_touch of dqsinput1x4 : entity is true; +end dqsinput1x4; + +architecture Structure of dqsinput1x4 is + + -- internal signal declarations + signal qb14: std_logic; + signal qa14: std_logic; + signal qb04: std_logic; + signal qa04: std_logic; + signal qb13: std_logic; + signal qa13: std_logic; + signal qb03: std_logic; + signal qa03: std_logic; + signal qb12: std_logic; + signal qa12: std_logic; + signal qb02: std_logic; + signal qa02: std_logic; + signal qb11: std_logic; + signal qa11: std_logic; + signal qb01: std_logic; + signal qa01: std_logic; + signal qb10: std_logic; + signal qa10: std_logic; + signal qb00: std_logic; + signal qa00: std_logic; + signal cdiv8: std_logic; + signal cdiv4: std_logic; + signal cdiv1: std_logic; + signal scuba_vhi: std_logic; + signal eclk_t: std_logic; + signal dataini_t4: std_logic; + signal dataini_t3: std_logic; + signal dataini_t2: std_logic; + signal dataini_t1: std_logic; + signal dataini_t0: std_logic; + signal buf_clk: std_logic; + signal buf_dataini4: std_logic; + signal buf_dataini3: std_logic; + signal buf_dataini2: std_logic; + signal buf_dataini1: std_logic; + signal buf_dataini0: std_logic; + signal sclk_t: std_logic; + + -- local component declarations + component VHI + port (Z: out std_logic); + end component; + component IB + port (I: in std_logic; O: out std_logic); + end component; + component CLKDIVB + port (CLKI: in std_logic; RST: in std_logic; + RELEASE: in std_logic; CDIV1: out std_logic; + CDIV2: out std_logic; CDIV4: out std_logic; + CDIV8: out std_logic); + end component; + component IDDRX2D1 + generic (DR_CONFIG : in String); + port (D: in std_logic; SCLK: in std_logic; ECLK: in std_logic; + QA0: out std_logic; QB0: out std_logic; + QA1: out std_logic; QB1: out std_logic); + end component; + component DELAYC + port (A: in std_logic; Z: out std_logic); + end component; + attribute IDDRAPPS : string; + attribute IO_TYPE : string; + attribute IDDRAPPS of Inst_IDDRX2D1_0_4 : label is "ECLK_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D1_0_3 : label is "ECLK_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D1_0_2 : label is "ECLK_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D1_0_1 : label is "ECLK_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D1_0_0 : label is "ECLK_CENTERED"; + attribute IO_TYPE of Inst2_IB : label is "LVDS25"; + attribute IO_TYPE of Inst1_IB4 : label is "LVDS25"; + attribute IO_TYPE of Inst1_IB3 : label is "LVDS25"; + attribute IO_TYPE of Inst1_IB2 : label is "LVDS25"; + attribute IO_TYPE of Inst1_IB1 : label is "LVDS25"; + attribute IO_TYPE of Inst1_IB0 : label is "LVDS25"; + attribute syn_keep : boolean; + attribute syn_noprune : boolean; + attribute syn_noprune of Structure : architecture is true; + +begin + -- component instantiation statements + Inst_IDDRX2D1_0_4: IDDRX2D1 + generic map (DR_CONFIG=> "DISABLED") + port map (D=>dataini_t4, SCLK=>sclk_t, ECLK=>eclk_t, QA0=>qa04, + QB0=>qb04, QA1=>qa14, QB1=>qb14); + + Inst_IDDRX2D1_0_3: IDDRX2D1 + generic map (DR_CONFIG=> "DISABLED") + port map (D=>dataini_t3, SCLK=>sclk_t, ECLK=>eclk_t, QA0=>qa03, + QB0=>qb03, QA1=>qa13, QB1=>qb13); + + Inst_IDDRX2D1_0_2: IDDRX2D1 + generic map (DR_CONFIG=> "DISABLED") + port map (D=>dataini_t2, SCLK=>sclk_t, ECLK=>eclk_t, QA0=>qa02, + QB0=>qb02, QA1=>qa12, QB1=>qb12); + + Inst_IDDRX2D1_0_1: IDDRX2D1 + generic map (DR_CONFIG=> "DISABLED") + port map (D=>dataini_t1, SCLK=>sclk_t, ECLK=>eclk_t, QA0=>qa01, + QB0=>qb01, QA1=>qa11, QB1=>qb11); + + Inst_IDDRX2D1_0_0: IDDRX2D1 + generic map (DR_CONFIG=> "DISABLED") + port map (D=>dataini_t0, SCLK=>sclk_t, ECLK=>eclk_t, QA0=>qa00, + QB0=>qb00, QA1=>qa10, QB1=>qb10); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + Inst3_CLKDIVB: CLKDIVB + port map (CLKI=>eclk_t, RST=>clkdiv_reset, RELEASE=>scuba_vhi, + CDIV1=>cdiv1, CDIV2=>sclk_t, CDIV4=>cdiv4, CDIV8=>cdiv8); + + udel_dataini4: DELAYC + port map (A=>buf_dataini4, Z=>dataini_t4); + + udel_dataini3: DELAYC + port map (A=>buf_dataini3, Z=>dataini_t3); + + udel_dataini2: DELAYC + port map (A=>buf_dataini2, Z=>dataini_t2); + + udel_dataini1: DELAYC + port map (A=>buf_dataini1, Z=>dataini_t1); + + udel_dataini0: DELAYC + port map (A=>buf_dataini0, Z=>dataini_t0); + + Inst2_IB: IB + port map (I=>clk, O=>buf_clk); + + Inst1_IB4: IB + port map (I=>datain(4), O=>buf_dataini4); + + Inst1_IB3: IB + port map (I=>datain(3), O=>buf_dataini3); + + Inst1_IB2: IB + port map (I=>datain(2), O=>buf_dataini2); + + Inst1_IB1: IB + port map (I=>datain(1), O=>buf_dataini1); + + Inst1_IB0: IB + port map (I=>datain(0), O=>buf_dataini0); + + eclk <= eclk_t; + q(19) <= qb14; + q(18) <= qb13; + q(17) <= qb12; + q(16) <= qb11; + q(15) <= qb10; + q(14) <= qa14; + q(13) <= qa13; + q(12) <= qa12; + q(11) <= qa11; + q(10) <= qa10; + q(9) <= qb04; + q(8) <= qb03; + q(7) <= qb02; + q(6) <= qb01; + q(5) <= qb00; + q(4) <= qa04; + q(3) <= qa03; + q(2) <= qa02; + q(1) <= qa01; + q(0) <= qa00; + eclk_t <= buf_clk; + sclk <= sclk_t; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of dqsinput1x4 is + for Structure + for all:VHI use entity ecp3.VHI(V); end for; + for all:IB use entity ecp3.IB(V); end for; + for all:CLKDIVB use entity ecp3.CLKDIVB(V); end for; + for all:IDDRX2D1 use entity ecp3.IDDRX2D1(V); end for; + for all:DELAYC use entity ecp3.DELAYC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on