From: hadeshyp <hadeshyp>
Date: Thu, 10 Jan 2008 15:40:53 +0000 (+0000)
Subject: optical link on trb working, Jan
X-Git-Tag: oldGBE~644
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=a74f13b2df49066909095f81537cf517ba520d5a;p=trbnet.git

optical link on trb working, Jan
---

diff --git a/trb_net16_med_tlk.vhd b/trb_net16_med_tlk.vhd
index d775c24..7ff21c6 100644
--- a/trb_net16_med_tlk.vhd
+++ b/trb_net16_med_tlk.vhd
@@ -82,10 +82,11 @@ architecture trb_net16_med_tlk_arch of trb_net16_med_tlk is
   signal internal_reset  : std_logic;
   signal reset_counter   : std_logic_vector(16 downto 0);
 
-  signal reg_RXD : std_logic_vector(15 downto 0);
+  signal reg_RXD   : std_logic_vector(15 downto 0);
   signal reg_RX_DV : std_logic;
   signal reg_RX_ER : std_logic;
-
+  signal reg_TXD   : std_logic_vector(15 downto 0);
+  signal reg_TX_EN : std_logic;
 
 begin
 
@@ -202,8 +203,21 @@ begin
   fifo_rd_en_m <= tx_allow and not fifo_empty_m;
   fifo_wr_en_m <= MED_DATAREADY_IN and buf_MED_READ_OUT;
   fifo_din_m <= "00" & MED_DATA_IN;
-  TLK_TXD <= fifo_dout_m(15 downto 0);
-  TLK_TX_EN <= last_fifo_rd_en_m;
+  TLK_TXD <= reg_TXD;
+  TLK_TX_EN <= reg_TX_EN;
+
+  process(TLK_CLK)
+    begin
+      if rising_edge(TLK_CLK) then
+        if internal_reset = '1' then
+          reg_TXD   <= (others => '0');
+          reg_TX_EN <= '0';
+        else
+          reg_TXD   <= fifo_dout_m(15 downto 0);
+          reg_TX_EN <= last_fifo_rd_en_m;
+        end if;
+      end if;
+    end process;
 
   process(TLK_CLK)
     begin