From: Jan Michel Date: Wed, 14 Feb 2024 16:31:00 +0000 (+0100) Subject: changed few memories to use block RAM instead of distributed RAM by default X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=a754ab9abc11526363a1bb227a62f0aa0964091b;p=trbnet.git changed few memories to use block RAM instead of distributed RAM by default --- diff --git a/basics/ram_16x16_dp.vhd b/basics/ram_16x16_dp.vhd index 4f93d70..223244a 100644 --- a/basics/ram_16x16_dp.vhd +++ b/basics/ram_16x16_dp.vhd @@ -38,7 +38,7 @@ architecture ram_16x16_dp_arch of ram_16x16_dp is SIGNAL ram : ram_t := (INIT0, INIT1, INIT2, INIT3, INIT4, INIT5, INIT6, INIT7, INIT8, INIT9, INITA, INITB, INITC, INITD, INITE, INITF); attribute syn_ramstyle : string; --- attribute syn_ramstyle of ram : signal is "block_ram"; + attribute syn_ramstyle of ram : signal is "block_ram"; begin process(CLK) begin @@ -52,4 +52,4 @@ begin end if; end process; -end architecture; \ No newline at end of file +end architecture; diff --git a/basics/ram_dp.vhd b/basics/ram_dp.vhd index ad061cb..61ea5cf 100644 --- a/basics/ram_dp.vhd +++ b/basics/ram_dp.vhd @@ -25,6 +25,10 @@ end entity; architecture ram_dp_arch of ram_dp is type ram_t is array(0 to 2**depth-1) of std_logic_vector(width-1 downto 0); SIGNAL ram : ram_t ; -- := (others => (others => '0')); + + attribute syn_ramstyle : string; + attribute syn_ramstyle of ram : signal is "block_ram"; + begin diff --git a/basics/ram_dp_19x8_preset.vhd b/basics/ram_dp_19x8_preset.vhd index 6725f1a..808a2ca 100644 --- a/basics/ram_dp_19x8_preset.vhd +++ b/basics/ram_dp_19x8_preset.vhd @@ -26,7 +26,8 @@ end entity; architecture ram_dp_arch of ram_dp_19x8_preset is --type ram_t is array(0 to 2**depth-1) of std_logic_vector(width-1 downto 0); SIGNAL ram : std_logic_vector_array_20(0 to 7) := content; - + attribute syn_ramstyle : string; + attribute syn_ramstyle of ram : signal is "block_ram"; begin diff --git a/basics/ram_dp_rw.vhd b/basics/ram_dp_rw.vhd index 01f07a7..605990c 100644 --- a/basics/ram_dp_rw.vhd +++ b/basics/ram_dp_rw.vhd @@ -11,7 +11,8 @@ use work.trb_net_std.all; entity ram_dp_rw is generic( depth : integer := 3; - width : integer := 16 + width : integer := 16; + ramstyle : string := "distributed" ); port( CLK : in std_logic; @@ -26,6 +27,9 @@ end entity; architecture ram_dp_rw_arch of ram_dp_rw is type ram_t is array(0 to 2**depth-1) of std_logic_vector(width-1 downto 0); SIGNAL ram : ram_t := (others => (others => '0')); + + attribute syn_ramstyle : string; + attribute syn_ramstyle of ram : signal is ramstyle; begin process(CLK) diff --git a/lattice/ecp3/fifo/fifo_1x64k_oreg.ipx b/lattice/ecp3/fifo/fifo_1x64k_oreg.ipx new file mode 100644 index 0000000..3729ef8 --- /dev/null +++ b/lattice/ecp3/fifo/fifo_1x64k_oreg.ipx @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/lattice/ecp3/fifo/fifo_1x64k_oreg.lpc b/lattice/ecp3/fifo/fifo_1x64k_oreg.lpc new file mode 100644 index 0000000..4374972 --- /dev/null +++ b/lattice/ecp3/fifo/fifo_1x64k_oreg.lpc @@ -0,0 +1,50 @@ +[Device] +Family=ecp5um +PartType=LFE5UM-85F +PartName=LFE5UM-85F-8BG381C +SpeedGrade=8 +Package=CABGA381 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO +CoreRevision=5.1 +ModuleName=fifo_1x64k_oreg +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=12/19/2023 +Time=12:11:22 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=65536 +Width=1 +regout=1 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +Reset=Async +Reset1=Sync +RDataCount=1 +EnECC=0 +EnFWFT=0 + +[Command] +cmd_line= -w -n fifo_1x64k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 65536 -width 1 -regout -no_enable -pe -1 -pf -1 -reset_rel SYNC -fill diff --git a/lattice/ecp3/fifo/fifo_1x64k_oreg.vhd b/lattice/ecp3/fifo/fifo_1x64k_oreg.vhd new file mode 100644 index 0000000..542090a --- /dev/null +++ b/lattice/ecp3/fifo/fifo_1x64k_oreg.vhd @@ -0,0 +1,1119 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 +-- Module Version: 5.1 +--/d/jspc29/lattice/diamond/3.12/ispfpga/bin/lin64/scuba -w -n fifo_1x64k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 65536 -width 1 -regout -no_enable -pe -1 -pf -1 -reset_rel SYNC -fill + +-- Tue Dec 19 12:11:22 2023 + +library IEEE; +use IEEE.std_logic_1164.all; +library ecp5um; +use ecp5um.components.all; + +entity fifo_1x64k_oreg is + port ( + Data: in std_logic_vector(0 downto 0); + Clock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + Q: out std_logic_vector(0 downto 0); + WCNT: out std_logic_vector(16 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_1x64k_oreg; + +architecture Structure of fifo_1x64k_oreg is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal rden_i_inv: std_logic; + signal fcnt_en: std_logic; + signal empty_i: std_logic; + signal empty_d: std_logic; + signal full_i: std_logic; + signal full_d: std_logic; + signal rcount_14_ff: std_logic; + signal rcount_15_ff: std_logic; + signal ifcount_0: std_logic; + signal ifcount_1: std_logic; + signal bdcnt_bctr_ci: std_logic; + signal ifcount_2: std_logic; + signal ifcount_3: std_logic; + signal co0: std_logic; + signal ifcount_4: std_logic; + signal ifcount_5: std_logic; + signal co1: std_logic; + signal ifcount_6: std_logic; + signal ifcount_7: std_logic; + signal co2: std_logic; + signal ifcount_8: std_logic; + signal ifcount_9: std_logic; + signal co3: std_logic; + signal ifcount_10: std_logic; + signal ifcount_11: std_logic; + signal co4: std_logic; + signal ifcount_12: std_logic; + signal ifcount_13: std_logic; + signal co5: std_logic; + signal ifcount_14: std_logic; + signal ifcount_15: std_logic; + signal co6: std_logic; + signal ifcount_16: std_logic; + signal co8: std_logic; + signal cnt_con: std_logic; + signal co7: std_logic; + signal cmp_ci: std_logic; + signal rden_i: std_logic; + signal co0_1: std_logic; + signal co1_1: std_logic; + signal co2_1: std_logic; + signal co3_1: std_logic; + signal co4_1: std_logic; + signal co5_1: std_logic; + signal co6_1: std_logic; + signal co7_1: std_logic; + signal cmp_le_1: std_logic; + signal cmp_le_1_c: std_logic; + signal cmp_ci_1: std_logic; + signal fcount_0: std_logic; + signal fcount_1: std_logic; + signal co0_2: std_logic; + signal fcount_2: std_logic; + signal fcount_3: std_logic; + signal co1_2: std_logic; + signal fcount_4: std_logic; + signal fcount_5: std_logic; + signal co2_2: std_logic; + signal fcount_6: std_logic; + signal fcount_7: std_logic; + signal co3_2: std_logic; + signal fcount_8: std_logic; + signal fcount_9: std_logic; + signal co4_2: std_logic; + signal fcount_10: std_logic; + signal fcount_11: std_logic; + signal co5_2: std_logic; + signal fcount_12: std_logic; + signal fcount_13: std_logic; + signal co6_2: std_logic; + signal wren_i: std_logic; + signal fcount_14: std_logic; + signal fcount_15: std_logic; + signal co7_2: std_logic; + signal wren_i_inv: std_logic; + signal fcount_16: std_logic; + signal cmp_ge_d1: std_logic; + signal cmp_ge_d1_c: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_ctr_ci: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0_3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1_3: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2_3: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3_3: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal iwcount_10: std_logic; + signal iwcount_11: std_logic; + signal co4_3: std_logic; + signal wcount_10: std_logic; + signal wcount_11: std_logic; + signal iwcount_12: std_logic; + signal iwcount_13: std_logic; + signal co5_3: std_logic; + signal wcount_12: std_logic; + signal wcount_13: std_logic; + signal iwcount_14: std_logic; + signal iwcount_15: std_logic; + signal co6_3: std_logic; + signal wcount_14: std_logic; + signal wcount_15: std_logic; + signal iwcount_16: std_logic; + signal co8_1: std_logic; + signal co7_3: std_logic; + signal wcount_16: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_ctr_ci: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_4: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_4: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_4: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_4: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal ircount_10: std_logic; + signal ircount_11: std_logic; + signal co4_4: std_logic; + signal rcount_10: std_logic; + signal rcount_11: std_logic; + signal ircount_12: std_logic; + signal ircount_13: std_logic; + signal co5_4: std_logic; + signal rcount_12: std_logic; + signal rcount_13: std_logic; + signal ircount_14: std_logic; + signal ircount_15: std_logic; + signal co6_4: std_logic; + signal rcount_14: std_logic; + signal rcount_15: std_logic; + signal ircount_16: std_logic; + signal co8_2: std_logic; + signal scuba_vhi: std_logic; + signal co7_4: std_logic; + signal rcount_16: std_logic; + signal scuba_vlo: std_logic; + signal rcount_15_ff2: std_logic; + signal rcount_14_ff2: std_logic; + signal mdout1_3_0: std_logic; + signal mdout1_2_0: std_logic; + signal mdout1_1_0: std_logic; + signal mdout1_0_0: std_logic; + + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_3 : label is "fifo_1x64k_oreg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_3 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_1_0_2 : label is "fifo_1x64k_oreg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_0_2 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_2_0_1 : label is "fifo_1x64k_oreg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_0_1 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_3_0_0 : label is "fifo_1x64k_oreg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_0_0 : label is ""; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t3: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_3: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t2: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_2: INV + port map (A=>empty_i, Z=>invout_0); + + AND2_t1: AND2 + port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con); + + XOR2_t0: XOR2 + port map (A=>wren_i, B=>rden_i, Z=>fcnt_en); + + INV_1: INV + port map (A=>rden_i, Z=>rden_i_inv); + + INV_0: INV + port map (A=>wren_i, Z=>wren_i_inv); + + LUT4_1: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, + AD0=>empty_i, DO0=>empty_d); + + LUT4_0: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, + AD0=>full_i, DO0=>full_d); + + pdp_ram_0_0_3: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>scuba_vlo, DIA7=>scuba_vlo, DIA6=>scuba_vlo, + DIA5=>scuba_vlo, DIA4=>scuba_vlo, DIA3=>scuba_vlo, + DIA2=>scuba_vlo, DIA1=>scuba_vlo, DIA0=>Data(0), + ADA13=>wcount_13, ADA12=>wcount_12, ADA11=>wcount_11, + ADA10=>wcount_10, ADA9=>wcount_9, ADA8=>wcount_8, + ADA7=>wcount_7, ADA6=>wcount_6, ADA5=>wcount_5, + ADA4=>wcount_4, ADA3=>wcount_3, ADA2=>wcount_2, + ADA1=>wcount_1, ADA0=>wcount_0, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>wcount_15, CSA0=>wcount_14, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rcount_13, ADB12=>rcount_12, ADB11=>rcount_11, + ADB10=>rcount_10, ADB9=>rcount_9, ADB8=>rcount_8, + ADB7=>rcount_7, ADB6=>rcount_6, ADB5=>rcount_5, + ADB4=>rcount_4, ADB3=>rcount_3, ADB2=>rcount_2, + ADB1=>rcount_1, ADB0=>rcount_0, CEB=>rden_i, OCEB=>scuba_vhi, + CLKB=>Clock, WEB=>scuba_vlo, CSB2=>scuba_vlo, + CSB1=>rcount_15, CSB0=>rcount_14, RSTB=>Reset, DOA17=>open, + DOA16=>open, DOA15=>open, DOA14=>open, DOA13=>open, + DOA12=>open, DOA11=>open, DOA10=>open, DOA9=>open, + DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open, DOA4=>open, + DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open, DOB17=>open, + DOB16=>open, DOB15=>open, DOB14=>open, DOB13=>open, + DOB12=>open, DOB11=>open, DOB10=>open, DOB9=>open, + DOB8=>open, DOB7=>open, DOB6=>open, DOB5=>open, DOB4=>open, + DOB3=>open, DOB2=>open, DOB1=>open, DOB0=>mdout1_0_0); + + pdp_ram_1_0_2: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>scuba_vlo, DIA7=>scuba_vlo, DIA6=>scuba_vlo, + DIA5=>scuba_vlo, DIA4=>scuba_vlo, DIA3=>scuba_vlo, + DIA2=>scuba_vlo, DIA1=>scuba_vlo, DIA0=>Data(0), + ADA13=>wcount_13, ADA12=>wcount_12, ADA11=>wcount_11, + ADA10=>wcount_10, ADA9=>wcount_9, ADA8=>wcount_8, + ADA7=>wcount_7, ADA6=>wcount_6, ADA5=>wcount_5, + ADA4=>wcount_4, ADA3=>wcount_3, ADA2=>wcount_2, + ADA1=>wcount_1, ADA0=>wcount_0, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>wcount_15, CSA0=>wcount_14, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rcount_13, ADB12=>rcount_12, ADB11=>rcount_11, + ADB10=>rcount_10, ADB9=>rcount_9, ADB8=>rcount_8, + ADB7=>rcount_7, ADB6=>rcount_6, ADB5=>rcount_5, + ADB4=>rcount_4, ADB3=>rcount_3, ADB2=>rcount_2, + ADB1=>rcount_1, ADB0=>rcount_0, CEB=>rden_i, OCEB=>scuba_vhi, + CLKB=>Clock, WEB=>scuba_vlo, CSB2=>scuba_vlo, + CSB1=>rcount_15, CSB0=>rcount_14, RSTB=>Reset, DOA17=>open, + DOA16=>open, DOA15=>open, DOA14=>open, DOA13=>open, + DOA12=>open, DOA11=>open, DOA10=>open, DOA9=>open, + DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open, DOA4=>open, + DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open, DOB17=>open, + DOB16=>open, DOB15=>open, DOB14=>open, DOB13=>open, + DOB12=>open, DOB11=>open, DOB10=>open, DOB9=>open, + DOB8=>open, DOB7=>open, DOB6=>open, DOB5=>open, DOB4=>open, + DOB3=>open, DOB2=>open, DOB1=>open, DOB0=>mdout1_1_0); + + pdp_ram_2_0_1: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>scuba_vlo, DIA7=>scuba_vlo, DIA6=>scuba_vlo, + DIA5=>scuba_vlo, DIA4=>scuba_vlo, DIA3=>scuba_vlo, + DIA2=>scuba_vlo, DIA1=>scuba_vlo, DIA0=>Data(0), + ADA13=>wcount_13, ADA12=>wcount_12, ADA11=>wcount_11, + ADA10=>wcount_10, ADA9=>wcount_9, ADA8=>wcount_8, + ADA7=>wcount_7, ADA6=>wcount_6, ADA5=>wcount_5, + ADA4=>wcount_4, ADA3=>wcount_3, ADA2=>wcount_2, + ADA1=>wcount_1, ADA0=>wcount_0, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>wcount_15, CSA0=>wcount_14, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rcount_13, ADB12=>rcount_12, ADB11=>rcount_11, + ADB10=>rcount_10, ADB9=>rcount_9, ADB8=>rcount_8, + ADB7=>rcount_7, ADB6=>rcount_6, ADB5=>rcount_5, + ADB4=>rcount_4, ADB3=>rcount_3, ADB2=>rcount_2, + ADB1=>rcount_1, ADB0=>rcount_0, CEB=>rden_i, OCEB=>scuba_vhi, + CLKB=>Clock, WEB=>scuba_vlo, CSB2=>scuba_vlo, + CSB1=>rcount_15, CSB0=>rcount_14, RSTB=>Reset, DOA17=>open, + DOA16=>open, DOA15=>open, DOA14=>open, DOA13=>open, + DOA12=>open, DOA11=>open, DOA10=>open, DOA9=>open, + DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open, DOA4=>open, + DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open, DOB17=>open, + DOB16=>open, DOB15=>open, DOB14=>open, DOB13=>open, + DOB12=>open, DOB11=>open, DOB10=>open, DOB9=>open, + DOB8=>open, DOB7=>open, DOB6=>open, DOB5=>open, DOB4=>open, + DOB3=>open, DOB2=>open, DOB1=>open, DOB0=>mdout1_2_0); + + pdp_ram_3_0_0: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>scuba_vlo, DIA7=>scuba_vlo, DIA6=>scuba_vlo, + DIA5=>scuba_vlo, DIA4=>scuba_vlo, DIA3=>scuba_vlo, + DIA2=>scuba_vlo, DIA1=>scuba_vlo, DIA0=>Data(0), + ADA13=>wcount_13, ADA12=>wcount_12, ADA11=>wcount_11, + ADA10=>wcount_10, ADA9=>wcount_9, ADA8=>wcount_8, + ADA7=>wcount_7, ADA6=>wcount_6, ADA5=>wcount_5, + ADA4=>wcount_4, ADA3=>wcount_3, ADA2=>wcount_2, + ADA1=>wcount_1, ADA0=>wcount_0, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>wcount_15, CSA0=>wcount_14, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rcount_13, ADB12=>rcount_12, ADB11=>rcount_11, + ADB10=>rcount_10, ADB9=>rcount_9, ADB8=>rcount_8, + ADB7=>rcount_7, ADB6=>rcount_6, ADB5=>rcount_5, + ADB4=>rcount_4, ADB3=>rcount_3, ADB2=>rcount_2, + ADB1=>rcount_1, ADB0=>rcount_0, CEB=>rden_i, OCEB=>scuba_vhi, + CLKB=>Clock, WEB=>scuba_vlo, CSB2=>scuba_vlo, + CSB1=>rcount_15, CSB0=>rcount_14, RSTB=>Reset, DOA17=>open, + DOA16=>open, DOA15=>open, DOA14=>open, DOA13=>open, + DOA12=>open, DOA11=>open, DOA10=>open, DOA9=>open, + DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open, DOA4=>open, + DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open, DOB17=>open, + DOB16=>open, DOB15=>open, DOB14=>open, DOB13=>open, + DOB12=>open, DOB11=>open, DOB10=>open, DOB9=>open, + DOB8=>open, DOB7=>open, DOB6=>open, DOB5=>open, DOB4=>open, + DOB3=>open, DOB2=>open, DOB1=>open, DOB0=>mdout1_3_0); + + FF_56: FD1P3DX + port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_0); + + FF_55: FD1P3DX + port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_1); + + FF_54: FD1P3DX + port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_2); + + FF_53: FD1P3DX + port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_3); + + FF_52: FD1P3DX + port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_4); + + FF_51: FD1P3DX + port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_5); + + FF_50: FD1P3DX + port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_6); + + FF_49: FD1P3DX + port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_7); + + FF_48: FD1P3DX + port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_8); + + FF_47: FD1P3DX + port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_9); + + FF_46: FD1P3DX + port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_10); + + FF_45: FD1P3DX + port map (D=>ifcount_11, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_11); + + FF_44: FD1P3DX + port map (D=>ifcount_12, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_12); + + FF_43: FD1P3DX + port map (D=>ifcount_13, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_13); + + FF_42: FD1P3DX + port map (D=>ifcount_14, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_14); + + FF_41: FD1P3DX + port map (D=>ifcount_15, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_15); + + FF_40: FD1P3DX + port map (D=>ifcount_16, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_16); + + FF_39: FD1S3BX + port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i); + + FF_38: FD1S3DX + port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i); + + FF_37: FD1P3DX + port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_0); + + FF_36: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_1); + + FF_35: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_2); + + FF_34: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_3); + + FF_33: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_4); + + FF_32: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_5); + + FF_31: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_6); + + FF_30: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_7); + + FF_29: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_8); + + FF_28: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_9); + + FF_27: FD1P3DX + port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_10); + + FF_26: FD1P3DX + port map (D=>iwcount_11, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_11); + + FF_25: FD1P3DX + port map (D=>iwcount_12, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_12); + + FF_24: FD1P3DX + port map (D=>iwcount_13, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_13); + + FF_23: FD1P3DX + port map (D=>iwcount_14, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_14); + + FF_22: FD1P3DX + port map (D=>iwcount_15, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_15); + + FF_21: FD1P3DX + port map (D=>iwcount_16, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_16); + + FF_20: FD1P3DX + port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_0); + + FF_19: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_1); + + FF_18: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_2); + + FF_17: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_3); + + FF_16: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_4); + + FF_15: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_5); + + FF_14: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_6); + + FF_13: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_7); + + FF_12: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_8); + + FF_11: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_9); + + FF_10: FD1P3DX + port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_10); + + FF_9: FD1P3DX + port map (D=>ircount_11, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_11); + + FF_8: FD1P3DX + port map (D=>ircount_12, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_12); + + FF_7: FD1P3DX + port map (D=>ircount_13, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_13); + + FF_6: FD1P3DX + port map (D=>ircount_14, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_14); + + FF_5: FD1P3DX + port map (D=>ircount_15, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_15); + + FF_4: FD1P3DX + port map (D=>ircount_16, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_16); + + FF_3: FD1P3DX + port map (D=>rcount_14, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, + Q=>rcount_14_ff); + + FF_2: FD1P3DX + port map (D=>rcount_15, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, + Q=>rcount_15_ff); + + FF_1: FD1P3DX + port map (D=>rcount_14_ff, SP=>scuba_vhi, CK=>Clock, + CD=>scuba_vlo, Q=>rcount_14_ff2); + + FF_0: FD1P3DX + port map (D=>rcount_15_ff, SP=>scuba_vhi, CK=>Clock, + CD=>scuba_vlo, Q=>rcount_15_ff2); + + bdcnt_bctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>'X', S0=>open, S1=>open, COUT=>bdcnt_bctr_ci); + + bdcnt_bctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_0, A1=>fcount_1, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>bdcnt_bctr_ci, S0=>ifcount_0, S1=>ifcount_1, COUT=>co0); + + bdcnt_bctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0, S0=>ifcount_2, S1=>ifcount_3, COUT=>co1); + + bdcnt_bctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_4, A1=>fcount_5, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1, S0=>ifcount_4, S1=>ifcount_5, COUT=>co2); + + bdcnt_bctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_6, A1=>fcount_7, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co2, S0=>ifcount_6, S1=>ifcount_7, COUT=>co3); + + bdcnt_bctr_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_8, A1=>fcount_9, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co3, S0=>ifcount_8, S1=>ifcount_9, COUT=>co4); + + bdcnt_bctr_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_10, A1=>fcount_11, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co4, S0=>ifcount_10, S1=>ifcount_11, COUT=>co5); + + bdcnt_bctr_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_12, A1=>fcount_13, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co5, S0=>ifcount_12, S1=>ifcount_13, COUT=>co6); + + bdcnt_bctr_7: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_14, A1=>fcount_15, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co6, S0=>ifcount_14, S1=>ifcount_15, COUT=>co7); + + bdcnt_bctr_8: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_16, A1=>scuba_vlo, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co7, S0=>ifcount_16, S1=>open, COUT=>co8); + + e_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci); + + e_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rden_i, A1=>scuba_vlo, B0=>fcount_0, B1=>fcount_1, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>cmp_ci, S0=>open, S1=>open, COUT=>co0_1); + + e_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_2, + B1=>fcount_3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_1, S0=>open, S1=>open, COUT=>co1_1); + + e_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_4, + B1=>fcount_5, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_1, S0=>open, S1=>open, COUT=>co2_1); + + e_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_6, + B1=>fcount_7, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_1, S0=>open, S1=>open, COUT=>co3_1); + + e_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_8, + B1=>fcount_9, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_1, S0=>open, S1=>open, COUT=>co4_1); + + e_cmp_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_10, + B1=>fcount_11, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_1, S0=>open, S1=>open, COUT=>co5_1); + + e_cmp_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_12, + B1=>fcount_13, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co5_1, S0=>open, S1=>open, COUT=>co6_1); + + e_cmp_7: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_14, + B1=>fcount_15, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co6_1, S0=>open, S1=>open, COUT=>co7_1); + + e_cmp_8: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_16, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co7_1, S0=>open, S1=>open, + COUT=>cmp_le_1_c); + + a0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_le_1_c, S0=>cmp_le_1, S1=>open, + COUT=>open); + + g_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_1); + + g_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>cmp_ci_1, S0=>open, S1=>open, COUT=>co0_2); + + g_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0_2, S0=>open, S1=>open, COUT=>co1_2); + + g_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1_2, S0=>open, S1=>open, COUT=>co2_2); + + g_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co2_2, S0=>open, S1=>open, COUT=>co3_2); + + g_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co3_2, S0=>open, S1=>open, COUT=>co4_2); + + g_cmp_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_10, A1=>fcount_11, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co4_2, S0=>open, S1=>open, COUT=>co5_2); + + g_cmp_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_12, A1=>fcount_13, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co5_2, S0=>open, S1=>open, COUT=>co6_2); + + g_cmp_7: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_14, A1=>fcount_15, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co6_2, S0=>open, S1=>open, COUT=>co7_2); + + g_cmp_8: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_16, A1=>scuba_vlo, B0=>wren_i_inv, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co7_2, S0=>open, S1=>open, + COUT=>cmp_ge_d1_c); + + a1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_ge_d1_c, S0=>cmp_ge_d1, S1=>open, + COUT=>open); + + w_ctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>w_ctr_ci); + + w_ctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>w_ctr_ci, S0=>iwcount_0, S1=>iwcount_1, + COUT=>co0_3); + + w_ctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_3, S0=>iwcount_2, S1=>iwcount_3, + COUT=>co1_3); + + w_ctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_4, A1=>wcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_3, S0=>iwcount_4, S1=>iwcount_5, + COUT=>co2_3); + + w_ctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_6, A1=>wcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_3, S0=>iwcount_6, S1=>iwcount_7, + COUT=>co3_3); + + w_ctr_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_8, A1=>wcount_9, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_3, S0=>iwcount_8, S1=>iwcount_9, + COUT=>co4_3); + + w_ctr_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_10, A1=>wcount_11, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_3, S0=>iwcount_10, S1=>iwcount_11, + COUT=>co5_3); + + w_ctr_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_12, A1=>wcount_13, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co5_3, S0=>iwcount_12, S1=>iwcount_13, + COUT=>co6_3); + + w_ctr_7: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_14, A1=>wcount_15, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co6_3, S0=>iwcount_14, S1=>iwcount_15, + COUT=>co7_3); + + w_ctr_8: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_16, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co7_3, S0=>iwcount_16, S1=>open, + COUT=>co8_1); + + r_ctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>r_ctr_ci); + + r_ctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>r_ctr_ci, S0=>ircount_0, S1=>ircount_1, + COUT=>co0_4); + + r_ctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_2, A1=>rcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_4, S0=>ircount_2, S1=>ircount_3, + COUT=>co1_4); + + r_ctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_4, A1=>rcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_4, S0=>ircount_4, S1=>ircount_5, + COUT=>co2_4); + + r_ctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_6, A1=>rcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_4, S0=>ircount_6, S1=>ircount_7, + COUT=>co3_4); + + r_ctr_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_8, A1=>rcount_9, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_4, S0=>ircount_8, S1=>ircount_9, + COUT=>co4_4); + + r_ctr_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_10, A1=>rcount_11, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_4, S0=>ircount_10, S1=>ircount_11, + COUT=>co5_4); + + r_ctr_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_12, A1=>rcount_13, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co5_4, S0=>ircount_12, S1=>ircount_13, + COUT=>co6_4); + + r_ctr_7: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_14, A1=>rcount_15, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co6_4, S0=>ircount_14, S1=>ircount_15, + COUT=>co7_4); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_ctr_8: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_16, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co7_4, S0=>ircount_16, S1=>open, + COUT=>co8_2); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + mux_0: MUX41 + port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0, + D3=>mdout1_3_0, SD1=>rcount_14_ff2, SD2=>rcount_15_ff2, + Z=>Q(0)); + + WCNT(0) <= fcount_0; + WCNT(1) <= fcount_1; + WCNT(2) <= fcount_2; + WCNT(3) <= fcount_3; + WCNT(4) <= fcount_4; + WCNT(5) <= fcount_5; + WCNT(6) <= fcount_6; + WCNT(7) <= fcount_7; + WCNT(8) <= fcount_8; + WCNT(9) <= fcount_9; + WCNT(10) <= fcount_10; + WCNT(11) <= fcount_11; + WCNT(12) <= fcount_12; + WCNT(13) <= fcount_13; + WCNT(14) <= fcount_14; + WCNT(15) <= fcount_15; + WCNT(16) <= fcount_16; + Empty <= empty_i; + Full <= full_i; +end Structure; diff --git a/lattice/ecp3/fifo/fifo_4x2k_oreg.ipx b/lattice/ecp3/fifo/fifo_4x2k_oreg.ipx new file mode 100644 index 0000000..d139fae --- /dev/null +++ b/lattice/ecp3/fifo/fifo_4x2k_oreg.ipx @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/lattice/ecp3/fifo/fifo_4x2k_oreg.lpc b/lattice/ecp3/fifo/fifo_4x2k_oreg.lpc new file mode 100644 index 0000000..86ee369 --- /dev/null +++ b/lattice/ecp3/fifo/fifo_4x2k_oreg.lpc @@ -0,0 +1,48 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN672C +SpeedGrade=8 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO +CoreRevision=5.1 +ModuleName=fifo_4x2k_oreg +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=12/27/2023 +Time=12:31:55 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=2048 +Width=4 +regout=1 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=1 +EnECC=0 +EnFWFT=0 + +[Command] +cmd_line= -w -n fifo_4x2k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifoblk -addr_width 11 -data_width 4 -num_words 2048 -outdata REGISTERED -no_enable -pe -1 -pf -1 -fill diff --git a/lattice/ecp3/fifo/fifo_4x2k_oreg.vhd b/lattice/ecp3/fifo/fifo_4x2k_oreg.vhd new file mode 100644 index 0000000..cafa06c --- /dev/null +++ b/lattice/ecp3/fifo/fifo_4x2k_oreg.vhd @@ -0,0 +1,745 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 +-- Module Version: 5.1 +--/d/jspc29/lattice/diamond/3.12/ispfpga/bin/lin64/scuba -w -n fifo_4x2k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 2048 -width 4 -depth 2048 -regout -no_enable -pe -1 -pf -1 -fill + +-- Wed Dec 27 12:31:55 2023 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_4x2k_oreg is + port ( + Data: in std_logic_vector(3 downto 0); + Clock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + Q: out std_logic_vector(3 downto 0); + WCNT: out std_logic_vector(11 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_4x2k_oreg; + +architecture Structure of fifo_4x2k_oreg is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal rden_i_inv: std_logic; + signal fcnt_en: std_logic; + signal empty_i: std_logic; + signal empty_d: std_logic; + signal full_i: std_logic; + signal full_d: std_logic; + signal ifcount_0: std_logic; + signal ifcount_1: std_logic; + signal bdcnt_bctr_ci: std_logic; + signal ifcount_2: std_logic; + signal ifcount_3: std_logic; + signal co0: std_logic; + signal ifcount_4: std_logic; + signal ifcount_5: std_logic; + signal co1: std_logic; + signal ifcount_6: std_logic; + signal ifcount_7: std_logic; + signal co2: std_logic; + signal ifcount_8: std_logic; + signal ifcount_9: std_logic; + signal co3: std_logic; + signal ifcount_10: std_logic; + signal ifcount_11: std_logic; + signal co5: std_logic; + signal cnt_con: std_logic; + signal co4: std_logic; + signal cmp_ci: std_logic; + signal rden_i: std_logic; + signal co0_1: std_logic; + signal co1_1: std_logic; + signal co2_1: std_logic; + signal co3_1: std_logic; + signal co4_1: std_logic; + signal cmp_le_1: std_logic; + signal cmp_le_1_c: std_logic; + signal cmp_ci_1: std_logic; + signal fcount_0: std_logic; + signal fcount_1: std_logic; + signal co0_2: std_logic; + signal fcount_2: std_logic; + signal fcount_3: std_logic; + signal co1_2: std_logic; + signal fcount_4: std_logic; + signal fcount_5: std_logic; + signal co2_2: std_logic; + signal fcount_6: std_logic; + signal fcount_7: std_logic; + signal co3_2: std_logic; + signal fcount_8: std_logic; + signal fcount_9: std_logic; + signal co4_2: std_logic; + signal wren_i: std_logic; + signal wren_i_inv: std_logic; + signal fcount_10: std_logic; + signal fcount_11: std_logic; + signal cmp_ge_d1: std_logic; + signal cmp_ge_d1_c: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_ctr_ci: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0_3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1_3: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2_3: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3_3: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal iwcount_10: std_logic; + signal iwcount_11: std_logic; + signal co5_1: std_logic; + signal co4_3: std_logic; + signal wcount_10: std_logic; + signal wcount_11: std_logic; + signal scuba_vlo: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_ctr_ci: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_4: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_4: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_4: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_4: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal ircount_10: std_logic; + signal ircount_11: std_logic; + signal co5_2: std_logic; + signal co4_4: std_logic; + signal rcount_10: std_logic; + signal rcount_11: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component ALEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; LE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component CB2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CON: in std_logic; CO: out std_logic; NC0: out std_logic; + NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KC + generic (GSR : in String; WRITEMODE_B : in String; + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_4x2k_oreg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t3: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_3: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t2: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_2: INV + port map (A=>empty_i, Z=>invout_0); + + AND2_t1: AND2 + port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con); + + XOR2_t0: XOR2 + port map (A=>wren_i, B=>rden_i, Z=>fcnt_en); + + INV_1: INV + port map (A=>rden_i, Z=>rden_i_inv); + + INV_0: INV + port map (A=>wren_i, Z=>wren_i_inv); + + LUT4_1: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, + AD0=>empty_i, DO0=>empty_d); + + LUT4_0: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, + AD0=>full_i, DO0=>full_d); + + pdp_ram_0_0_0: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, + ADA3=>wcount_0, ADA4=>wcount_1, ADA5=>wcount_2, + ADA6=>wcount_3, ADA7=>wcount_4, ADA8=>wcount_5, + ADA9=>wcount_6, ADA10=>wcount_7, ADA11=>wcount_8, + ADA12=>wcount_9, ADA13=>wcount_10, CEA=>wren_i, CLKA=>Clock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, + ADB3=>rcount_0, ADB4=>rcount_1, ADB5=>rcount_2, + ADB6=>rcount_3, ADB7=>rcount_4, ADB8=>rcount_5, + ADB9=>rcount_6, ADB10=>rcount_7, ADB11=>rcount_8, + ADB12=>rcount_9, ADB13=>rcount_10, CEB=>rden_i, CLKB=>Clock, + OCEB=>scuba_vhi, WEB=>scuba_vlo, CSB0=>scuba_vlo, + CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, + DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, + DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, + DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, + DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(0), + DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), DOB4=>open, DOB5=>open, + DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, + DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, + DOB15=>open, DOB16=>open, DOB17=>open); + + FF_37: FD1P3DX + port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_0); + + FF_36: FD1P3DX + port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_1); + + FF_35: FD1P3DX + port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_2); + + FF_34: FD1P3DX + port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_3); + + FF_33: FD1P3DX + port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_4); + + FF_32: FD1P3DX + port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_5); + + FF_31: FD1P3DX + port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_6); + + FF_30: FD1P3DX + port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_7); + + FF_29: FD1P3DX + port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_8); + + FF_28: FD1P3DX + port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_9); + + FF_27: FD1P3DX + port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_10); + + FF_26: FD1P3DX + port map (D=>ifcount_11, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_11); + + FF_25: FD1S3BX + port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i); + + FF_24: FD1S3DX + port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i); + + FF_23: FD1P3DX + port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_0); + + FF_22: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_1); + + FF_21: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_2); + + FF_20: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_3); + + FF_19: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_4); + + FF_18: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_5); + + FF_17: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_6); + + FF_16: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_7); + + FF_15: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_8); + + FF_14: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_9); + + FF_13: FD1P3DX + port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_10); + + FF_12: FD1P3DX + port map (D=>iwcount_11, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_11); + + FF_11: FD1P3DX + port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_0); + + FF_10: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_1); + + FF_9: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_2); + + FF_8: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_3); + + FF_7: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_4); + + FF_6: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_5); + + FF_5: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_6); + + FF_4: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_7); + + FF_3: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_8); + + FF_2: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_9); + + FF_1: FD1P3DX + port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_10); + + FF_0: FD1P3DX + port map (D=>ircount_11, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_11); + + bdcnt_bctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, + CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open); + + bdcnt_bctr_0: CB2 + port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1, + CON=>cnt_con, CO=>co0, NC0=>ifcount_0, NC1=>ifcount_1); + + bdcnt_bctr_1: CB2 + port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con, + CO=>co1, NC0=>ifcount_2, NC1=>ifcount_3); + + bdcnt_bctr_2: CB2 + port map (CI=>co1, PC0=>fcount_4, PC1=>fcount_5, CON=>cnt_con, + CO=>co2, NC0=>ifcount_4, NC1=>ifcount_5); + + bdcnt_bctr_3: CB2 + port map (CI=>co2, PC0=>fcount_6, PC1=>fcount_7, CON=>cnt_con, + CO=>co3, NC0=>ifcount_6, NC1=>ifcount_7); + + bdcnt_bctr_4: CB2 + port map (CI=>co3, PC0=>fcount_8, PC1=>fcount_9, CON=>cnt_con, + CO=>co4, NC0=>ifcount_8, NC1=>ifcount_9); + + bdcnt_bctr_5: CB2 + port map (CI=>co4, PC0=>fcount_10, PC1=>fcount_11, CON=>cnt_con, + CO=>co5, NC0=>ifcount_10, NC1=>ifcount_11); + + e_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, + S1=>open); + + e_cmp_0: ALEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo, + CI=>cmp_ci, LE=>co0_1); + + e_cmp_1: ALEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co0_1, LE=>co1_1); + + e_cmp_2: ALEB2 + port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co1_1, LE=>co2_1); + + e_cmp_3: ALEB2 + port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co2_1, LE=>co3_1); + + e_cmp_4: ALEB2 + port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co3_1, LE=>co4_1); + + e_cmp_5: ALEB2 + port map (A0=>fcount_10, A1=>fcount_11, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co4_1, LE=>cmp_le_1_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1, + S1=>open); + + g_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, + S1=>open); + + g_cmp_0: AGEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, + CI=>cmp_ci_1, GE=>co0_2); + + g_cmp_1: AGEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, + CI=>co0_2, GE=>co1_2); + + g_cmp_2: AGEB2 + port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i, + CI=>co1_2, GE=>co2_2); + + g_cmp_3: AGEB2 + port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i, + CI=>co2_2, GE=>co3_2); + + g_cmp_4: AGEB2 + port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i, + CI=>co3_2, GE=>co4_2); + + g_cmp_5: AGEB2 + port map (A0=>fcount_10, A1=>fcount_11, B0=>wren_i, + B1=>wren_i_inv, CI=>co4_2, GE=>cmp_ge_d1_c); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1, + S1=>open); + + w_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open, + S1=>open); + + w_ctr_0: CU2 + port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_ctr_1: CU2 + port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_ctr_2: CU2 + port map (CI=>co1_3, PC0=>wcount_4, PC1=>wcount_5, CO=>co2_3, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_ctr_3: CU2 + port map (CI=>co2_3, PC0=>wcount_6, PC1=>wcount_7, CO=>co3_3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_ctr_4: CU2 + port map (CI=>co3_3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4_3, + NC0=>iwcount_8, NC1=>iwcount_9); + + w_ctr_5: CU2 + port map (CI=>co4_3, PC0=>wcount_10, PC1=>wcount_11, CO=>co5_1, + NC0=>iwcount_10, NC1=>iwcount_11); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open, + S1=>open); + + r_ctr_0: CU2 + port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4, + NC0=>ircount_0, NC1=>ircount_1); + + r_ctr_1: CU2 + port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4, + NC0=>ircount_2, NC1=>ircount_3); + + r_ctr_2: CU2 + port map (CI=>co1_4, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_4, + NC0=>ircount_4, NC1=>ircount_5); + + r_ctr_3: CU2 + port map (CI=>co2_4, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_4, + NC0=>ircount_6, NC1=>ircount_7); + + r_ctr_4: CU2 + port map (CI=>co3_4, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_4, + NC0=>ircount_8, NC1=>ircount_9); + + r_ctr_5: CU2 + port map (CI=>co4_4, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_2, + NC0=>ircount_10, NC1=>ircount_11); + + WCNT(0) <= fcount_0; + WCNT(1) <= fcount_1; + WCNT(2) <= fcount_2; + WCNT(3) <= fcount_3; + WCNT(4) <= fcount_4; + WCNT(5) <= fcount_5; + WCNT(6) <= fcount_6; + WCNT(7) <= fcount_7; + WCNT(8) <= fcount_8; + WCNT(9) <= fcount_9; + WCNT(10) <= fcount_10; + WCNT(11) <= fcount_11; + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_4x2k_oreg is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:ALEB2 use entity ecp3.ALEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:CB2 use entity ecp3.CB2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/lattice/ecp5/FIFO/fifo_19x16.ipx b/lattice/ecp5/FIFO/fifo_19x16.ipx index 0b2c36e..8def3cc 100644 --- a/lattice/ecp5/FIFO/fifo_19x16.ipx +++ b/lattice/ecp5/FIFO/fifo_19x16.ipx @@ -1,9 +1,9 @@ - + - - - - + + + + diff --git a/lattice/ecp5/FIFO/fifo_19x16.lpc b/lattice/ecp5/FIFO/fifo_19x16.lpc index cd4a10f..3ef2815 100644 --- a/lattice/ecp5/FIFO/fifo_19x16.lpc +++ b/lattice/ecp5/FIFO/fifo_19x16.lpc @@ -16,8 +16,8 @@ CoreRevision=5.1 ModuleName=fifo_19x16 SourceFormat=VHDL ParameterFileVersion=1.0 -Date=11/09/2020 -Time=17:39:57 +Date=02/14/2024 +Time=14:03:57 [Parameters] Verilog=0 @@ -27,7 +27,7 @@ Destination=Synplicity Expression=BusA(0 to 7) Order=Big Endian [MSB:LSB] IO=0 -FIFOImp=LUT Based +FIFOImp=EBR Based Depth=16 Width=19 regout=0 @@ -47,4 +47,4 @@ EnECC=0 EnFWFT=0 [Command] -cmd_line= -w -n fifo_19x16 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -pfu_fifo -depth 16 -width 19 -no_enable -pe -1 -pf 8 -reset_rel SYNC -fill +cmd_line= -w -n fifo_19x16 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 16 -width 19 -no_enable -pe -1 -pf 8 -reset_rel SYNC -fill diff --git a/lattice/ecp5/FIFO/fifo_19x16.vhd b/lattice/ecp5/FIFO/fifo_19x16.vhd index 5d789b4..ccd4127 100644 --- a/lattice/ecp5/FIFO/fifo_19x16.vhd +++ b/lattice/ecp5/FIFO/fifo_19x16.vhd @@ -1,8 +1,8 @@ --- VHDL netlist generated by SCUBA Diamond (64-bit) 3.11.2.446 +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 -- Module Version: 5.1 ---/d/jspc29/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n fifo_19x16 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -pfu_fifo -depth 16 -width 19 -no_enable -pe -1 -pf 8 -reset_rel SYNC -fill +--/d/jspc29/lattice/diamond/3.12/ispfpga/bin/lin64/scuba -w -n fifo_19x16 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 16 -width 19 -no_enable -pe -1 -pf 8 -reset_rel SYNC -fill --- Mon Nov 9 17:39:57 2020 +-- Wed Feb 14 14:03:57 2024 library IEEE; use IEEE.std_logic_1164.all; @@ -63,9 +63,13 @@ architecture Structure of fifo_19x16 is signal iwcount_0: std_logic; signal iwcount_1: std_logic; signal w_ctr_ci: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; signal iwcount_2: std_logic; signal iwcount_3: std_logic; signal co0_3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; signal iwcount_4: std_logic; signal co2_1: std_logic; signal co1_3: std_logic; @@ -73,9 +77,13 @@ architecture Structure of fifo_19x16 is signal ircount_0: std_logic; signal ircount_1: std_logic; signal r_ctr_ci: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; signal ircount_2: std_logic; signal ircount_3: std_logic; signal co0_4: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; signal ircount_4: std_logic; signal co2_2: std_logic; signal co1_4: std_logic; @@ -92,61 +100,15 @@ architecture Structure of fifo_19x16 is signal co1_5: std_logic; signal fcount_4: std_logic; signal af_d: std_logic; + signal scuba_vhi: std_logic; signal scuba_vlo: std_logic; signal af_d_c: std_logic; - signal rdataout18: std_logic; - signal rdataout17: std_logic; - signal rdataout16: std_logic; - signal scuba_vhi: std_logic; - signal rdataout15: std_logic; - signal rdataout14: std_logic; - signal rdataout13: std_logic; - signal rdataout12: std_logic; - signal rdataout11: std_logic; - signal rdataout10: std_logic; - signal rdataout9: std_logic; - signal rdataout8: std_logic; - signal rdataout7: std_logic; - signal rdataout6: std_logic; - signal rdataout5: std_logic; - signal rdataout4: std_logic; - signal rdataout3: std_logic; - signal rdataout2: std_logic; - signal rdataout1: std_logic; - signal rdataout0: std_logic; - signal rcount_3: std_logic; - signal rcount_2: std_logic; - signal rcount_1: std_logic; - signal rcount_0: std_logic; - signal dec0_wre3: std_logic; - signal wcount_3: std_logic; - signal wcount_2: std_logic; - signal wcount_1: std_logic; - signal wcount_0: std_logic; - attribute GSR : string; - attribute MEM_INIT_FILE : string; attribute MEM_LPC_FILE : string; - attribute COMP : string; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; + attribute MEM_INIT_FILE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_19x16.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; attribute GSR of FF_17 : label is "ENABLED"; attribute GSR of FF_16 : label is "ENABLED"; attribute GSR of FF_15 : label is "ENABLED"; @@ -165,21 +127,6 @@ architecture Structure of fifo_19x16 is attribute GSR of FF_2 : label is "ENABLED"; attribute GSR of FF_1 : label is "ENABLED"; attribute GSR of FF_0 : label is "ENABLED"; - attribute MEM_INIT_FILE of fifo_pfu_0_0 : label is "(0-15)(0-3)"; - attribute MEM_LPC_FILE of fifo_pfu_0_0 : label is "fifo_19x16.lpc"; - attribute COMP of fifo_pfu_0_0 : label is "fifo_pfu_0_0"; - attribute MEM_INIT_FILE of fifo_pfu_0_1 : label is "(0-15)(4-7)"; - attribute MEM_LPC_FILE of fifo_pfu_0_1 : label is "fifo_19x16.lpc"; - attribute COMP of fifo_pfu_0_1 : label is "fifo_pfu_0_1"; - attribute MEM_INIT_FILE of fifo_pfu_0_2 : label is "(0-15)(8-11)"; - attribute MEM_LPC_FILE of fifo_pfu_0_2 : label is "fifo_19x16.lpc"; - attribute COMP of fifo_pfu_0_2 : label is "fifo_pfu_0_2"; - attribute MEM_INIT_FILE of fifo_pfu_0_3 : label is "(0-15)(12-15)"; - attribute MEM_LPC_FILE of fifo_pfu_0_3 : label is "fifo_19x16.lpc"; - attribute COMP of fifo_pfu_0_3 : label is "fifo_pfu_0_3"; - attribute MEM_INIT_FILE of fifo_pfu_0_4 : label is "(0-15)(16-19)"; - attribute MEM_LPC_FILE of fifo_pfu_0_4 : label is "fifo_19x16.lpc"; - attribute COMP of fifo_pfu_0_4 : label is "fifo_pfu_0_4"; attribute syn_keep : boolean; attribute NGD_DRC_MASK : integer; attribute NGD_DRC_MASK of Structure : architecture is 1; @@ -210,21 +157,16 @@ begin INV_5: INV port map (A=>wren_i, Z=>wren_i_inv); - LUT4_2: ROM16X1A + LUT4_1: ROM16X1A generic map (initval=> X"3232") port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, AD0=>empty_i, DO0=>empty_d); - LUT4_1: ROM16X1A + LUT4_0: ROM16X1A generic map (initval=> X"3232") port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, AD0=>full_i, DO0=>full_d); - LUT4_0: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>scuba_vhi, AD2=>wren_i, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec0_wre3); - AND2_t0: AND2 port map (A=>rden_i, B=>invout_0, Z=>r_nw); @@ -243,148 +185,109 @@ begin INV_0: INV port map (A=>fcnt_en_inv, Z=>fcnt_en_inv_inv); - FF_36: FD1P3DX + pdp_ram_0_0_0: PDPW16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "ENABLED", + RESETMODE=> "ASYNC", REGMODE=> "NOREG", DATA_WIDTH_R=> 36, + DATA_WIDTH_W=> 36) + port map (DI35=>scuba_vlo, DI34=>scuba_vlo, DI33=>scuba_vlo, + DI32=>scuba_vlo, DI31=>scuba_vlo, DI30=>scuba_vlo, + DI29=>scuba_vlo, DI28=>scuba_vlo, DI27=>scuba_vlo, + DI26=>scuba_vlo, DI25=>scuba_vlo, DI24=>scuba_vlo, + DI23=>scuba_vlo, DI22=>scuba_vlo, DI21=>scuba_vlo, + DI20=>scuba_vlo, DI19=>scuba_vlo, DI18=>Data(18), + DI17=>Data(17), DI16=>Data(16), DI15=>Data(15), + DI14=>Data(14), DI13=>Data(13), DI12=>Data(12), + DI11=>Data(11), DI10=>Data(10), DI9=>Data(9), DI8=>Data(8), + DI7=>Data(7), DI6=>Data(6), DI5=>Data(5), DI4=>Data(4), + DI3=>Data(3), DI2=>Data(2), DI1=>Data(1), DI0=>Data(0), + ADW8=>scuba_vlo, ADW7=>scuba_vlo, ADW6=>scuba_vlo, + ADW5=>scuba_vlo, ADW4=>scuba_vlo, ADW3=>wcount_3, + ADW2=>wcount_2, ADW1=>wcount_1, ADW0=>wcount_0, + BE3=>scuba_vhi, BE2=>scuba_vhi, BE1=>scuba_vhi, + BE0=>scuba_vhi, CEW=>wren_i, CLKW=>Clock, CSW2=>scuba_vlo, + CSW1=>scuba_vlo, CSW0=>scuba_vhi, ADR13=>scuba_vlo, + ADR12=>scuba_vlo, ADR11=>scuba_vlo, ADR10=>scuba_vlo, + ADR9=>scuba_vlo, ADR8=>rcount_3, ADR7=>rcount_2, + ADR6=>rcount_1, ADR5=>rcount_0, ADR4=>scuba_vlo, + ADR3=>scuba_vlo, ADR2=>scuba_vlo, ADR1=>scuba_vlo, + ADR0=>scuba_vlo, CER=>rden_i, OCER=>rden_i, CLKR=>Clock, + CSR2=>scuba_vlo, CSR1=>scuba_vlo, CSR0=>scuba_vlo, + RST=>Reset, DO35=>Q(17), DO34=>Q(16), DO33=>Q(15), + DO32=>Q(14), DO31=>Q(13), DO30=>Q(12), DO29=>Q(11), + DO28=>Q(10), DO27=>Q(9), DO26=>Q(8), DO25=>Q(7), DO24=>Q(6), + DO23=>Q(5), DO22=>Q(4), DO21=>Q(3), DO20=>Q(2), DO19=>Q(1), + DO18=>Q(0), DO17=>open, DO16=>open, DO15=>open, DO14=>open, + DO13=>open, DO12=>open, DO11=>open, DO10=>open, DO9=>open, + DO8=>open, DO7=>open, DO6=>open, DO5=>open, DO4=>open, + DO3=>open, DO2=>open, DO1=>open, DO0=>Q(18)); + + FF_17: FD1P3DX port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, Q=>fcount_0); - FF_35: FD1P3DX + FF_16: FD1P3DX port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, Q=>fcount_1); - FF_34: FD1P3DX + FF_15: FD1P3DX port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, Q=>fcount_2); - FF_33: FD1P3DX + FF_14: FD1P3DX port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, Q=>fcount_3); - FF_32: FD1P3DX + FF_13: FD1P3DX port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, Q=>fcount_4); - FF_31: FD1S3BX + FF_12: FD1S3BX port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i); - FF_30: FD1S3DX + FF_11: FD1S3DX port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i); - FF_29: FD1P3DX + FF_10: FD1P3DX port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wcount_0); - FF_28: FD1P3DX + FF_9: FD1P3DX port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wcount_1); - FF_27: FD1P3DX + FF_8: FD1P3DX port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wcount_2); - FF_26: FD1P3DX + FF_7: FD1P3DX port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wcount_3); - FF_25: FD1P3DX + FF_6: FD1P3DX port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wcount_4); - FF_24: FD1P3DX + FF_5: FD1P3DX port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rcount_0); - FF_23: FD1P3DX + FF_4: FD1P3DX port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rcount_1); - FF_22: FD1P3DX + FF_3: FD1P3DX port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rcount_2); - FF_21: FD1P3DX + FF_2: FD1P3DX port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rcount_3); - FF_20: FD1P3DX + FF_1: FD1P3DX port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rcount_4); - FF_19: FD1P3DX - port map (D=>rdataout0, SP=>rden_i, CK=>Clock, CD=>Reset, - Q=>Q(0)); - - FF_18: FD1P3DX - port map (D=>rdataout1, SP=>rden_i, CK=>Clock, CD=>Reset, - Q=>Q(1)); - - FF_17: FD1P3DX - port map (D=>rdataout2, SP=>rden_i, CK=>Clock, CD=>Reset, - Q=>Q(2)); - - FF_16: FD1P3DX - port map (D=>rdataout3, SP=>rden_i, CK=>Clock, CD=>Reset, - Q=>Q(3)); - - FF_15: FD1P3DX - port map (D=>rdataout4, SP=>rden_i, CK=>Clock, CD=>Reset, - Q=>Q(4)); - - FF_14: FD1P3DX - port map (D=>rdataout5, SP=>rden_i, CK=>Clock, CD=>Reset, - Q=>Q(5)); - - FF_13: FD1P3DX - port map (D=>rdataout6, SP=>rden_i, CK=>Clock, CD=>Reset, - Q=>Q(6)); - - FF_12: FD1P3DX - port map (D=>rdataout7, SP=>rden_i, CK=>Clock, CD=>Reset, - Q=>Q(7)); - - FF_11: FD1P3DX - port map (D=>rdataout8, SP=>rden_i, CK=>Clock, CD=>Reset, - Q=>Q(8)); - - FF_10: FD1P3DX - port map (D=>rdataout9, SP=>rden_i, CK=>Clock, CD=>Reset, - Q=>Q(9)); - - FF_9: FD1P3DX - port map (D=>rdataout10, SP=>rden_i, CK=>Clock, CD=>Reset, - Q=>Q(10)); - - FF_8: FD1P3DX - port map (D=>rdataout11, SP=>rden_i, CK=>Clock, CD=>Reset, - Q=>Q(11)); - - FF_7: FD1P3DX - port map (D=>rdataout12, SP=>rden_i, CK=>Clock, CD=>Reset, - Q=>Q(12)); - - FF_6: FD1P3DX - port map (D=>rdataout13, SP=>rden_i, CK=>Clock, CD=>Reset, - Q=>Q(13)); - - FF_5: FD1P3DX - port map (D=>rdataout14, SP=>rden_i, CK=>Clock, CD=>Reset, - Q=>Q(14)); - - FF_4: FD1P3DX - port map (D=>rdataout15, SP=>rden_i, CK=>Clock, CD=>Reset, - Q=>Q(15)); - - FF_3: FD1P3DX - port map (D=>rdataout16, SP=>rden_i, CK=>Clock, CD=>Reset, - Q=>Q(16)); - - FF_2: FD1P3DX - port map (D=>rdataout17, SP=>rden_i, CK=>Clock, CD=>Reset, - Q=>Q(17)); - - FF_1: FD1P3DX - port map (D=>rdataout18, SP=>rden_i, CK=>Clock, CD=>Reset, - Q=>Q(18)); - FF_0: FD1S3DX port map (D=>af_d, CK=>Clock, CD=>Reset, Q=>AlmostFull); @@ -581,6 +484,9 @@ begin B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co1_5, S0=>open, S1=>open, COUT=>af_d_c); + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + scuba_vlo_inst: VLO port map (Z=>scuba_vlo); @@ -591,54 +497,6 @@ begin B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, CIN=>af_d_c, S0=>af_d, S1=>open, COUT=>open); - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - fifo_pfu_0_0: DPR16X4C - generic map (initval=> "0x0000000000000000") - port map (DI0=>Data(16), DI1=>Data(17), DI2=>Data(18), - DI3=>scuba_vhi, WCK=>Clock, WRE=>dec0_wre3, RAD0=>rcount_0, - RAD1=>rcount_1, RAD2=>rcount_2, RAD3=>rcount_3, - WAD0=>wcount_0, WAD1=>wcount_1, WAD2=>wcount_2, - WAD3=>wcount_3, DO0=>rdataout16, DO1=>rdataout17, - DO2=>rdataout18, DO3=>open); - - fifo_pfu_0_1: DPR16X4C - generic map (initval=> "0x0000000000000000") - port map (DI0=>Data(12), DI1=>Data(13), DI2=>Data(14), - DI3=>Data(15), WCK=>Clock, WRE=>dec0_wre3, RAD0=>rcount_0, - RAD1=>rcount_1, RAD2=>rcount_2, RAD3=>rcount_3, - WAD0=>wcount_0, WAD1=>wcount_1, WAD2=>wcount_2, - WAD3=>wcount_3, DO0=>rdataout12, DO1=>rdataout13, - DO2=>rdataout14, DO3=>rdataout15); - - fifo_pfu_0_2: DPR16X4C - generic map (initval=> "0x0000000000000000") - port map (DI0=>Data(8), DI1=>Data(9), DI2=>Data(10), - DI3=>Data(11), WCK=>Clock, WRE=>dec0_wre3, RAD0=>rcount_0, - RAD1=>rcount_1, RAD2=>rcount_2, RAD3=>rcount_3, - WAD0=>wcount_0, WAD1=>wcount_1, WAD2=>wcount_2, - WAD3=>wcount_3, DO0=>rdataout8, DO1=>rdataout9, - DO2=>rdataout10, DO3=>rdataout11); - - fifo_pfu_0_3: DPR16X4C - generic map (initval=> "0x0000000000000000") - port map (DI0=>Data(4), DI1=>Data(5), DI2=>Data(6), DI3=>Data(7), - WCK=>Clock, WRE=>dec0_wre3, RAD0=>rcount_0, RAD1=>rcount_1, - RAD2=>rcount_2, RAD3=>rcount_3, WAD0=>wcount_0, - WAD1=>wcount_1, WAD2=>wcount_2, WAD3=>wcount_3, - DO0=>rdataout4, DO1=>rdataout5, DO2=>rdataout6, - DO3=>rdataout7); - - fifo_pfu_0_4: DPR16X4C - generic map (initval=> "0x0000000000000000") - port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), - WCK=>Clock, WRE=>dec0_wre3, RAD0=>rcount_0, RAD1=>rcount_1, - RAD2=>rcount_2, RAD3=>rcount_3, WAD0=>wcount_0, - WAD1=>wcount_1, WAD2=>wcount_2, WAD3=>wcount_3, - DO0=>rdataout0, DO1=>rdataout1, DO2=>rdataout2, - DO3=>rdataout3); - WCNT(0) <= fcount_0; WCNT(1) <= fcount_1; WCNT(2) <= fcount_2; diff --git a/special/trb2_control_endpoint_tlk.vhd b/oldfiles/trb2_control_endpoint_tlk.vhd similarity index 100% rename from special/trb2_control_endpoint_tlk.vhd rename to oldfiles/trb2_control_endpoint_tlk.vhd diff --git a/special/trb_net16_ethernet_bridge.vhd b/oldfiles/trb_net16_ethernet_bridge.vhd similarity index 100% rename from special/trb_net16_ethernet_bridge.vhd rename to oldfiles/trb_net16_ethernet_bridge.vhd diff --git a/special/trb_net_bridge_acromag_apl.vhd b/oldfiles/trb_net_bridge_acromag_apl.vhd similarity index 100% rename from special/trb_net_bridge_acromag_apl.vhd rename to oldfiles/trb_net_bridge_acromag_apl.vhd diff --git a/special/trb_net_bridge_acromag_endpoint.vhd b/oldfiles/trb_net_bridge_acromag_endpoint.vhd similarity index 100% rename from special/trb_net_bridge_acromag_endpoint.vhd rename to oldfiles/trb_net_bridge_acromag_endpoint.vhd diff --git a/special/trb_net_bridge_etrax_apl.vhd b/oldfiles/trb_net_bridge_etrax_apl.vhd similarity index 100% rename from special/trb_net_bridge_etrax_apl.vhd rename to oldfiles/trb_net_bridge_etrax_apl.vhd diff --git a/special/trb_net_bridge_etrax_endpoint.vhd b/oldfiles/trb_net_bridge_etrax_endpoint.vhd similarity index 100% rename from special/trb_net_bridge_etrax_endpoint.vhd rename to oldfiles/trb_net_bridge_etrax_endpoint.vhd diff --git a/special/spi_ltc2600.vhd b/special/spi_ltc2600.vhd index a1fdca5..b99f0de 100644 --- a/special/spi_ltc2600.vhd +++ b/special/spi_ltc2600.vhd @@ -63,6 +63,9 @@ architecture spi_ltc2600_arch of spi_ltc2600 is signal word_length : integer range 0 to BITS := BITS; signal wait_cycles : integer range 0 to 1023 := WAITCYCLES; + + attribute syn_ramstyle : string; + attribute syn_ramstyle of ram : signal is "block_ram"; begin diff --git a/trb_net16_hub_ipu_logic.vhd b/trb_net16_hub_ipu_logic.vhd index 16a3bc3..d573392 100644 --- a/trb_net16_hub_ipu_logic.vhd +++ b/trb_net16_hub_ipu_logic.vhd @@ -604,10 +604,11 @@ begin hdrram_address(i*3+1 downto i*3) <= REPLY_PACKET_NUM_IN((i)*c_NUM_WIDTH+1 downto i*c_NUM_WIDTH); hdrram_address(i*3+2) <= '1' when current_reply_reading_DHDR(i)='1' else '0'; - the_last_HDR_RAM : ram_dp_rw + the_last_HDR_RAM : entity work.ram_dp_rw generic map( depth => 3, - width => 16 + width => 16, + ramstyle => "block_ram" ) port map( CLK => CLK,