From: Tobias Weber <toweber86@gmail.com>
Date: Tue, 22 Aug 2017 16:14:35 +0000 (+0200)
Subject: multicycle for hitbus_timeout
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=a841bdfcaa02950ee727ff1838a5543a78e3b41a;p=trb3.git

multicycle for hitbus_timeout
---

diff --git a/base/trb3_periph_mupix.lpf b/base/trb3_periph_mupix.lpf
index 2c802ed..93426e5 100644
--- a/base/trb3_periph_mupix.lpf
+++ b/base/trb3_periph_mupix.lpf
@@ -374,3 +374,4 @@ IOBUF GROUP "not_connected_group" IO_TYPE=LVCMOS25;
 ##Relax some timing constraints
 ###########################################################
 #MULTICYCLE FROM CELL "MuPix3_Board_*/board_interface_1/hbus_from_mupix_sync" TO CELL "MuPix3_Board_*/HitbusHistogram_1/hitbus_buffer" 2 X;
+MULTICYCLE FROM CELL "MuPix3_Board_*/TimeWalkWithFiFo_1/hitbus_timeout_slow_sync*" TO CELL "MuPix3_Board_*/TimeWalkWithFiFo_1/hitbus_timeout_fast_sync*" 2 X;
\ No newline at end of file
diff --git a/mupix/sources/TimeWalk.vhd b/mupix/sources/TimeWalk.vhd
index 018f038..1b61d3f 100644
--- a/mupix/sources/TimeWalk.vhd
+++ b/mupix/sources/TimeWalk.vhd
@@ -21,8 +21,8 @@ end entity TimeWalk;
 
 architecture TimeWalk_Arch of TimeWalk is
 
-  signal latencycounter            : unsigned(15 downto 0)        := (others => '0');
-  signal hitbuscounter             : unsigned(15 downto 0)        := (others => '0');
+  signal latencycounter            : unsigned(11 downto 0)        := (others => '0');
+  signal hitbuscounter             : unsigned(11 downto 0)        := (others => '0');
   signal hitbus_delayed            : std_logic := '0';
   signal hitbus_edge               : std_logic_vector(1 downto 0) := (others => '0');
   signal szintillator_trigger_edge : std_logic_vector(1 downto 0) := (others => '0');
@@ -91,14 +91,14 @@ begin  -- architecture TimeWalk_Arch
              latencycounter <= latencycounter + 1;
              if hitbus_edge = "01" then
               timewalk_fsm  <= measurehitbus;
-             elsif latencycounter = unsigned(hitbus_timeout) then
+             elsif latencycounter = unsigned(hitbus_timeout) or latencycounter = to_unsigned(4095, 12) then
               timewalk_fsm <= idle;
              else
               timewalk_fsm <= waitforhitbus;
              end if;
            when measurehitbus =>
               hitbuscounter <= hitbuscounter + 1;
-              if hitbus_edge = "10" then
+              if hitbus_edge = "10" or hitbuscounter = to_unsigned(4095, 12) then
                 timewalk_fsm <= measurement_done;
               else
                 timewalk_fsm  <= measurehitbus;
@@ -106,7 +106,7 @@ begin  -- architecture TimeWalk_Arch
            when measurement_done =>
               timewalk_fsm <= idle;
               if readyToWrite = '1' then
-                measurementData        <= std_logic_vector(latencycounter & hitbuscounter);
+                measurementData        <= std_logic_vector("0000" & latencycounter & "0000" & hitbuscounter);
                 measurementFinished    <= '1';
               end if;
            end case;
diff --git a/mupix/sources/TimeWalkWithFiFo.vhd b/mupix/sources/TimeWalkWithFiFo.vhd
index d1adc2c..7aa1b99 100644
--- a/mupix/sources/TimeWalkWithFiFo.vhd
+++ b/mupix/sources/TimeWalkWithFiFo.vhd
@@ -35,6 +35,14 @@ architecture TimeWalk_arch of TimeWalkWithFiFo is
 
   constant bitsBeforeWriteCounter : integer := 2;
   signal hitbus_timeout            : std_logic_vector(15 downto 0)        := x"0024";
+  
+  signal hitbus_timeout_slow_sync  : std_logic_vector(15 downto 0);
+  signal hitbus_timeout_fast_sync : std_logic_vector(15 downto 0);
+  
+  attribute syn_preserve : boolean;
+  attribute syn_keep : boolean;
+  attribute syn_keep of hitbus_timeout_slow_sync, hitbus_timeout_fast_sync : signal is true;
+  attribute syn_preserve of hitbus_timeout_slow_sync, hitbus_timeout_fast_sync : signal is true;
 
   signal resetcounters : std_logic := '0';
   signal hitbusEdgeCounter : unsigned(31 downto 0) := (others => '0');
@@ -97,12 +105,36 @@ begin  -- architecture TimeWalk_arch
       clk                  => fast_clk,
       reset                => reset,
       hitbus               => hitbus_fast,
-      hitbus_timeout       => hitbus_timeout,
+      hitbus_timeout       => hitbus_timeout_fast_sync,
       szintillator_trigger => szintillator_trigger_fast,
       readyToWrite         => not FiFo_full,
       measurementFinished  => FiFo_Wren,
       measurementData      => FiFo_data_in);
 
+
+  trb_slow_sync : process (trb_slv_clock) is
+  begin
+  	if rising_edge(trb_slv_clock) then
+  		if reset = '1' then
+  			hitbus_timeout_slow_sync <= (others => '0');
+  		else
+  			hitbus_timeout_slow_sync <= hitbus_timeout;
+  		end if;
+  	end if;
+  end process trb_slow_sync;
+  
+  fast_clk_sync : process (fast_clk) is
+  begin
+  	if rising_edge(fast_clk) then
+  		if reset = '1' then
+  			hitbus_timeout_fast_sync <= (others => '0');
+  		else
+  			hitbus_timeout_fast_sync <= hitbus_timeout_slow_sync;
+  		end if;
+  	end if;
+  end process fast_clk_sync;
+  
+
   ------------------------------------------------------------
   --count number of rising edges on szintilator and hitbus
   ------------------------------------------------------------