From: Your Name <you@example.com>
Date: Thu, 23 Nov 2017 14:48:39 +0000 (+0100)
Subject: added diamond project file, AR + AP
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=a89f36a40810d212aedabab0ae08cb052950673a;p=padiwa.git

added diamond project file, AR + AP
---

diff --git a/amps2/amps2.ldf b/amps2/amps2.ldf
new file mode 100644
index 0000000..7287f20
--- /dev/null
+++ b/amps2/amps2.ldf
@@ -0,0 +1,35 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<BaliProject version="3.2" title="amps2" device="LCMXO3LF-6900C-6BG256C" default_implementation="amps2">
+    <Options/>
+    <Implementation title="amps2" dir="amps2" description="amps2" synthesis="synplify" default_strategy="Strategy1">
+        <Options def_top="spi_slave" top="padiwa_amps2"/>
+        <Source name="../source/Stretcher_A.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../source/Stretcher_B.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../source/Stretcher.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../source/pwm.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../cores/pll_in133_out33_133_266.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../source/spi_slave.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="padiwa_amps2.vhd" type="VHDL" type_short="VHDL">
+            <Options top_module="padiwa_amps2"/>
+        </Source>
+        <Source name="../pinout/padiwa_amps2.lpf" type="Logic Preference" type_short="LPF">
+            <Options/>
+        </Source>
+    </Implementation>
+    <Strategy name="Strategy1" file="amps21.sty"/>
+</BaliProject>